CN109786271A - A kind of three-dimensional stacking encapsulation method and structure - Google Patents
A kind of three-dimensional stacking encapsulation method and structure Download PDFInfo
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- CN109786271A CN109786271A CN201811640475.1A CN201811640475A CN109786271A CN 109786271 A CN109786271 A CN 109786271A CN 201811640475 A CN201811640475 A CN 201811640475A CN 109786271 A CN109786271 A CN 109786271A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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Abstract
The invention discloses three-dimensional stacking encapsulation method and structures, this method comprises: attaching conductive structure and the first chip, and first surface the first support plate of direction of conductive structure on the surface of the first support plate；Wherein, conductive structure has at least one conductive metal wire of perforation first surface and second surface, and the first surface of conductive structure is disposed with the first metallic circuit layer and first medium layer；The first molding layer is formed in the first surface of the first support plate；The second metallic circuit layer is formed in the first molding layer surface；The second chip is attached in the second metallic circuit layer surface.The present invention realizes that the solder joint of the second chip is fanned out to setting by conductive structure, conductive structure second surface pre-sets the first metallic circuit and is electrically connected with inner conductive metal wire, due to not being related to being fanned out to technique, when the support plate for making conductive structure uses inorganic medium, first metallic circuit can be done sufficiently fine, to which when the solder joint of the second chip is more and intensive, conductive structure overall volume can be smaller.
Description
Technical field
The present invention relates to technical field of electronic encapsulation, and in particular to a kind of three-dimensional stacking encapsulation method and structure.
Background technique
Three-dimensional stacked encapsulation is to stack at least layers of chips to be arranged and encapsulated, by encapsulating between usual each layer
Intracorporal conductive structure realizes electric signal connection, and in order to reduce the intracorporal number of conductive structures of encapsulation, it will usually it is led in cladding
Wiring layer is arranged in the surface of the molding layer of electric structure.
Existing three-dimensional stacking encapsulation method, generally includes following steps: interim bonded layer 2 is formed on support plate 1, interim
The first wiring layer 3 is formed on bonded layer 2, and the first mould of cladding the first chip 5 and conductive structure 4 is formed on the first wiring layer 3
Sealing 6, as shown in Figure 1A；Second wiring layer 7 is set on the surface of the first molding layer 6, the is then arranged on the second wiring layer 7
Two chips 8, and the second molding layer 9 of the second chip 8 of cladding is formed, as shown in Figure 1B.
However, it is found by the inventors that being fanned out to (English: Fan Out) work since the first wiring layer 3 and the second wiring layer 7 belong to
Skill, and be usually to be initially formed dielectric layer, metallic circuit is then formed on dielectric layer.The characteristic for being fanned out to technique and dielectric layer is determined
The metallic circuit for having determined the first wiring layer 3 and the second wiring layer 7 can not be made sufficiently thin, and conductive knot is located at especially on wiring layer
The metallic circuit at structure both ends, this to be packaged it using the above method when the solder joint of the second chip 8 is more and intensive
When, the overall volume of used conductive structure is larger.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of three-dimensional stacking encapsulation method and structure, to solve on wiring layer
The thicker problem of metallic circuit positioned at conductive structure both ends.
According in a first aspect, the embodiment of the invention provides a kind of three-dimensional stacking encapsulation methods, comprising: in the first support plate
First surface attaches conductive structure and the first chip, and the first surface of the conductive structure is towards first support plate；Wherein,
At least one conductive metal wire of the conductive structure with perforation first surface and second surface, the first of the conductive structure
Surface is disposed with the first metallic circuit layer and first medium layer, at least portion of metallic circuit in the first metallic circuit layer
Divide and be electrically connected with conductive metal wire, the first medium layer exposes at least portion of metallic circuit in the first metallic circuit layer
Point；The first molding layer is formed in the first surface of first support plate, the first molding layer coats first chip, and wraps
The side wall of the conductive structure is covered, and exposes the conductive metal thread end on the conductive structure second surface；Described first
Molding layer surface forms the second metallic circuit layer, and metallic circuit at least partly leads with exposing in the second metallic circuit layer
The electrical connection of electric metal thread end；The second chip, the salient point court of second chip are attached in the second metallic circuit layer surface
It is at least partly electrically connected to first chip, and with metallic circuit in the second metallic circuit layer.
Optionally, the solder joint of first chip is towards first support plate；The method also includes: remove described first
Support plate；Second dielectric layer is set on the surface for originally attaching first support plate, the second dielectric layer exposes first core
Metallic circuit is at least partly on the solder joint of piece and the conductive structure first surface；The is formed in the second medium layer surface
Three metallic circuit layers, metallic circuit is at least partly revealed with the conductive structure first surface in the third metallic circuit layer
At least partly electrical connection of metallic circuit out；Third dielectric layer, the third are formed in the third metallic circuit layer surface
Dielectric layer exposes in the third metallic circuit metallic circuit at least partly；Expose the position of metallic circuit on third dielectric layer
Set plant ball.
Optionally, the making step of the conductive structure includes: that the substrate of inorganic is temporarily bonded in the second support plate
On；Conductive metal is punched and is filled in hole at least one predetermined position on the substrate, forms conductive metal wire；Described
Substrate surface forms the first metallic circuit layer, in the first metallic circuit layer metallic circuit at least partly with conductive metal wire
Electrical connection；First medium layer is formed in the first metallic circuit layer surface, the first medium layer exposes first metal
Metallic circuit is at least partly in line layer；Remove the second support plate；Cutting as needed, obtains conductive structure.
Optionally, when the step for attaching the second chip in the first metallic circuit layer surface, second chip
At least partly salient point it is corresponding with the position of conductive metal wire in the conductive structure.
Optionally, described to form third dielectric layer in the third metallic circuit layer surface, the third dielectric layer exposes
In the third metallic circuit when step of the part of metallic circuit, exposes in the position of metallic circuit and at least partly led with described
The position of conductive metal wire is corresponding in electric structure.
Optionally, described includes: described second the step of the second metallic circuit layer surface attaches the second chip
Metallic circuit layer surface forms the 4th dielectric layer, and the 4th dielectric layer exposes metallic circuit in the second metallic circuit layer
Part；The salient point of second chip is arranged in the position for exposing metallic circuit on the one or four dielectric layer.
Optionally, described includes: by the second chip the step of the second metallic circuit layer surface attaches the second chip
Salient point be correspondingly arranged at expose metallic circuit position；It is filled out between second chip and the second metallic circuit layer
Glue.
According to second aspect, the embodiment of the invention provides a kind of three-dimensional stacked encapsulating structures, comprising: the first chip；The
One molding layer coats first chip；And expose the contact that is electrically connected of first chip；Conductive structure has perforation first
At least one conductive metal wire on surface and second surface, the first surface of the conductive structure are disposed with the first metal wire
Road floor and first medium floor, metallic circuit is at least partly electrically connected with conductive metal wire in the first metallic circuit layer, institute
It states first medium layer and exposes in the first metallic circuit layer metallic circuit at least partly；Conductive structure perforation described the
One molding layer, and the metallic circuit that first medium layer is exposed in the conductive structure is in a side surface of the first molding layer
Expose, the conductive metal thread end of the conductive structure second surface exposes in another side surface of the first molding layer；The
Two metallic circuit layers are set to the surface of the first molding layer, and are located at the second surface side of the conductive structure, described
Metallic circuit is at least partly electrically connected with the conductive metal thread end of exposing in second metallic circuit layer；Second chip, setting
In the first metallic circuit layer surface, and the salient point of second chip is towards first chip, and with second gold medal
Belong at least partly electrical connection of metallic circuit in line layer.
Optionally, the solder joint of first chip is towards first support plate；The structure further include: second dielectric layer,
It is set to the surface of the first molding layer, and is located at the first surface side of the conductive structure, the second dielectric layer dew
Metallic circuit is at least partly on the solder joint of first chip and the conductive structure first surface out；Third metallic circuit
Layer, is set to the second medium layer surface, and metallic circuit is at least partly led with described in the third metallic circuit layer
At least partly electrical connection for the metallic circuit that electric structure first surface is exposed；Third dielectric layer is set to the third metal
Route layer surface, the third dielectric layer expose in the third metallic circuit metallic circuit at least partly；Soldered ball is set to
Expose the position of metallic circuit on the third dielectric layer.
Optionally, the position pair of at least partly salient point of second chip and conductive metal wire in the conductive structure
It answers；And/or on the third dielectric layer expose metallic circuit position at least partly with conductive metal in the conductive structure
The position of line is corresponding.
Three-dimensional stacking encapsulation method and structure provided by the embodiment of the present invention realize the second chip by conductive structure
Solder joint is fanned out to setting, and the second surface of conductive structure pre-sets the conductive metal inside the first metallic circuit and conductive structure
Line electrical connection, due to not being related to being fanned out to technique, when the support plate for making conductive structure uses inorganic medium, the first metallic circuit energy
That enough does is sufficiently fine, so that conductive structure overall volume can be smaller when the solder joint of the second chip is more and intensive.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Figure 1A and Figure 1B shows the obtained structural schematic diagram of part steps of existing three-dimensional stacking encapsulation method；
Fig. 2 shows a kind of flow charts of three-dimensional stacking encapsulation method according to an embodiment of the present invention；
Fig. 3 shows the flow chart of another three-dimensional stacking encapsulation method according to an embodiment of the present invention；
The part steps that Fig. 4 A to Fig. 4 M shows three-dimensional stacking encapsulation method according to an embodiment of the present invention are obtained
Structural schematic diagram；
Fig. 5 A to Fig. 5 E shows the step of conductive structure production method according to an embodiment of the present invention obtained structure
Schematic diagram；
Fig. 6 shows a kind of flow chart of the production method of conductive structure according to an embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
Embodiment one
The present invention provides a kind of three-dimensional stacked encapsulating structures, and as shown in fig. 4m, which includes the
One chip 40, the first molding layer 50, conductive structure 30, the second metallic circuit layer 61, the second chip 70.
First molding layer 50 coats the first chip 40, and exposes the contact that is electrically connected of the first chip 40.The weldering of first chip 40
Point can be towards the second chip 70 (as shown in fig. 4m), then the contact that is electrically connected of the first chip 40 exposed can be weldering
Disk or salient point；Alternatively, the solder joint of the first chip 40 can also be directed away from the direction of the second chip 70, then exposed first
The contact that is electrically connected of chip 40 can be the electrical connection drawn after being electrically connected by metal routing with the solder joint of the first chip 40
Point.
Conductive structure 30 has at least one conductive metal wire 32 of perforation first surface and second surface, conductive structure 30
First surface be disposed with the first metallic circuit layer 33 and first medium layer 34, metallic circuit in the first metallic circuit layer 33
Be at least partly electrically connected with conductive metal wire 32, first medium layer 34 expose the first metallic circuit layer 33 in metallic circuit extremely
Small part.
Conductive structure 30 penetrates through the first molding layer 50, and the metallic circuit that first medium layer 34 is exposed in conductive structure 30
Expose in a side surface of the first molding layer 50,32 end of conductive metal wire of 30 second surface of conductive structure is in the first molding layer
Expose 50 another side surface.
Second metallic circuit layer 61 is set to the surface of the first molding layer 50, and is located at the second surface one of conductive structure 30
Side, metallic circuit is at least partly electrically connected with the conductive metal thread end of exposing in the second metallic circuit layer 61.
Second chip 70 is set to 33 surface of the first metallic circuit layer, and salient point the first chip of direction of the second chip 70
40, and be at least partly electrically connected with metallic circuit in the second metallic circuit layer 61.
Above-mentioned three-dimensional stacked fan-out packaging structure realizes that the solder joint of the second chip is fanned out to setting by conductive structure, conductive
The second surface of structure pre-sets the first metallic circuit and is electrically connected with the conductive metal wire inside conductive structure, due to not relating to
And it is fanned out to technique, when the support plate for making conductive structure uses inorganic medium, the first metallic circuit can be done sufficiently fine, thus
When the solder joint of the second chip is more and intensive, conductive structure overall volume can be smaller.
Optionally, for the solder joint of the first chip 40 towards the first support plate 10, which further includes second Jie
Matter layer 90, third metallic circuit layer 100, third dielectric layer 110 and soldered ball 120.
Second dielectric layer 90 is set to the surface of the first molding layer 50, and is located at the first surface side of conductive structure 30,
Second dielectric layer 90 expose the first chip 40 30 first surface of solder joint and conductive structure on metallic circuit at least partly.
Third metallic circuit layer 100 is set to 90 surface of second dielectric layer, and metallic circuit in third metallic circuit layer 100
The metallic circuit that is at least partly exposed with 30 first surface of conductive structure be at least partly electrically connected.
Third dielectric layer 110 is set to 100 surface of third metallic circuit layer, and third dielectric layer 110 exposes third metal wire
Metallic circuit is at least partly in road 100.
Soldered ball 120 is set to the position for exposing metallic circuit on third dielectric layer 110.
Optionally, at least partly salient point of the second chip 70 is corresponding with the position of conductive metal wire in conductive structure 30, or
Person exposes the position in the position of metallic circuit at least partly with conductive metal wire 32 in conductive structure 30 on third dielectric layer 110
Set correspondence.
Embodiment two
Fig. 2 shows a kind of flow chart of three-dimensional stacking encapsulation method according to an embodiment of the present invention, this method can be used
The three-dimensional stacked encapsulating structure described in production embodiment one or its any optional embodiment.As shown in Fig. 2, this method packet
Include following steps:
S101: conductive structure and the first chip, and the first surface of conductive structure are attached in the first surface of the first support plate
Towards the first support plate；Wherein, conductive structure has at least one conductive metal wire of perforation first surface and second surface, conductive
The first surface of structure is disposed with the first metallic circuit layer and first medium layer, metallic circuit in the first metallic circuit layer
At least partly be electrically connected with conductive metal wire, first medium layer expose the first metallic circuit layer in metallic circuit at least partly.
Step S101 can be as shown in Fig. 4 A to Fig. 4 B: interim bonded layer 20 first is set on the surface of the first support plate 10,
Conductive structure 30 and the first chip 40 are attached on interim bonded layer again；It can also be by other means by conductive structure 30
With 40 Direct Bonding of the first chip on support plate 10.The application does not limit specific attaching method herein.
S102: the first molding layer is formed in the first surface of the first support plate, the first molding layer coats the first chip, and coats
The side wall of conductive structure, and expose the conductive metal thread end on conductive structure second surface.
As shown in Figure 4 D, 50 be the first molding layer.
It should be noted that step S102 is after the first surface of the first support plate 10 forms the first molding layer 50, this
One molding layer 50 may not necessarily expose conductive metal thread end (as shown in Figure 4 C) in conductive structure 30, at this time can be by other hands
Section makes its exposing, such as makes its exposing by way of grinding and being thinned, or conductive structure is removed by way of laser drill
The first molding layer material that conductive metal thread end is covered in 30.The application is to making " and to expose on conductive structure second surface
Conductive metal thread end " expose method without limitation.
S103: forming the second metallic circuit layer in the first molding layer surface, and metallic circuit is extremely in the second metallic circuit layer
Small part is electrically connected with the conductive metal thread end of exposing.
As shown in Figure 4 E, 61 be the second metallic circuit layer, which can be by physically or chemically depositing
Method, such as evaporation, sputtering, plating, change plating, first in the first molding layer 50 surface deposition, one layer of metal, metal is generally copper,
It can be other metals, such as aluminium, tungsten, then one layer of metallic circuit is formed by the method for photoetching.It should be noted that the application
To formed metallic circuit layer method without limitation.
S104: attaching the second chip in the second metallic circuit layer surface, the salient point of the second chip towards the first chip, and with
At least partly electrical connection of metallic circuit in second metallic circuit layer.
For example, as shown in Figure 4 G, 61 surface of the second metallic circuit layer attach the second chip 70, the salient point of the second chip with
The metallic circuit of second metallic circuit layer 61 is electrically connected.
Optionally, step S104, which can be, first forms the 4th dielectric layer 62 on 61 surface of the second metallic circuit layer, and the 4th is situated between
Matter layer 62 exposes the part of metallic circuit in the second metallic circuit layer 61, and then the salient point setting of the second chip 70 is situated between the 4th
Expose the position of metallic circuit on matter layer 62, as shown in Figure 4 G.
Alternatively, step S104 is also possible to that the salient point of the second chip 70 is first correspondingly arranged to the position for exposing metallic circuit
It sets, then the filler between the second chip 70 and the second metallic circuit layer 61.
The above-mentioned three-dimensional stacked method for being fanned out to encapsulation is realized that the solder joint of the second chip is fanned out to setting by conductive structure, is led
The second surface of electric structure pre-sets the first metallic circuit and is electrically connected with the conductive metal wire inside conductive structure, due to not
It is related to being fanned out to technique, when the support plate for making conductive structure uses inorganic medium, the first metallic circuit can be done sufficiently fine, from
And when the solder joint of the second chip is more and intensive, conductive structure overall volume can be smaller.
Embodiment three
Fig. 3 shows the flow chart of another three-dimensional stacking encapsulation method according to an embodiment of the present invention, and this method can be with
For making three-dimensional stacked encapsulating structure described in embodiment one or its any optional embodiment.As shown in figure 3, this method
Include the following steps:
S201: conductive structure and the first chip, and the first surface of conductive structure are attached in the first surface of the first support plate
Towards the first support plate, solder joint the first support plate of direction of the first chip；Wherein, conductive structure has perforation first surface and the second table
At least one conductive metal wire in face, the first surface of conductive structure are disposed with the first metallic circuit layer and first medium
Layer, metallic circuit at least partly be electrically connected with conductive metal wire in the first metallic circuit layer, first medium layer the first gold medal of exposing
Belong to line layer in metallic circuit at least partly.
The step specifically refers to step S101, and details are not described herein.
S202: the first molding layer is formed in the first surface of the first support plate, the first molding layer coats the first chip, and coats
The side wall of conductive structure, and expose the conductive metal thread end on conductive structure second surface.
The step specifically refers to step S102, and details are not described herein.
S203: forming the second metallic circuit layer in the first molding layer surface, and metallic circuit is extremely in the second metallic circuit layer
Small part is electrically connected with the conductive metal thread end of exposing.
The step specifically refers to step S103, and details are not described herein.
S204: attaching the second chip in the second metallic circuit layer surface, the salient point of the second chip towards the first chip, and with
At least partly electrical connection of metallic circuit in second metallic circuit layer.
The step specifically refers to step S104, and details are not described herein.
S205: the second molding layer is formed in the second metallic circuit layer surface, which coats the second chip.
As shown at figure 4h, 80 be the second molding layer.
S206: the first support plate is removed.
S207: third support plate is temporarily bonded in the second molding layer surface.
As shown in fig. 41,130 be third support plate, and 140 be interim bonded layer.
S208: second dielectric layer is set on the surface for originally attaching the first support plate, second dielectric layer exposes the first chip
Metallic circuit is at least partly on solder joint and conductive structure first surface.
As shown in fig. 4j, 90 be second dielectric layer.
S209: forming third metallic circuit layer in second medium layer surface, and metallic circuit is extremely in third metallic circuit layer
The metallic circuit that small part is exposed with conductive structure first surface is at least partly electrically connected.
As shown in Figure 4 K, 100 be third metallic circuit layer.
S210: third dielectric layer is formed in third metallic circuit layer surface, third dielectric layer exposes third metallic circuit layer
Middle metallic circuit is at least partly.
As illustrated in fig. 4l, 110 be third dielectric layer.
S211: ball is planted in the position for exposing metallic circuit on third dielectric layer.
As shown in fig. 4m, 120 be soldered ball.
S212: third support plate is removed.
The above-mentioned three-dimensional stacked method for being fanned out to encapsulation is realized that the solder joint of the second chip is fanned out to setting by conductive structure, is led
The second surface of electric structure pre-sets the first metallic circuit and is electrically connected with the conductive metal wire inside conductive structure, due to not
It is related to being fanned out to technique, when the support plate for making conductive structure uses inorganic medium, the first metallic circuit can be done sufficiently fine, from
And when the solder joint of the second chip is more and intensive, conductive structure overall volume can be smaller.
Optionally, for step S204 when the second metallic circuit layer surface attaches the step of the second chip, the second chip is extremely
Small part salient point is corresponding with the position of conductive metal wire in conductive structure.
Optionally, step S210 forms third dielectric layer in third metallic circuit layer surface, and third dielectric layer exposes third
In metallic circuit layer when the part of metallic circuit, expose in the position of metallic circuit at least partly with conductive metal in conductive structure
The position of line is corresponding.
Example IV
Fig. 6 shows a kind of flow chart of the production method of conductive structure according to an embodiment of the present invention, and this method can be with
For making conductive structure described in embodiment two or embodiment three, as shown in fig. 6, this method comprises the following steps:
S301: the substrate of inorganic is temporarily bonded on the second support plate.
As shown in Figure 5A, a is the second support plate, and b is interim bonded layer, and 31 be the substrate of inorganic.
S302: conductive metal is punched and is filled in hole at least one predetermined position on substrate, forms conductive metal wire.
As shown in Figure 5 B, 31 be conductive metal wire.
S303: forming the first metallic circuit layer in substrate surface, and metallic circuit is at least partly in the first metallic circuit layer
It is electrically connected with conductive metal wire.
As shown in Figure 5 C, 33 be the first metallic circuit layer.
S304: first medium layer is formed in the first metallic circuit layer surface, first medium layer exposes the first metallic circuit layer
Middle metallic circuit is at least partly.
As shown in Figure 5 D, 34 be first medium layer.
S305: the second support plate is removed.
S306: cutting as needed obtains conductive structure.
As shown in Figure 5 D, it can be cut the position of dotted line along figure, the conductive structure obtained after cutting is as shown in fig. 5e.
Although being described in detail about example embodiment and its advantage, those skilled in the art can not departed from
Various change, replacement are carried out to these embodiments in the case where spirit of the invention and protection scope defined in the appended claims
And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability
The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention
Change.
In addition, application range of the invention is not limited to the technique, mechanism, system of specific embodiment described in specification
It makes, material composition, means, method and step.From the disclosure, will be easy as those skilled in the art
Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or
Step, wherein they execute the function that the corresponding embodiment described with the present invention is substantially the same or the knot that acquisition is substantially the same
Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system
It makes, material composition, means, method or step are included in its protection scope.
Claims (10)
1. a kind of three-dimensional stacking encapsulation method characterized by comprising
Conductive structure and the first chip are attached in the first surface of the first support plate, and the first surface of the conductive structure is towards institute
State the first support plate；Wherein, the conductive structure has at least one conductive metal wire of perforation first surface and second surface, institute
The first surface for stating conductive structure is disposed with the first metallic circuit layer and first medium layer, in the first metallic circuit layer
Metallic circuit is at least partly electrically connected with conductive metal wire, and the first medium layer exposes gold in the first metallic circuit layer
Belong to route at least partly；
The first molding layer is formed in the first surface of first support plate, the first molding layer coats first chip, and
The side wall of the conductive structure is coated, and exposes the conductive metal thread end on the conductive structure second surface；
The second metallic circuit layer is formed in the first molding layer surface, metallic circuit is at least in the second metallic circuit layer
Part is electrically connected with the conductive metal thread end of exposing；
Attach the second chip in the second metallic circuit layer surface, the salient point of second chip towards first chip,
And it is at least partly electrically connected with metallic circuit in the second metallic circuit layer.
2. three-dimensional stacking encapsulation method according to claim 1, which is characterized in that the solder joint of first chip is towards institute
State the first support plate；The method also includes:
Remove first support plate；
Second dielectric layer is set on the surface for originally attaching first support plate, the second dielectric layer exposes first chip
Solder joint and the conductive structure first surface on metallic circuit at least partly；
Third metallic circuit layer is formed in the second medium layer surface, metallic circuit is at least in the third metallic circuit layer
The metallic circuit that part is exposed with the conductive structure first surface is at least partly electrically connected；
Third dielectric layer is formed in the third metallic circuit layer surface, the third dielectric layer exposes the third metallic circuit
Middle metallic circuit is at least partly；
Plant ball in the position for exposing metallic circuit on third dielectric layer.
3. three-dimensional stacking encapsulation method according to claim 1, which is characterized in that the making step packet of the conductive structure
It includes:
The substrate of inorganic is temporarily bonded on the second support plate；
Conductive metal is punched and is filled in hole at least one predetermined position on the substrate, forms conductive metal wire；
Form the first metallic circuit layer in the substrate surface, in the first metallic circuit layer metallic circuit at least partly with
Conductive metal wire electrical connection；
First medium layer is formed in the first metallic circuit layer surface, the first medium layer exposes first metallic circuit
Layer in metallic circuit at least partly；
Remove the second support plate；
Cutting as needed, obtains conductive structure.
4. three-dimensional stacking encapsulation method according to claim 1, which is characterized in that described in the first metallic circuit layer
When surface attaches the step of the second chip, conductive metal wire in at least partly salient point and the conductive structure of second chip
Position it is corresponding.
5. three-dimensional stacking encapsulation method according to claim 2, which is characterized in that described in the third metallic circuit layer
The step of surface forms third dielectric layer, and the third dielectric layer exposes the part of metallic circuit in the third metallic circuit
When, expose at least partly corresponding with the position of conductive metal wire in the conductive structure in the position of metallic circuit.
6. three-dimensional stacking encapsulation method according to claim 1, which is characterized in that described in the second metallic circuit layer
Surface attach the second chip the step of include:
The 4th dielectric layer is formed in the second metallic circuit layer surface, the 4th dielectric layer exposes second metallic circuit
The part of metallic circuit in layer；
The salient point of second chip is arranged in the position for exposing metallic circuit on the one or four dielectric layer.
7. three-dimensional stacking encapsulation method according to claim 1, which is characterized in that described in the second metallic circuit layer
Surface attach the second chip the step of include:
The salient point of second chip is correspondingly arranged to the position for exposing metallic circuit；
The filler between second chip and the second metallic circuit layer.
8. a kind of three-dimensional stacked encapsulating structure characterized by comprising
First chip；
First molding layer coats first chip；And expose the contact that is electrically connected of first chip；
Conductive structure, has an at least one conductive metal wire of perforation first surface and second surface, and the of the conductive structure
One surface is disposed with the first metallic circuit layer and first medium layer, and metallic circuit is at least in the first metallic circuit layer
Part is electrically connected with conductive metal wire, and the first medium layer exposes at least portion of metallic circuit in the first metallic circuit layer
Point；
The conductive structure penetrates through the first molding layer, and the metallic circuit that first medium layer is exposed in the conductive structure
Expose in a side surface of the first molding layer, the conductive metal thread end of the conductive structure second surface is described first
Expose another side surface of molding layer；
Second metallic circuit layer is set to the surface of the first molding layer, and is located at the second surface one of the conductive structure
Side, metallic circuit is at least partly electrically connected with the conductive metal thread end of exposing in the second metallic circuit layer；
Second chip, is set to the first metallic circuit layer surface, and the salient point of second chip is towards first core
Piece, and be at least partly electrically connected with metallic circuit in the second metallic circuit layer.
9. three-dimensional stacked encapsulating structure according to claim 7, which is characterized in that the solder joint of first chip is towards institute
State the first support plate；The structure further include:
Second dielectric layer is set to the surface of the first molding layer, and is located at the first surface side of the conductive structure, institute
It states second dielectric layer and exposes on the solder joint and the conductive structure first surface of first chip metallic circuit at least partly；
Third metallic circuit layer is set to the second medium layer surface, and metallic circuit in the third metallic circuit layer
The metallic circuit at least partly exposed with the conductive structure first surface is at least partly electrically connected；
Third dielectric layer, is set to the third metallic circuit layer surface, and the third dielectric layer exposes the third metal wire
Metallic circuit is at least partly in road；
Soldered ball is set to the position for exposing metallic circuit on the third dielectric layer.
10. three-dimensional stacked encapsulating structure according to claim 8, which is characterized in that second chip is at least partly
Salient point is corresponding with the position of conductive metal wire in the conductive structure；And/or
On the third dielectric layer expose metallic circuit position at least partly with conductive metal wire in the conductive structure
Position is corresponding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811640475.1A CN109786271A (en) | 2018-12-29 | 2018-12-29 | A kind of three-dimensional stacking encapsulation method and structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811640475.1A CN109786271A (en) | 2018-12-29 | 2018-12-29 | A kind of three-dimensional stacking encapsulation method and structure |
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Citations (5)
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|---|---|---|---|---|
| US20110024916A1 (en) * | 2008-12-01 | 2011-02-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias |
| US20130182402A1 (en) * | 2012-01-18 | 2013-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | PoP Structures Including Through-Assembly Via Modules |
| US20150359098A1 (en) * | 2012-12-26 | 2015-12-10 | Hana Micron Inc. | Circuit Board Having Interposer Embedded Therein, Electronic Module Using Same, and Method for Manufacturing Same |
| US9490167B2 (en) * | 2012-10-11 | 2016-11-08 | Taiwan Semiconductor Manufactoring Company, Ltd. | Pop structures and methods of forming the same |
| US20180308824A1 (en) * | 2012-09-10 | 2018-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device with Discrete Blocks |
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2018
- 2018-12-29 CN CN201811640475.1A patent/CN109786271A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110024916A1 (en) * | 2008-12-01 | 2011-02-03 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias |
| US20130182402A1 (en) * | 2012-01-18 | 2013-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | PoP Structures Including Through-Assembly Via Modules |
| US20180308824A1 (en) * | 2012-09-10 | 2018-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device with Discrete Blocks |
| US9490167B2 (en) * | 2012-10-11 | 2016-11-08 | Taiwan Semiconductor Manufactoring Company, Ltd. | Pop structures and methods of forming the same |
| US20150359098A1 (en) * | 2012-12-26 | 2015-12-10 | Hana Micron Inc. | Circuit Board Having Interposer Embedded Therein, Electronic Module Using Same, and Method for Manufacturing Same |
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Application publication date: 20190521 |