CN109767740A - Shift register, gate driving circuit and driving method thereof, and display device - Google Patents

Abstract

The invention discloses a shift register, a gate driving circuit and a driving method thereof, and a display device, comprising: a first input control module connected between a first node, a first signal input terminal and a first reference signal terminal, A second input control module connected between the first node, the second signal input terminal and the second reference signal terminal, and an output control module connected between the first node and the gate signal output terminal, further comprising: A first signal output termination module between the input control module and the first reference signal terminal, a second signal output termination module between the second input control module and the second reference signal terminal, and a signal connected to the first node Output switching unit. Through the cooperation of the above modules, it is possible to select any row between the start row and the end row of the shift register to output the scan signal, thereby realizing the selection of the panel resolution, reducing power consumption and prolonging the standby time.

Description

Shift register, gate driving circuit and driving method thereof, and display device

technical field

The present invention relates to the field of display technology, and in particular, to a shift register, a gate driving circuit and a driving method thereof, and a display device.

Background technique

In a thin film transistor display, a gate driving signal is usually provided to the gate of each thin film transistor (TFT, Thin Film Transistor) in a pixel area through a gate driving device. The gate driving device can be formed on the array substrate of the display through an array process, that is, the gate driver on array (GOA) process of the array substrate. The symmetrical and beautiful design also saves the bonding area of the gate integrated circuit (IC, Integrated Circuit) and the wiring space of the fan-out (Fan-out), so that the design of the narrow frame can be realized; and, This integrated process can also eliminate the bonding process in the gate scan line direction, thereby improving productivity and yield.

At present, the replacement of mobile products is extremely fast, and the products are developing towards the trend of thinness, refinement and ultra-long standby time. From the perspective of customer experience, the requirements for the screen frame are getting narrower and longer, and the standby time is longer. Therefore, the development of a panel design with strong driving capability, lower power consumption and longer standby time has a great effect on improving the competitiveness of display device performance.

After the resolution of the traditional GOA circuit is determined, it can only scan from the first row of gate lines to the end of the last row of gate lines. No matter what the actual demand for display is, it must be scanned and displayed from the start row to the end row. As the resolution of our mobile products is getting higher and higher, the power consumption also increases with the increase of resolution, resulting in a great reduction in the standby time of display products. Therefore, how to improve the standby time of the display product is a technical problem that needs to be solved urgently by those skilled in the art.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention provide a shift register, a gate driving circuit and a driving method thereof, and a display device, which can realize the selection of any row between the start row and the end row of the shift register and output a scan signal , so as to realize the selection of panel resolution, reduce power consumption and prolong standby time.

Therefore, an embodiment of the present invention provides a shift register, including: a first input control module connected between a first node, a first signal input terminal and a first reference signal terminal, connected to the first node, A second input control module between the second signal input terminal and the second reference signal terminal, and an output control module connected between the first node and the gate signal output terminal, further comprising: located at the first input A first signal output termination module between the control module and the first reference signal terminal, a second signal output termination module between the second input control module and the second reference signal terminal, and the a signal output switching unit connected to the first node; wherein,

The first signal output termination module is configured to terminate the connection between the first reference signal terminal and the first input control module under the control of the signal output termination terminal signal;

The second signal output termination module is configured to terminate the connection between the second reference signal terminal and the second input control module under the control of the signal output termination terminal signal;

The signal output switching unit includes: a signal output selection module, a signal output trigger module and a signal output reset module; wherein,

The signal output selection module is configured to provide the signal of the signal output selection terminal to the second node under the control of the gate signal output terminal signal;

The signal output trigger module is configured to provide the signal of the trigger signal terminal to the first node under the control of the second node;

The signal output reset module is configured to provide the signal of the third reference signal terminal to the second node under the control of the reset signal terminal signal.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, the first signal output termination module specifically includes: a first switch transistor; wherein,

The gate of the first switching transistor is connected to the signal output terminal, the first pole is connected to the first reference signal terminal, and the second pole is connected to the first input control module.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, the second signal output termination module specifically includes: a second switch transistor; wherein,

The gate of the second switching transistor is connected to the signal output terminal, the first pole is connected to the second reference signal terminal, and the second pole is connected to the second input control module.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, the signal output selection module specifically includes: a third switch transistor; wherein,

The gate of the third switching transistor is connected to the gate signal output terminal, the first pole is connected to the signal output selection terminal, and the second pole is connected to the second node.

In a possible implementation manner, during specific implementation, in the above-mentioned shift register provided in the embodiment of the present invention, the signal output reset module specifically includes: a fourth switch transistor; wherein,

The gate of the fourth switch transistor is connected to the reset signal terminal, the first pole is connected to the third reference signal terminal, and the second pole is connected to the second node.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, the signal output trigger module specifically includes: a fifth switch transistor and a capacitor; wherein,

the gate of the fifth switch transistor is connected to the second node, the first pole is connected to the trigger signal terminal, and the second pole is connected to the first node;

The first end of the capacitor is connected to the second node, and the second end is connected to the first node.

In a possible implementation manner, during specific implementation, the above-mentioned shift register provided in the embodiment of the present invention further includes: a sixth switch transistor; wherein,

the gate of the sixth switching transistor is connected to the second terminal of the capacitor, the first pole is connected to the third reference signal terminal, and the second pole is connected to the first node; it is used for connecting to the second node The signal of the third reference signal terminal is provided to the first node under the control of the .

Correspondingly, an embodiment of the present invention also provides a gate drive circuit, including a plurality of the above-mentioned shift registers provided in the embodiments of the present invention in cascade; wherein,

Except the last stage shift register, the gate signal output end of each stage shift register is connected to the first signal input end of its adjacent next stage shift register;

Except for the first stage shift register, the gate signal output terminal of each stage shift register is connected to the second signal input terminal of the adjacent previous stage shift register.

Correspondingly, an embodiment of the present invention further provides a display device including the above-mentioned gate driving circuit provided by the embodiment of the present invention.

Correspondingly, the embodiment of the present invention also provides a driving method for the gate driving circuit provided by the embodiment of the present invention, including:

When it is determined to scan the full-screen gate line, input a low-potential signal to the trigger signal terminal;

When it is determined to scan the gate lines of the m-th row to the n-th row, a high-level signal is input to the signal output selection terminal of the m-th row shift register, and a low-level signal is input to the signal output terminal of the n-th row shift register, wherein , 1≤m<n.

The beneficial effects of the present invention are as follows:

A shift register, a gate driving circuit and a driving method thereof, and a display device provided by the embodiments of the present invention include: a first input control connected between a first node, a first signal input terminal and a first reference signal terminal The module, the second input control module connected between the first node, the second signal input terminal and the second reference signal terminal, and the output control module connected between the first node and the gate signal output terminal, further comprising: a first signal output termination module located between the first input control module and the first reference signal terminal, a second signal output termination module located between the second input control module and the second reference signal terminal, and connected to the first node The signal output switching unit. Through the cooperation of the above modules, it is possible to select any row between the start row and the end row of the shift register to output the scan signal, thereby realizing the selection of the panel resolution, reducing power consumption and prolonging the standby time.

Description of drawings

1 is one of the schematic structural diagrams of a shift register provided by an embodiment of the present invention;

2 is a second schematic structural diagram of a shift register provided by an embodiment of the present invention;

Fig. 3 is an input and output timing diagram corresponding to the shift register shown in Fig. 2;

Fig. 4 is another input and output timing diagram corresponding to the shift register shown in Fig. 2;

FIG. 5 is an input and output timing diagram corresponding to the gate drive circuit provided by the embodiment of the present invention;

FIG. 6 is another input and output timing diagram corresponding to the gate driving circuit provided by the embodiment of the present invention.

Detailed ways

The specific implementations of the shift register, the gate driving circuit and the driving method thereof, and the display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

A shift register provided by an embodiment of the present invention, as shown in FIG. 1 , includes: a first input control device connected between a first node A, a first signal input terminal OUT _N-1 and a first reference signal terminal CN Module 1, connected to the second input control module 2 between the first node A, the second signal input terminal OUT _N+1 and the second reference signal terminal CNB, and connected to the first node A and the gate signal output terminal Out The output control module 3 between _N further includes: a first signal output termination module 4 located between the first input control module 1 and the first reference signal terminal CN, located between the second input control module 2 and the second reference signal terminal A second signal output termination module 5 between CNBs, and a signal output switch unit connected to the first node A; wherein,

The first signal output termination module 4 is configured to terminate the connection between the first reference signal terminal CN and the first input control module 1 under the control of the signal output terminal CGE signal;

The second signal output termination module 5 is configured to terminate the connection between the second reference signal terminal CNB and the second input control module 2 under the control of the signal output termination terminal CGE signal;

The signal output switching unit includes: a signal output selection module 6, a signal output trigger module 7 and a signal output reset module 8; wherein,

The signal output selection module 6 is configured to provide the signal of the signal output selection terminal CGI to the second node B under the control of the gate signal output terminal Out _N signal;

The signal output trigger module 7 is configured to provide the signal of the trigger signal terminal CGS to the first node A under the control of the second node B;

The signal output reset module 8 is configured to provide the signal of the third reference signal terminal VGL to the second node B under the control of the reset signal terminal CGR signal.

The shift register provided by the embodiment of the present invention includes: a first input control module connected between the first node, the first signal input terminal and the first reference signal terminal, and connected to the first node, the second signal input terminal and the first reference signal terminal. A second input control module between the two reference signal terminals, and an output control module connected between the first node and the gate signal output terminal, further comprising: a second input control module located between the first input control module and the first reference signal terminal A first signal output termination module, a second signal output termination module located between the second input control module and the second reference signal terminal, and a signal output switch unit connected to the first node. Through the cooperation of the above modules, it is possible to select any row between the start row and the end row of the shift register to output the scan signal, thereby realizing the selection of the panel resolution, reducing power consumption and prolonging the standby time.

In the specific implementation, as shown in FIG. 1 , the first signal input terminal of the shift register N of the current stage is connected to the gate signal output terminal OUT N-1 of the shift register N-1 of the previous stage, and the shift register N-1 of the current stage is connected to the gate signal output terminal OUT _N-1 The second signal input terminal of the bit register N is connected to the gate signal output terminal OUT _N+1 of the shift register N+1 of the next stage. The above-mentioned shift register provided by the embodiment of the present invention can realize forward scanning and reverse scanning modes. When the forward scanning mode is adopted, the signal of the first reference signal terminal CN is a high-level signal, and the signal of the second reference signal terminal CNB is a low-level signal; when the reverse scanning mode is used, the signal of the first reference signal terminal CN is a low-level signal, and the signal of the second reference signal terminal CNB is a high-level signal. When forward scanning is used, the signal output from the gate signal output terminal OUT _N+1 of the next stage shift register N+1 resets the current stage shift register N; when reverse scanning is used, the previous stage shifts The signal output from the gate signal output terminal OUT _N-1 of the register N-1 resets the shift register N of this stage.

The present invention will be described in detail below with reference to specific embodiments. It should be noted that this embodiment is for better explaining the present invention, but does not limit the present invention.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the first signal output termination module 4 specifically includes: a first switch transistor M1; wherein ,

The gate of the first switching transistor M1 is connected to the signal output terminal CGE, the first pole is connected to the first reference signal terminal CN, and the second pole is connected to the first input control module 1 .

The above is only an example to illustrate the specific structure of the first signal output termination module in the shift register. During specific implementation, the specific structure of the first signal output termination module is not limited to the above-mentioned structure provided in the embodiment of the present invention, and may also be a technology in the art. Other structures known to personnel are not limited here.

In a possible implementation, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the second signal output termination module 5 specifically includes: a second switch transistor M2; wherein ,

The gate of the second switching transistor M2 is connected to the signal output terminal CGE, the first pole is connected to the second reference signal terminal CNB, and the second pole is connected to the second input control module 2 .

The above is only an example to illustrate the specific structure of the second signal output termination module in the shift register. During specific implementation, the specific structure of the second signal output termination module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be a technology in the art. Other structures known to personnel are not limited here.

In a possible implementation, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the signal output selection module 6 specifically includes: a third switch transistor M3; wherein,

The gate of the third switching transistor M3 is connected to the gate signal output terminal Out _N , the first pole is connected to the signal output selection terminal CGI, and the second pole is connected to the second node B.

Specifically, after the resolution of the conventional shift register circuit is determined, it can only scan from the gate line of the first row to the end of the gate line of the last row. No matter what the actual demand of the display is, it must scan from the starting row to the ending row. All scans are carried out to display, because the resolution of our mobile products is getting higher and higher, the power consumption also increases with the increase of resolution, resulting in a great reduction in the standby time of display products. For example, we only need to watch the time and weather information on the screen for a long time, and do not need to display it in other places, while the traditional screen is full-screen display, which consumes a lot of power; for example, the time and weather information on the screen only needs to display a few lines , such as the third row to the eighth row, the signal output selection module in the signal output switching unit in the shift register provided by the embodiment of the present invention can scan the third row through the signal output selection terminal CGI input high potential The signal charges the second node B. Due to the bootstrapping effect of the capacitor C, the potential of the second node B remains high until the third row of the next frame is scanned, so that it can be switched to scan from the 3rd row to the 8th row. .

The above is only an example to illustrate the specific structure of the signal output selection module in the shift register. During specific implementation, the specific structure of the signal output selection module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art. The structure is not limited here.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the signal output reset module 8 specifically includes: a fourth switch transistor M4; wherein,

The gate of the fourth switching transistor M4 is connected to the reset signal terminal CGR, the first pole is connected to the third reference signal terminal VGL, and the second pole is connected to the second node B.

Specifically, the function of the signal output reset module is to select only certain rows in the cascaded multiple shift registers to scan and output the gate signal, for example, from the third row to the eighth row, that is, the third row to the eighth row. The 8th line is one cycle. After scanning for several cycles, the scan ends, and the shift register scans from the first line to the last line. Then, before the next selection from the 3rd line to the 8th line, the second node B must be scanned. The potential is reset, that is, the fourth switch transistor M4 is turned on under the control of the high-level signal of the reset signal terminal CGR, the low-level signal of the third reference signal terminal VGL is input to the second node B, and the signal of the second node B is a low-level signal. , does not affect the operation of the shift register.

The above is only an example to illustrate the specific structure of the signal output reset module in the shift register. During specific implementation, the specific structure of the signal output reset module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art. The structure is not limited here.

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the signal output trigger module 7 specifically includes: a fifth switch transistor M5 and a capacitor C; in,

the gate of the fifth switch transistor M5 is connected to the second node B, the first pole is connected to the trigger signal terminal CGS, and the second pole is connected to the first node A;

The first end of the capacitor C is connected to the second node B, and the second end is connected to the first node A.

Specifically, in the embodiment of the present invention, when the signal output selection module 4 selects to scan from a certain row, the signal output trigger module 5 inputs a high-potential signal to the first node A at the trigger signal terminal CGS to charge the first node A, so as to carry out Scanning of the shift register.

The above is only an example to illustrate the specific structure of the signal output trigger module in the shift register. During specific implementation, the specific structure of the signal output trigger module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. The structure is not limited here.

In a possible implementation manner, during the specific implementation, since the second end of the capacitor C is connected to the source and drain of each switching transistor, this will affect the function of the capacitor C to store charges. Therefore, in order to improve the capacity of the capacitor C to store charges Capability, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , further includes: a sixth switch transistor M6; wherein,

The sixth switching transistor M6, the gate of which is connected to the second end of the capacitor C, the first pole is connected to the fourth reference signal terminal VGH, and the second pole is connected to the first node A; used under the control of the second node B The signal of the fourth reference signal terminal VGH is supplied to the first node A.

In a possible implementation, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the first input control module 1 specifically includes: a seventh switch transistor M7; wherein,

The gate of the seventh switch transistor M7 is connected to the first signal input terminal OUT _N-1 , the first pole is connected to the second pole of the first switch transistor M1, and the second pole is connected to the first node A.

The above is only an example to illustrate the specific structure of the first input control module in the shift register. During specific implementation, the specific structure of the first input control module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be known by those skilled in the art. Other structures are not limited here.

In a possible implementation, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the second input control module 2 specifically includes: an eighth switch transistor M8; wherein,

The gate of the eighth switch transistor M8 is connected to the second signal input terminal OUT _N+1 , the first pole is connected to the second pole of the second switch transistor M2, and the second pole is connected to the first node A.

The above is only an example to illustrate the specific structure of the second input control module in the shift register. During the specific implementation, the specific structure of the second input control module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and can also be known by those skilled in the art. Other structures are not limited here.

During specific implementation, the above-mentioned shift register provided in the embodiment of the present invention, as shown in FIG. 1 , further includes: a node control module 9 , a second output module 10 and a reset module 11 .

In a possible implementation, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the node control module 9 specifically includes: a ninth switch transistor M9 and a tenth switch transistor M10, the eleventh switch transistor M11, the twelfth switch transistor M12 and the second capacitor C2; wherein,

The ninth switch transistor M9, its gate and first pole are both connected to the first clock signal terminal CK, and the second pole is connected to the third node D;

The tenth switch transistor M10, the gate of which is connected to the third node D, the first pole is connected to the first node A, and the second pole is connected to the third reference signal terminal VGL;

The eleventh switch transistor M11, the gate of which is connected to the first node A, the first pole is connected to the third node D, and the second pole is connected to the third reference signal terminal VGL;

The twelfth switch transistor M12, the gate of which is connected to the gate signal output terminal Out _N of the shift register of this stage, the first pole is connected to the third node D, and the second pole is connected to the third reference signal terminal VGL;

The first end of the second capacitor C2 is connected to the third node D, and the second end thereof is connected to the third reference signal end VGL.

In specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, the size of the eleventh switch transistor is generally set to be larger than the size of the ninth switch transistor during process preparation, so that when the potential of the first node is set When the voltage level is high, the rate at which the eleventh switch transistor provides the signal of the second reference signal terminal to the third node under the control of the signal of the first node is greater than that of the ninth switch transistor under the control of the first clock signal terminal to supply the first clock signal. The rate at which the signal at the signal terminal is supplied to the third node, thereby ensuring that the potential of the third node is at a low potential.

The above is only an example to illustrate the specific structure of the node control module in the shift register. During specific implementation, the specific structure of the node control module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may also be other structures known to those skilled in the art. It is not limited here.

In a possible implementation, in the above-mentioned shift register provided in the embodiment of the present invention, as shown in FIG. 2 , the output control module 3 specifically includes: a thirteenth switch transistor M13 and a third capacitor C3; where,

The thirteenth switching transistor M13, the gate of which is connected to the first node A, the first pole is connected to the second clock signal terminal CKB, and the second pole is connected to the gate signal output terminal Out _N of the shift register of this stage;

The first end of the third capacitor C3 is connected to the first node A, and the second end is connected to the gate signal output end Out _N of the shift register of this stage.

The above is only an example to illustrate the specific structure of the output control module in the shift register. During the specific implementation, the specific structure of the output control module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and can also be other structures known to those skilled in the art. It is not limited here.

In a possible implementation, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the second output module 10 specifically includes: a fourteenth switch transistor M14; wherein,

The gate of the fourteenth switch transistor M14 is connected to the third node D, the first pole is connected to the gate signal output terminal Out _N of the shift register of this stage, and the second pole is connected to the third reference signal terminal VGL.

The above is only an example to illustrate the specific structure of the second output module in the shift register. During specific implementation, the specific structure of the second output module is not limited to the above-mentioned structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art. The structure is not limited here.

In a possible implementation, in the specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , the second reset module 11 specifically includes: a fifteenth switch transistor M15; wherein,

The gate and first pole of the fifteenth switching transistor M15 are both connected to the second reset signal terminal RST, and the second pole is connected to the third node D.

Specifically, the role of the second reset module is to turn on the fifteenth switch transistor M15 under the control of the high-level signal of the second reset signal terminal RST before the first row of the shift registers of the cascaded multiple shift registers starts scanning, The high-level signal of the second reset signal terminal RST is input to the third node D to charge the third node D, the fourteenth switch transistor M14 is turned on, and the low-level signal of the third reference signal terminal VGL is input to the gate signal output terminal Out _N , the gate signal output terminal Out _N is reset, so as not to affect the progressive scanning of the cascaded multiple shift registers.

The above is only an example to illustrate the specific structure of the second reset module in the shift register. During specific implementation, the specific structure of the second reset module is not limited to the above-mentioned structure provided by the embodiments of the present invention, and may also be other structures known to those skilled in the art. The structure is not limited here.

It should be noted that the switching transistor mentioned in the above embodiments of the present invention may be a thin film transistor (TFT, Thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor), which is not limited herein.

During specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, as shown in FIG. 2 , all switch transistors are N-type transistors; the potential of the third reference signal terminal VGL is a low potential, and the fourth reference signal terminal The potential of VGH is a high potential.

Of course, during specific implementation, in the above-mentioned shift register provided by the embodiment of the present invention, all switch transistors may also be P-type transistors.

Further, in specific implementation, the N-type transistor is turned on under the action of a high potential and turned off under the action of a low potential; the P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential.

It should be noted that the first electrode of the switching transistor mentioned in the above embodiments of the present invention may be the source electrode and the second electrode may be the drain electrode, or the first electrode may be the drain electrode and the second electrode may be the source electrode, which will not be described in detail here. distinguish.

In the following, a working process of switching from full-screen scanning to designated line scanning of the shift register provided by the embodiment of the present invention is described by taking forward scanning as an example with reference to the circuit timing diagram. In the following description, 1 represents a high-level signal, and 0 represents a low-level signal.

Taking the shift register shown in FIG. 2 as an example, in FIG. 2 , all the switching transistors M1 are N-type transistors. The input and output timing process of switching from scanning the full-screen gate lines to scanning the gate lines from the 3rd row to the 8th row is described in detail, and the corresponding input and output timing sequences are shown in FIG. 3 and FIG. 4 . RST in Fig. 3 and Fig. 4 indicates that before the shift register of the first row is triggered (that is, before STV is high, STV is the initial trigger signal of the shift register), the gate signal output terminal of the shift register is reset, In order to ensure the normal output of the shift register; the input and output timings of Figure 3 and Figure 4 provided by the embodiment of the present invention are for bilateral driving, CKL and CKBL represent the clock signal terminal on the left, CKR and CKBR represent the clock signal terminal on the right, The signal of the first reference signal terminal CN is a high level signal, the signal of the second reference signal terminal CNB is a low level signal, the level of the third reference signal terminal VGL is a low level, and the level of the fourth reference signal terminal VGH is a high level.

The embodiment of the present invention takes forward scanning as an example to illustrate the working principle of switching from scanning the full screen to scanning from the 3rd line to the 8th line. When the current frame is full-screen scanning, the next frame is scanning from the 3rd line to the 8th line. Line 8, that is, the start line of the next frame, the start line of line 3, the end line of line 8, and the cycle of lines 3 to 8, which are continuously scanned for several cycles according to the display needs. When switching the resolution scanning, the work of specifying the specific initial line and the end line of the shift register is divided into two stages. The first stage: the resolution switching trigger frame T1, which is a normal one-frame scan (scanning from the first line To the last line), since the next frame needs to be scanned from the 3rd line, the resolution switching trigger stage T1 needs to cooperate with the signal of the signal output selection terminal CGI to designate the 3rd line shift register of the next frame as the initial line; the second line Stage: Resolution switching display stage T2, with the signal output selection terminal CGI, signal output trigger terminal CGS, signal output termination CGE and reset signal terminal CGR, the resolution display can be switched, and the start line and end line according to the specified behavior. Progressive scan display.

As shown in Figure 2, Figure 3 and Figure 4, the timing sequence of Figure 3 is the input and output timing of the second stage shift register Out ₂ and the input and output timing sequence of the third stage shift register Out ₃ , and the timing sequence of Figure 4 is the eighth The input and output timing of the stage shift register Out ₈ and the input and output timing of the ninth stage shift register Out ₉ .

As shown in Figure 3 and Figure 4, specify the start row of the third row and the end row of the eighth row, that is, the switching resolution of the gate line progressive scan of the 3rd to the 8th row is displayed as an example. The working states of lines 9 and 9 illustrate the working principle of the circuit for switching the resolution display of the shift register provided by the embodiment of the present invention.

Specifically, before triggering the operation of the shift register of the first row, the signal of the second reset signal terminal Rst is a high-level signal, other signals are low-level signals, the fifteenth switch transistor M15 is turned on, and the third node D is pulled up The potential of the first node A is pulled down, and the gate signal output terminal of the shift register is reset.

Explain the principle of switching to the third row of the shift register as the initial row:

Before switching to the third row of the shift register as the initial row, the shift register is scanned in full screen, that is, it is scanned from the first row to the last row step by step. When the output of the gate signal output terminal Out ₂ of the shift register in the second row is a high potential stage (the output of Out ₂ in FIG. 3 is a high stage), the signal of the signal output termination terminal CGE is a high potential signal, and the first switch The transistor M1 and the seventh switch transistor M7 are turned on to charge the first node A, the signal of the first node A is a high potential signal, the eleventh switch transistor M11 is turned on, and the third reference signal terminal VGL is at a low potential The signal pulls down the potential of the third node D, and the signal of the third node D is a low potential signal. When the signal of the second clock signal terminal CKR is a high-level signal, due to the bootstrapping effect of the third capacitor C3, the potential of the first node A is further increased, the thirteenth switching transistor M13 is turned on, and Out ₂ outputs a high level , the twelfth switch transistor M12 is turned on, and the low potential signal of the third reference signal terminal VGL continues to pull down the potential of the third node D. When the signal of the second clock signal terminal CKR is a low level signal, the potential of the first node A returns to the high level when Out ₂ output is high, the thirteenth switch transistor M13 is still turned on, and Out ₂ outputs a low level signal.

During full-screen scanning, the signal output selection terminal CGI in the shift register in the third row inputs a high potential signal when the output of the shift register in the third row is a high potential signal, the ninth switch transistor M9 is turned on, and the second node B is pulled high as High level, in the switching resolution trigger frame T1, the signal of the second node B in the progressive scanning period after Out ₃ is output is always kept as a high level signal. After the switching resolution trigger frame T1 ends, the signal of the signal output trigger terminal CGS is a high potential signal, the signal of the signal output termination terminal CGE is a high potential signal, the second node B is raised due to the bootstrapping effect of the capacitor C, the fifth The switching transistor M5 is turned on, and the signal of the first node A is a high-level signal. The signal of the second clock signal terminal CKBL is a high-level signal. Due to the bootstrapping effect of the third capacitor C3, the signal of the first node A is further increased, the thirteenth switch transistor M13 is turned on, and Out ₃ outputs a high-level signal. The twelfth switch transistor M12 is turned on, and the low-level signal of the third reference signal terminal VGL continues to pull down the signal of the third node D through the twelfth switch transistor M12; due to the Out ₃ output stage, the signal of the signal output selection terminal CGI is high Therefore, the next frame is switched to the third row of the shift register as the initial scanning row, that is, scanning from the third row to the eighth row for several cycles.

If after scanning for several cycles, if you want to terminate the scan on the 8th line of a certain frame, that is, select the end line of the 8th line, because the 8th line is the end line, when Out ₈ outputs a high-level signal, the signal output terminal CGE signal is a low-level signal.

Shift register in the ninth row: When the output of Out ₈ is a high-level signal, the signal at the signal output terminal CGE is a low-level signal, the first switch transistor M1 and the seventh switch transistor M7 are turned off, and the ninth shift register is not charged, That is, the scan line ends at line 8.

Therefore, the shift register provided by the embodiment of the present invention can select any line between the start line and the end line of the shift register to output a scan signal through the cooperation of the above-mentioned modules, so as to realize the adjustment of the panel resolution. Select, reduce power consumption and extend standby time.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, including a plurality of cascaded shift registers as provided by the embodiment of the present invention; wherein,

Except the last stage shift register, the gate signal output end of each stage shift register is connected to the first signal input end of its adjacent next stage shift register;

Except for the first stage shift register, the gate signal output terminal of each stage shift register is connected to the second signal input terminal of the adjacent previous stage shift register.

Based on the same inventive concept, an embodiment of the present invention further provides a display device including the gate driving circuit provided by the embodiment of the present invention. The display device may be a display device of any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. For the implementation of the display device, reference may be made to the embodiments of the gate driving circuit described above, and repeated descriptions will not be repeated here.

During specific implementation, the above-mentioned display device provided in the embodiment of the present invention may be a liquid crystal display device or an organic electroluminescence display device, which is not limited herein.

Based on the same inventive concept, an embodiment of the present invention also provides a driving method for a gate driving circuit, including:

When it is determined to scan the full-screen gate line, input a low-potential signal to the trigger signal terminal;

When it is determined to scan the gate lines of the m-th row to the n-th row, a high-level signal is input to the signal output selection terminal of the m-th row shift register, and a low-level signal is input to the signal output terminal of the n-th row shift register, wherein , 1≤m<n.

The following provides two embodiments to describe the input and output timing diagrams of the gate driving circuit provided by the embodiments of the present invention for switching from full-screen scanning to designated row scanning.

Example 1:

As shown in FIG. 5 , the resolution switching trigger frame T1 shows the input and output timing diagram of each signal in the shift register from the 1st row to the 14th row, and the resolution switching display stage T2 shows the switching to output from the 3rd row. until the end of line 9. It can be seen from Figure 5 that the resolution switching trigger frame T1 is a full-screen scan, and the next frame cooperates with the signals output from the CGI, CGS, and CGE signal terminals of the signal output switching unit to switch from the 3rd row to the 9th row. For the detailed working principle of the specific gate driving circuit, refer to the working principle of the above-mentioned shift register provided by the embodiment of the present invention, which will not be repeated here.

Embodiment 2:

As shown in FIG. 6 , the resolution switching trigger frame T1 shows the input and output timing diagram of each signal in the shift register from the 1st row to the 14th row, and the resolution switching display stage T2 shows the switching to output from the 5th row. until the end of line 11. It can be seen from Figure 6 that the resolution switching trigger frame T1 is a full-screen scan, and the next frame cooperates with the signals output by the signal terminals of the CGI, CGS, and CGE of the signal output switching unit to switch from the 5th row to the 11th row. For the detailed working principle of the specific gate driving circuit, refer to the working principle of the above-mentioned shift register provided by the embodiment of the present invention, which will not be repeated here.

A shift register, a gate driving circuit and a driving method thereof, and a display device provided by the embodiments of the present invention include: a first input control connected between a first node, a first signal input terminal and a first reference signal terminal The module, the second input control module connected between the first node, the second signal input terminal and the second reference signal terminal, and the output control module connected between the first node and the gate signal output terminal, further comprising: a first signal output termination module located between the first input control module and the first reference signal terminal, a second signal output termination module located between the second input control module and the second reference signal terminal, and connected to the first node The signal output switching unit. Through the cooperation of the above modules, it is possible to select any row between the start row and the end row of the shift register to output the scan signal, thereby realizing the selection of the panel resolution, reducing power consumption and prolonging the standby time.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (10)

1. A shift register, comprising: a first input control module connected between a first node, a first signal input terminal and a first reference signal terminal, connected to the first node, the second A second input control module between the signal input terminal and the second reference signal terminal, and an output control module connected between the first node and the gate signal output terminal, further comprising: located in the first input control module a first signal output termination module with the first reference signal terminal, a second signal output termination module located between the second input control module and the second reference signal terminal, and with the first signal output termination module The signal output switching unit of the node connection; wherein, The first signal output termination module is configured to terminate the connection between the first reference signal terminal and the first input control module under the control of the signal output termination terminal signal; The second signal output termination module is configured to terminate the connection between the second reference signal terminal and the second input control module under the control of the signal output termination terminal signal; The signal output switching unit includes: a signal output selection module, a signal output trigger module and a signal output reset module; wherein, The signal output selection module is configured to provide the signal of the signal output selection terminal to the second node under the control of the gate signal output terminal signal; The signal output trigger module is configured to provide the signal of the trigger signal terminal to the first node under the control of the second node; The signal output reset module is configured to provide the signal of the third reference signal terminal to the second node under the control of the reset signal terminal signal. 2. The shift register according to claim 1, wherein the first signal output termination module specifically comprises: a first switch transistor; wherein, The gate of the first switching transistor is connected to the signal output terminal, the first pole is connected to the first reference signal terminal, and the second pole is connected to the first input control module. 3. The shift register of claim 1, wherein the second signal output termination module specifically comprises: a second switch transistor; wherein, The gate of the second switching transistor is connected to the signal output terminal, the first pole is connected to the second reference signal terminal, and the second pole is connected to the second input control module. 4. The shift register of claim 1, wherein the signal output selection module specifically comprises: a third switch transistor; wherein, The gate of the third switching transistor is connected to the gate signal output terminal, the first pole is connected to the signal output selection terminal, and the second pole is connected to the second node. 5. The shift register of claim 1, wherein the signal output reset module specifically comprises: a fourth switch transistor; wherein, The gate of the fourth switch transistor is connected to the reset signal terminal, the first pole is connected to the third reference signal terminal, and the second pole is connected to the second node. 6. The shift register of claim 1, wherein the signal output trigger module specifically comprises: a fifth switch transistor and a capacitor; wherein, the gate of the fifth switch transistor is connected to the second node, the first pole is connected to the trigger signal terminal, and the second pole is connected to the first node; The first end of the capacitor is connected to the second node, and the second end is connected to the first node. 7. The shift register of claim 6, further comprising: a sixth switch transistor; wherein, the gate of the sixth switching transistor is connected to the second terminal of the capacitor, the first pole is connected to the third reference signal terminal, and the second pole is connected to the first node; it is used for connecting to the second node The signal of the third reference signal terminal is provided to the first node under the control of the . 8. A gate drive circuit, characterized in that it comprises a plurality of cascaded shift registers according to any one of claims 1-7; wherein, Except the last stage shift register, the gate signal output end of each stage shift register is connected to the first signal input end of its adjacent next stage shift register; Except for the first stage shift register, the gate signal output terminal of each stage shift register is connected to the second signal input terminal of the adjacent previous stage shift register. 9 . A display device, comprising the gate driving circuit according to claim 8 . 10 . 10. A driving method for a gate driving circuit as claimed in claim 8, characterized in that, comprising: When it is determined to scan the full-screen gate line, input a low-potential signal to the trigger signal terminal; When it is determined to scan the gate lines of the m-th row to the n-th row, a high-level signal is input to the signal output selection terminal of the m-th row shift register, and a low-level signal is input to the signal output terminal of the n-th row shift register, wherein , 1≤m<n.