CN109767740A - Shift register, gate driving circuit and its driving method, display device - Google Patents

Shift register, gate driving circuit and its driving method, display device Download PDF

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Publication number
CN109767740A
CN109767740A CN201910225344.5A CN201910225344A CN109767740A CN 109767740 A CN109767740 A CN 109767740A CN 201910225344 A CN201910225344 A CN 201910225344A CN 109767740 A CN109767740 A CN 109767740A
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Prior art keywords
signal
signal output
node
shift register
switching transistor
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CN109767740B (en
Inventor
刘鹏
刘白灵
李付强
王志冲
冯京
栾兴龙
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to CN201910225344.5A priority Critical patent/CN109767740B/en
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Priority to PCT/CN2020/076669 priority patent/WO2020192340A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention discloses a kind of shift registers, gate driving circuit and its driving method, display device, it include: to be connected to first node, the first input control module between first signal input part and the first reference signal end, it is connected to first node, the second input control module between second signal input terminal and the second reference signal end, and it is connected to the output control module between first node and grid signal output end, further include: the first signal output termination module between the first input control module and the first reference signal end, second signal output termination module between the second input control module and the second reference signal end, and the signal output switch unit being connect with first node.By the mutual cooperation of above-mentioned several modules, it may be implemented to carry out selection output scanning signal to row any between end line to the initial row of shift register, to realize the selection to panel resolution ratio, reduce power consumption, extension stand-by time.

Description

Shifting register, grid driving circuit and driving method thereof and display device
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit, a driving method of the grid driving circuit and a display device.
Background
In a Thin Film Transistor display, a gate driving signal is generally supplied to a gate of each Thin Film Transistor (TFT) in a pixel region by a gate driving device. The Gate driving device can be formed on an Array substrate of a display through an Array process, namely, a Gate Driver on Array (GOA) process of the Array substrate, the integration process not only saves cost, but also can achieve an aesthetic design of bilateral symmetry of a liquid crystal Panel (Panel), and simultaneously, a binding region of a Gate Integrated Circuit (IC) and a wiring space of a Fan-out (Fan-out) are also saved, thereby realizing the design of a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
At present, mobile products are updated very fast, products develop towards the trend of being light, thin, fine and ultra-long in standby, from the perspective of customer experience, the requirements on a frame of a screen are more and more narrow, and the standby time is longer. Therefore, a panel design with strong driving capability, lower power consumption and longer standby time is developed, and the method plays a great role in improving the competitiveness of the performance of the display device.
After the resolution is determined, the conventional GOA circuit can only scan from the first row of gate lines to the last row of gate lines, and no matter what the specific actual display requirements are, all scanning display must be performed from the starting row to the ending row. Therefore, how to increase the standby time of the display product is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of this, embodiments of the present invention provide a shift register, a gate driving circuit, a driving method thereof, and a display device, which can select an output scanning signal for any line between a start line and an end line of the shift register, thereby implementing selection of a panel resolution, reducing power consumption, and prolonging a standby time.
Accordingly, an embodiment of the present invention provides a shift register, including: the first input control module connected between the first node, the first signal input terminal and the first reference signal terminal, the second input control module connected between the first node, the second signal input terminal and the second reference signal terminal, and the output control module connected between the first node and the grid signal output terminal, further comprising: a first signal output termination module located between the first input control module and the first reference signal terminal, a second signal output termination module located between the second input control module and the second reference signal terminal, and a signal output switching unit connected to the first node; wherein,
the first signal output termination module is configured to terminate the connection between the first reference signal terminal and the first input control module under control of a signal output termination terminal signal;
the second signal output termination module is configured to terminate the connection between the second reference signal terminal and the second input control module under control of the signal output termination terminal signal;
the signal output switching unit includes: the signal output selection module, the signal output trigger module and the signal output reset module; wherein,
the signal output selection module is configured to provide a signal of a signal output selection terminal to a second node under the control of the gate signal output terminal signal;
the signal output trigger module is configured to provide a signal of a trigger signal terminal to the first node under the control of the second node;
the signal output reset module is configured to provide a signal of a third reference signal terminal to the second node under control of a reset signal terminal signal.
In a possible implementation manner, in an implementation manner, in the shift register provided in an embodiment of the present invention, the first signal output termination module specifically includes: a first switching transistor; wherein,
and the grid electrode of the first switch transistor is connected with the signal output termination end, the first pole of the first switch transistor is connected with the first reference signal end, and the second pole of the first switch transistor is connected with the first input control module.
In a possible implementation manner, in an implementation manner, in the shift register provided in an embodiment of the present invention, the second signal output termination module specifically includes: a second switching transistor; wherein,
and the grid electrode of the second switch transistor is connected with the signal output termination end, the first pole of the second switch transistor is connected with the second reference signal end, and the second pole of the second switch transistor is connected with the second input control module.
In a possible implementation manner, in an implementation manner, in the shift register provided in an embodiment of the present invention, the signal output selecting module specifically includes: a third switching transistor; wherein,
and the grid electrode of the third switching transistor is connected with the grid electrode signal output end, the first pole of the third switching transistor is connected with the signal output selection end, and the second pole of the third switching transistor is connected with the second node.
In a possible implementation manner, in an implementation manner, in the shift register provided in an embodiment of the present invention, the signal output resetting module specifically includes: a fourth switching transistor; wherein,
and the grid electrode of the fourth switching transistor is connected with the reset signal end, the first electrode of the fourth switching transistor is connected with the third reference signal end, and the second electrode of the fourth switching transistor is connected with the second node.
In a possible implementation manner, in a specific implementation, in the shift register provided in an embodiment of the present invention, the signal output triggering module specifically includes: a fifth switching transistor and a capacitor; wherein,
a gate of the fifth switching transistor is connected to the second node, a first pole of the fifth switching transistor is connected to the trigger signal terminal, and a second pole of the fifth switching transistor is connected to the first node;
and the first end of the capacitor is connected with the second node, and the second end of the capacitor is connected with the first node.
In a possible implementation manner, in a specific implementation, in the shift register provided in the embodiment of the present invention, the shift register further includes: a sixth switching transistor; wherein,
a gate of the sixth switching transistor is connected to the second end of the capacitor, a first electrode of the sixth switching transistor is connected to the third reference signal end, and a second electrode of the sixth switching transistor is connected to the first node; for providing a signal of the third reference signal terminal to the first node under control of the second node.
Correspondingly, the embodiment of the invention also provides a gate drive circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein,
except the last stage of shift register, the grid signal output end of each stage of shift register is connected with the first signal input end of the next stage of shift register adjacent to the grid signal output end of each stage of shift register;
except the first stage of shift register, the grid signal output end of each stage of shift register is connected with the second signal input end of the adjacent previous stage of shift register.
Correspondingly, the embodiment of the invention also provides a display device which comprises the gate driving circuit provided by the embodiment of the invention.
Correspondingly, an embodiment of the present invention further provides a driving method of the gate driving circuit provided by the embodiment of the present invention, including:
when the full-screen grid line is determined to be scanned, inputting a low-potential signal to the trigger signal end;
when the m-th to n-th rows of grid lines are determined to be scanned, inputting a high potential signal to a signal output selection end of the m-th row of shift registers, and inputting a low potential signal to a signal output termination end of the n-th row of shift registers, wherein m is more than or equal to 1 and less than n.
The invention has the following beneficial effects:
the shift register, the gate driving circuit, the driving method thereof and the display device provided by the embodiment of the invention comprise: connect the first input control module between first node, first signal input end and first reference signal end, connect the second input control module between first node, second signal input end and second reference signal end to and connect the output control module between first node and grid signal output, still include: the first signal output termination module is positioned between the first input control module and the first reference signal end, the second signal output termination module is positioned between the second input control module and the second reference signal end, and the signal output switching unit is connected with the first node. Through the mutual matching of the modules, the selection of any row between the initial row and the final row of the shift register to output a scanning signal can be realized, so that the selection of the resolution of the panel is realized, the power consumption is reduced, and the standby time is prolonged.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 3 is a timing diagram of an input/output of the shift register shown in FIG. 2;
FIG. 4 is a timing diagram of an input/output operation of the shift register shown in FIG. 2;
fig. 5 is a timing diagram of an input/output corresponding to the gate driving circuit according to the embodiment of the invention;
fig. 6 is another input/output timing diagram corresponding to the gate driving circuit according to the embodiment of the invention.
Detailed Description
The following describes in detail specific embodiments of a shift register, a gate driving circuit, a driving method thereof, and a display device according to embodiments of the present invention with reference to the accompanying drawings.
As shown in fig. 1, a shift register according to an embodiment of the present invention includes: connected to the first node A and the first signal input end OUTN-1A first input control module 1 connected to the first node A and the second signal input end OUT between the first input control module and the first reference signal end CNN+1A second input control module 2 connected between the first node A and the gate signal output terminal OutNThe output control module 3 in between, further comprising: a first signal output termination module 4 located between the first input control module 1 and the first reference signal terminal CN, a second signal output termination module 5 located between the second input control module 2 and the second reference signal terminal CNB, and a signal output switching unit connected to the first node a; wherein,
the first signal output termination module 4 is configured to terminate the connection between the first reference signal terminal CN and the first input control module 1 under the control of the signal output termination terminal CGE signal;
the second signal output termination module 5 is configured to terminate the connection between the second reference signal terminal CNB and the second input control module 2 under the control of the signal output termination terminal CGE signal;
the signal output switching unit includes: the device comprises a signal output selection module 6, a signal output trigger module 7 and a signal output reset module 8; wherein,
the signal output selection module 6 is configured to select the gate signal output Out at the gate signal output terminal OutNUnder the control of the signal, providing the signal of the signal output selection end CGI to a second node B;
the signal output triggering module 7 is configured to provide the signal of the triggering signal terminal CGS to the first node a under the control of the second node B;
the signal output reset module 8 is configured to provide the signal of the third reference signal terminal VGL to the second node B under the control of the reset signal terminal CGR signal.
The shift register provided by the embodiment of the invention comprises: connect the first input control module between first node, first signal input end and first reference signal end, connect the second input control module between first node, second signal input end and second reference signal end to and connect the output control module between first node and grid signal output, still include: the first signal output termination module is positioned between the first input control module and the first reference signal end, the second signal output termination module is positioned between the second input control module and the second reference signal end, and the signal output switching unit is connected with the first node. Through the mutual matching of the modules, the selection of any row between the initial row and the final row of the shift register to output a scanning signal can be realized, so that the selection of the resolution of the panel is realized, the power consumption is reduced, and the standby time is prolonged.
In specific implementation, as shown in fig. 1, the first signal input terminal of the shift register N of the present stage is the gate signal output terminal OUT of the shift register N-1 of the previous stageN-1The second signal input end of the shift register N of the current stage is connected with the grid signal output end OUT of the shift register N +1 of the next stageN+1Are connected. The shift register provided by the embodiment of the invention can realize forward scanning and reverse scanning modes, when the forward scanning mode is adopted, the signal of the first reference signal end CN is a high-potential signal, and the second reference signal end CN is a high-potential signalThe signal of the reference signal terminal CNB is a low potential signal; when the reverse scan mode is adopted, the signal of the first reference signal terminal CN is a low-potential signal, and the signal of the second reference signal terminal CNB is a high-potential signal. When forward scanning is adopted, the grid signal output end OUT of the next stage of shift register N +1N+1The output signal resets the shift register N of the current stage; when the reverse scanning is adopted, the grid signal output end OUT of the upper-stage shift register N-1N-1The output signal resets the shift register N of the present stage.
The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is for better explaining the present invention, but not limiting the present invention.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the first signal output termination module 4 specifically includes: a first switching transistor M1; wherein,
the gate of the first switching transistor M1 is connected to the signal output termination CGE, the first pole is connected to the first reference signal terminal CN, and the second pole is connected to the first input control module 1.
The above is merely an example of the specific structure of the first signal output termination module in the shift register, and in the specific implementation, the specific structure of the first signal output termination module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the second signal output termination module 5 specifically includes: a second switching transistor M2; wherein,
a second switching transistor M2 has a gate connected to the signal output termination CGE, a first pole connected to the second reference signal terminal CNB, and a second pole connected to the second input control block 2.
The above is merely an example of the specific structure of the second signal output termination module in the shift register, and in the specific implementation, the specific structure of the second signal output termination module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the signal output selecting module 6 specifically includes: a third switching transistor M3; wherein,
a third switching transistor M3 having its gate and gate signal output terminal OutNAnd the first pole is connected with the signal output selection end CGI, and the second pole is connected with the second node B.
Specifically, after the resolution is determined, the conventional shift register circuit can only start scanning from the first row of gate lines to the last row of gate lines, and no matter what the specific actual display requirements are, all scanning display must be performed from the starting row to the ending row. For example, the user only needs to watch time and weather information on the screen for a long time, and does not need to display the information in other places, but the traditional screen is full-screen display, so that the power consumption is high; for example, only some lines, such as the 3 rd line to the 8 th line, need to be displayed for time and weather information on the screen, the signal output selection module in the signal output switching unit in the shift register according to the embodiment of the present invention may charge the second node B through the high potential signal input by the signal output selection terminal CGI when the 3 rd line is scanned, and due to the bootstrap action of the capacitor C, the potential of the second node B is always kept at the high potential before the third line of the next frame is scanned, so that the scanning may be switched from the 3 rd line to the 8 th line.
The above is only an example of the specific structure of the signal output selection module in the shift register, and in the specific implementation, the specific structure of the signal output selection module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in an implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the signal output resetting module 8 specifically includes: a fourth switching transistor M4; wherein,
a fourth switching transistor M4 has a gate connected to the reset signal terminal CGR, a first pole connected to the third reference signal terminal VGL, and a second pole connected to the second node B.
Specifically, the signal output reset module is configured to, when only a certain row of the cascaded shift registers is selected to scan out the gate signal, for example, scan from row 3 to row 8, that is, row 3 to row 8 for one period, and after scanning for several periods, the scan is finished, and the shift registers scan from the first row to the last row again, before the next scan from row 3 to row 8, the potential of the second node B is reset, that is, the fourth switching transistor M4 is turned on under the control of the high potential signal of the reset signal terminal CGR, the low potential signal of the third reference signal terminal VGL is input to the second node B, and the signal of the second node B is a low potential signal, which does not affect the operation of the shift registers.
The above is only an example of the specific structure of the signal output reset module in the shift register, and in the specific implementation, the specific structure of the signal output reset module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the signal output triggering module 7 specifically includes: a fifth switching transistor M5 and a capacitor C; wherein,
a fifth switching transistor M5 having a gate connected to the second node B, a first pole connected to the trigger signal terminal CGS, and a second pole connected to the first node a;
and a capacitor C, a first end of which is connected with the second node B, and a second end of which is connected with the first node A.
Specifically, in the embodiment of the present invention, when the signal output selection module 4 selects to scan from a certain row, the signal output triggering module 5 inputs a high-potential signal to the first node a through the triggering signal terminal CGS, and charges the first node a to perform scanning of the shift register.
The above is only an example of the specific structure of the signal output trigger module in the shift register, and in the specific implementation, the specific structure of the signal output trigger module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in a specific implementation, since the second end of the capacitor C is connected to the source and drain of each switching transistor, which may affect the function of the capacitor C to store charges, in order to improve the capability of the capacitor C to store charges, as shown in fig. 2, the shift register provided in the embodiment of the present invention further includes: a sixth switching transistor M6; wherein,
a sixth switching transistor M6, having a gate connected to the second terminal of the capacitor C, a first pole connected to the fourth reference signal terminal VGH, and a second pole connected to the first node a; for providing a signal of the fourth reference signal terminal VGH to the first node a under the control of the second node B.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the first input control module 1 specifically includes: a seventh switching transistor M7; wherein,
a seventh switching transistor M7 having a gate connected to the first signal input terminal OUTN-1To a first pole of the first switching transistor M1, and a second pole of the first switching transistor M1, to a first node a.
The above is merely an example of the specific structure of the first input control module in the shift register, and in the specific implementation, the specific structure of the first input control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the second input control module 2 specifically includes: an eighth switching transistor M8; wherein,
an eighth switching transistor M8 having a gate connected to the second signal input terminal OUTN+1To a first pole of the second switching transistor M2, and a second pole of the second switching transistor M2, to a first node a.
The above is merely an example of the specific structure of the second input control module in the shift register, and in the specific implementation, the specific structure of the second input control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation, as shown in fig. 1, the shift register provided in the embodiment of the present invention further includes: a node control module 9, a second output module 10 and a reset module 11.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the node control module 9 specifically includes: a ninth switching transistor M9, a tenth switching transistor M10, an eleventh switching transistor M11, a twelfth switching transistor M12, and a second capacitor C2; wherein,
a ninth switching transistor M9 having a gate and a first pole both connected to the first clock signal terminal CK, and a second pole connected to the third node D;
a tenth switching transistor M10 having a gate connected to the third node D, a first pole connected to the first node a, and a second pole connected to the third reference signal terminal VGL;
an eleventh switching transistor M11 having a gate connected to the first node a, a first pole connected to the third node D, and a second pole connected to the third reference signal terminal VGL;
a twelfth switching transistor M12, having a gate connected to the gate signal output terminal Out of the shift register of the current stageNThe first pole is connected with the third node D, and the second pole is connected with the third reference signal end VGL;
and a second capacitor C2 having a first terminal connected to the third node D and a second terminal connected to the third reference signal terminal VGL.
In practical implementation, in the shift register provided in the embodiment of the present invention, the size of the eleventh switching transistor is generally set to be larger than that of the ninth switching transistor during process preparation, so that when the potential of the first node is at a high potential, the rate at which the eleventh switching transistor supplies the signal of the second reference signal terminal to the third node under the control of the signal of the first node is greater than the rate at which the ninth switching transistor supplies the signal of the first clock signal terminal to the third node under the control of the first clock signal terminal, thereby ensuring that the potential of the third node is at a low potential.
The above is merely an example of the specific structure of the node control module in the shift register, and in the specific implementation, the specific structure of the node control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the output control module 3 specifically includes: a thirteenth switching transistor M13 and a third capacitor C3; wherein,
a thirteenth switching transistor M13, having a gate connected to the first node a, a first pole connected to the second clock signal terminal CKB, and a second pole connected to the gate signal output terminal Out of the shift register of the current stageNConnecting;
a third capacitor C3, having a first end connected to the first node a and a second end connected to the gate signal output end Out of the shift register of the present stageNAre connected.
The above is merely an example of the specific structure of the output control module in the shift register, and in the specific implementation, the specific structure of the output control module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the second output module 10 specifically includes: a fourteenth switching transistor M14; wherein,
a fourteenth switching transistor M14, having a gate connected to the third node D, and a first pole connected to the gate signal output terminal Out of the present stage shift registerNAnd the second pole is connected to the third reference signal terminal VGL.
The above is merely an example of the specific structure of the second output module in the shift register, and in the specific implementation, the specific structure of the second output module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a possible implementation manner, in an implementation manner, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, the second reset module 11 specifically includes: a fifteenth switching transistor M15; wherein,
a fifteenth switching transistor M15 has a gate and a first pole both connected to the second reset signal terminal RST, and a second pole connected to the third node D.
Specifically, the second reset module is used for turning on the fifteenth switching transistor M15 under the control of the high-level signal of the second reset signal terminal RST before the scanning of the first row of shift registers of the cascaded shift registers is startedA high-potential signal of the two reset signal terminals RST is input to the third node D to charge the third node D, the fourteenth switching transistor M14 is turned on, and a low-potential signal of the third reference signal terminal VGL is input to the gate signal output terminal OutNOut to the gate signal output terminalNThe reset is performed so as not to affect the progressive scanning of the plurality of shift registers in cascade.
The above is merely an example of the specific structure of the second reset module in the shift register, and in the specific implementation, the specific structure of the second reset module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
It should be noted that the switching Transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a Metal oxide semiconductor field effect Transistor (MOS), and is not limited herein.
In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 2, all the switch transistors are N-type transistors; the third reference signal terminal VGL has a low potential, and the fourth reference signal terminal VGH has a high potential.
Of course, in the shift register provided in the embodiment of the present invention, all the switch transistors may also be P-type transistors.
Further, in specific implementation, the N-type transistor is turned on under the action of a high potential and is turned off under the action of a low potential; the P-type transistor is turned off under the action of a high potential and turned on under the action of a low potential.
It should be noted that the first pole of the switching transistor mentioned in the above embodiments of the present invention may be a source, and the second pole is a drain, or the first pole may be a drain, and the second pole is a source, which are not specifically distinguished herein.
The following describes the working process of switching the shift register from full-screen scanning to specified line scanning, which is provided by the embodiment of the present invention, by taking forward scanning as an example, with reference to a circuit timing diagram. In the following description, a high potential signal is denoted by 1, and a low potential signal is denoted by 0.
Take the shift register shown in fig. 2 as an example, wherein, in fig. 2, all the switch transistors M1 are N-type transistors. Describing in detail the input and output timing sequence process for switching from scanning full screen gate lines to scanning from line 3 to line 8, the corresponding input and output timing sequence is shown in fig. 3 and 4. RST in fig. 3 and 4 indicates that before the first row of shift registers is triggered (i.e., before STV is high, STV is the initial trigger signal of the shift registers), the gate signal output terminals of the shift registers are reset to ensure normal output of the shift registers; the input/output timing sequences shown in fig. 3 and 4 provided by the embodiments of the present invention are for bilateral driving, CKL and CKBL represent a left clock signal end, CKR and CKBR represent a right clock signal end, a signal of the first reference signal end CN is a high potential signal, a signal of the second reference signal end CNB is a low potential signal, a potential of the third reference signal end VGL is a low potential, and a potential of the fourth reference signal end VGH is a high potential.
The embodiment of the invention takes forward scanning as an example to explain the working principle of the design that full-screen scanning is switched to line 3 to line 8, when the current frame is full-screen scanning, the next frame is scanned from line 3 to line 8, namely the next frame starts the line 3 starting the line 8 ending the line, the line 3 to the line 8 is a period, and the scanning is continuously performed for a plurality of periods according to the display requirement. The operation of the shift register to specify a specific initial row and end row when switching resolution scans is divided into two phases, the first phase: a resolution switch trigger frame T1, which is a scan of a normal frame (from the first row to the last row), since the next frame is to be scanned from the 3 rd row, the resolution switch trigger frame T1 needs to cooperate with the signal of the signal output selection terminal CGI to designate the 3 rd row shift register of the next frame as the initial row; and a second stage: and in the resolution switching display stage T2, the resolution switching display can be realized by matching with signals of a signal output selection end CGI, a signal output trigger end CGS, a signal output termination CGE and a reset signal end CGR, and the display is scanned and displayed line by line according to the initial line and the end line of the specified behavior.
As shown in FIGS. 2, 3 and 4, the timing of FIG. 3 is the 2 nd stage shift register Out2Input/output timing of and 3 rd stage shift register Out3The timing sequence of FIG. 4 is the 8 th stage shift register Out8Input/output timing of and 9 th stage shift register Out9The input/output timing of (1).
As shown in fig. 3 and fig. 4, the 3 rd row start line and the 8 th row end line are specified, that is, the switching resolution of scanning the gate lines of the 3 rd to 8 th rows line by line is shown as an example, and the operating mode of the shift register switching resolution display provided by the embodiment of the present invention is described by using the operating states of the 2 nd, 3 rd, 8 th and 9 th rows.
Specifically, before the first row of shift registers is triggered to operate, the signal of the second reset signal terminal Rst is a high potential signal, the other signals are low potential signals, the fifteenth switching transistor M15 is turned on, the potential of the third node D is pulled up, the potential of the first node a is pulled down, and the gate signal output terminal of the shift register is reset.
The principle of switching to line 3 shift register as the initial line is explained:
before switching to the 3 rd row shift register as the initial row, the shift register is full-screen scanned, i.e. scanned from the first row to the last row step by step, if the next frame of full-screen scanning is started from the 3 rd row, the gate signal output end Out of the 2 nd row shift register is full-screen scanned2The output is a high phase (Out in FIG. 3)2Output is in a high stage), the signal of the signal output termination end CGE is a high potential signal, the first switching transistor M1 and the seventh switching transistor M7 are turned on to charge the first node a, the signal of the first node a is a high potential signal, the eleventh switching transistor M11 is turned on, the low potential signal of the third reference signal end VGL pulls down the potential of the third node D, and the signal of the third node D is a low potential signal. Signal at second clock signal terminal CKRWhen the signal is a high-level signal, the potential of the first node A further increases due to the bootstrap effect of the third capacitor C3, the thirteenth switching transistor M13 is turned on, Out2When the twelfth switching transistor M12 is turned on, the low-potential signal of the third reference signal terminal VGL keeps pulling the potential of the third node D low. When the signal of the second clock signal terminal CKR is a low-level signal, the potential of the first node A is restored to Out2The output is high at the high moment, the thirteenth switching transistor M13 is still turned on, Out2And outputting a low potential signal.
During full screen scanning, the CGI of the shift register in row 3 inputs a high signal when the shift register in row 3 outputs a high signal, the ninth switching transistor M9 is turned on, the second node B is pulled high, and Out is within the switching resolution trigger frame T13The signal of the second node B is always kept at a high potential signal in the progressive scanning period after the output. After the switching resolution trigger frame T1 is ended, the signal of the signal output trigger end CGS is a high-potential signal, the signal of the signal output termination end CGE is a high-potential signal, the second node B is raised due to the bootstrap effect of the capacitor C, the fifth switching transistor M5 is turned on, and the signal of the first node a is a high-potential signal. The signal of the second clock signal terminal CKBL is a high-level signal, and due to the bootstrap action of the third capacitor C3, the signal of the first node a further rises, the thirteenth switching transistor M13 is turned on, Out3Outputting a high-potential signal, turning on the twelfth switching transistor M12, and continuously pulling down the signal of the third node D by the low-potential signal of the third reference signal terminal VGL through the twelfth switching transistor M12; due to Out3In the output stage, the signal of the signal output selection terminal CGI is at a high level, so that switching to the 3 rd row shift register as the initial scan line in the next frame is achieved, i.e., scanning from the 3 rd row to the 8 th row for several cycles.
If after scanning for a number of periods, if the scanning is to be terminated at line 8 of a certain frame, then line 8 is selected as the line 8, Out due to line 8, which is the line 88When a high-potential signal is output, the signal of the signal output termination end CGE is a low-potential signal.
Line 9 shift register: out8When the output is a high-level signal, the signal of the signal output termination end CGE is a low-level signal, the first switching transistor M1 and the seventh switching transistor M7 are turned off, the 9 th shift register is not charged, that is, the scanning line is terminated at the 8 th line.
Therefore, the shift register provided by the embodiment of the invention can realize the selection of any line between the initial line and the final line of the shift register to output the scanning signal through the mutual matching of the modules, thereby realizing the selection of the resolution of the panel, reducing the power consumption and prolonging the standby time.
Based on the same inventive concept, the embodiment of the invention also provides a gate driving circuit, which comprises a plurality of cascaded shift registers provided by the embodiment of the invention; wherein,
except the last stage of shift register, the grid signal output end of each stage of shift register is connected with the first signal input end of the next stage of shift register adjacent to the grid signal output end of each stage of shift register;
except the first stage of shift register, the grid signal output end of each stage of shift register is connected with the second signal input end of the adjacent previous stage of shift register.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the gate driving circuit provided by the embodiment of the invention. The display device may be: the display device comprises a display device of any product with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be seen in the embodiments of the gate driving circuit, and repeated descriptions are omitted.
In a specific implementation, the display device provided in the embodiment of the present invention may be a liquid crystal display device, and may also be an organic electroluminescent display device, which is not limited herein.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a gate driving circuit, including:
when the full-screen grid line is determined to be scanned, inputting a low-potential signal to a trigger signal end;
when the m-th to n-th rows of grid lines are determined to be scanned, inputting a high potential signal to a signal output selection end of the m-th row of shift registers, and inputting a low potential signal to a signal output termination end of the n-th row of shift registers, wherein m is more than or equal to 1 and less than n.
The following describes the input/output timing diagram of the above-mentioned gate driving circuit switching from full-screen scanning to specified line scanning provided by the embodiment of the present invention by providing two embodiments.
The first embodiment is as follows:
as shown in fig. 5, the resolution switching trigger frame T1 shows the input/output timing diagram of signals in the shift register from row 1 to row 14, and the resolution switching display period T2 shows the switching to off from row 3 to row 9. As can be seen from fig. 5, the resolution switching trigger frame T1 is full-screen scanning, and the next frame realizes switching from the 3 rd line to the 9 th line by matching with signals output by the CGI, CGS, and CGE signal terminals of the signal output switching unit, and the detailed working principle of the specific gate driving circuit refers to the working principle of the shift register provided in the embodiment of the present invention, which is not described herein again.
Example two:
as shown in fig. 6, the resolution switching trigger frame T1 shows the input/output timing diagram of signals in the shift register from row 1 to row 14, and the resolution switching display period T2 shows the switching to off from row 5 to row 11. As can be seen from fig. 6, the resolution switching trigger frame T1 is full-screen scanning, and the next frame realizes switching from the line 5 to the line 11 in cooperation with signals output by the CGI, CGS, and CGE signal terminals of the signal output switching unit, and the detailed working principle of the specific gate driving circuit refers to the working principle of the shift register provided in the embodiment of the present invention, which is not described herein again.
The shift register, the gate driving circuit, the driving method thereof and the display device provided by the embodiment of the invention comprise: connect the first input control module between first node, first signal input end and first reference signal end, connect the second input control module between first node, second signal input end and second reference signal end to and connect the output control module between first node and grid signal output, still include: the first signal output termination module is positioned between the first input control module and the first reference signal end, the second signal output termination module is positioned between the second input control module and the second reference signal end, and the signal output switching unit is connected with the first node. Through the mutual matching of the modules, the selection of any row between the initial row and the final row of the shift register to output a scanning signal can be realized, so that the selection of the resolution of the panel is realized, the power consumption is reduced, and the standby time is prolonged.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A shift register, comprising: the first input control module connected between the first node, the first signal input terminal and the first reference signal terminal, the second input control module connected between the first node, the second signal input terminal and the second reference signal terminal, and the output control module connected between the first node and the grid signal output terminal, further comprising: a first signal output termination module located between the first input control module and the first reference signal terminal, a second signal output termination module located between the second input control module and the second reference signal terminal, and a signal output switching unit connected to the first node; wherein,
the first signal output termination module is configured to terminate the connection between the first reference signal terminal and the first input control module under control of a signal output termination terminal signal;
the second signal output termination module is configured to terminate the connection between the second reference signal terminal and the second input control module under control of the signal output termination terminal signal;
the signal output switching unit includes: the signal output selection module, the signal output trigger module and the signal output reset module; wherein,
the signal output selection module is configured to provide a signal of a signal output selection terminal to a second node under the control of the gate signal output terminal signal;
the signal output trigger module is configured to provide a signal of a trigger signal terminal to the first node under the control of the second node;
the signal output reset module is configured to provide a signal of a third reference signal terminal to the second node under control of a reset signal terminal signal.
2. The shift register of claim 1, wherein the first signal output termination module specifically comprises: a first switching transistor; wherein,
and the grid electrode of the first switch transistor is connected with the signal output termination end, the first pole of the first switch transistor is connected with the first reference signal end, and the second pole of the first switch transistor is connected with the first input control module.
3. The shift register of claim 1, wherein the second signal output termination module specifically comprises: a second switching transistor; wherein,
and the grid electrode of the second switch transistor is connected with the signal output termination end, the first pole of the second switch transistor is connected with the second reference signal end, and the second pole of the second switch transistor is connected with the second input control module.
4. The shift register of claim 1, wherein the signal output selection module specifically comprises: a third switching transistor; wherein,
and the grid electrode of the third switching transistor is connected with the grid electrode signal output end, the first pole of the third switching transistor is connected with the signal output selection end, and the second pole of the third switching transistor is connected with the second node.
5. The shift register of claim 1, wherein the signal output reset module specifically comprises: a fourth switching transistor; wherein,
and the grid electrode of the fourth switching transistor is connected with the reset signal end, the first electrode of the fourth switching transistor is connected with the third reference signal end, and the second electrode of the fourth switching transistor is connected with the second node.
6. The shift register according to claim 1, wherein the signal output triggering module specifically includes: a fifth switching transistor and a capacitor; wherein,
a gate of the fifth switching transistor is connected to the second node, a first pole of the fifth switching transistor is connected to the trigger signal terminal, and a second pole of the fifth switching transistor is connected to the first node;
and the first end of the capacitor is connected with the second node, and the second end of the capacitor is connected with the first node.
7. The shift register of claim 6, further comprising: a sixth switching transistor; wherein,
a gate of the sixth switching transistor is connected to the second end of the capacitor, a first electrode of the sixth switching transistor is connected to the third reference signal end, and a second electrode of the sixth switching transistor is connected to the first node; for providing a signal of the third reference signal terminal to the first node under control of the second node.
8. A gate drive circuit comprising a plurality of shift registers according to any one of claims 1 to 7 in cascade; wherein,
except the last stage of shift register, the grid signal output end of each stage of shift register is connected with the first signal input end of the next stage of shift register adjacent to the grid signal output end of each stage of shift register;
except the first stage of shift register, the grid signal output end of each stage of shift register is connected with the second signal input end of the adjacent previous stage of shift register.
9. A display device comprising the gate driver circuit according to claim 8.
10. A driving method of the gate driving circuit according to claim 8, comprising:
when the full-screen grid line is determined to be scanned, inputting a low-potential signal to the trigger signal end;
when the m-th to n-th rows of grid lines are determined to be scanned, inputting a high potential signal to a signal output selection end of the m-th row of shift registers, and inputting a low potential signal to a signal output termination end of the n-th row of shift registers, wherein m is more than or equal to 1 and less than n.
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