CN109765732A - 像素结构 - Google Patents
像素结构 Download PDFInfo
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- CN109765732A CN109765732A CN201711095725.3A CN201711095725A CN109765732A CN 109765732 A CN109765732 A CN 109765732A CN 201711095725 A CN201711095725 A CN 201711095725A CN 109765732 A CN109765732 A CN 109765732A
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- 239000010409 thin film Substances 0.000 claims abstract description 19
- 230000001154 acute effect Effects 0.000 claims abstract description 11
- 238000005452 bending Methods 0.000 claims description 51
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 26
- 230000035484 reaction time Effects 0.000 abstract description 8
- 230000000052 comparative effect Effects 0.000 description 23
- 239000000758 substrate Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 241001442589 Convoluta Species 0.000 description 2
- RQIPKMUHKBASFK-UHFFFAOYSA-N [O-2].[Zn+2].[Ge+2].[In+3] Chemical compound [O-2].[Zn+2].[Ge+2].[In+3] RQIPKMUHKBASFK-UHFFFAOYSA-N 0.000 description 2
- -1 aluminium tin-oxide Chemical compound 0.000 description 2
- JYMITAMFTJDTAE-UHFFFAOYSA-N aluminum zinc oxygen(2-) Chemical compound [O-2].[Al+3].[Zn+2] JYMITAMFTJDTAE-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
本发明提供一种像素结构,包括薄膜晶体管、与薄膜晶体管电性连接的像素电极、共用电极以及位于共用电极与像素电极之间的绝缘层。像素电极且具有多个第一像素分支。共用电极具有多个第一共用分支。多个第一像素分支与多个第一共用分支交替排列。第一像素分支的延伸方向与第一共用分支的延伸方向夹有第一锐角。藉此,第一像素分支与共用电极之间的等电位曲线会向上分布,进而缩短采用像素结构的液晶显示屏的反应时间。
Description
技术领域
本发明涉及一种像素结构。
背景技术
随着高阶智能手机及平板电脑的蓬勃发展,搭载于其上的显示屏的性能也备受重视。一般而言,搭载于高阶智能手机及平板电脑的显示屏除了需省电外,也需具有广视角及低色偏等优良的光学性能。为使显示屏兼具广视角及低色偏,以满足高阶智能手机及平板电脑厂商需求。显示屏厂商开发出边缘场切换(Fringe-Field Switching,FFS)模式液晶显示屏。边缘场切换模式液晶显示屏包括像素阵列基板、相对于像素阵列基板的对向基板以及像素阵列基板与对向基板之间的液晶分子。像素阵列基板包括像素电极、共用电极以及像素电极与共用电极之间的绝缘层。当像素电极与共用电极之间存在足够的电压差时,像素电极和共通电极之间会产生边缘电场,进而使液晶分子水平旋转,进而显示画面。然而,在边缘场切换(Fringe-Field Switching,FFS)模式的液晶显示屏中,液晶分子的运动方式为水平旋转,而存在反应时间过长的问题。
发明内容
本发明是针对一种像素结构,采用所述像素结构的液晶显示屏的反应时间短。
根据本发明的实施例,像素结构包括薄膜晶体管、与薄膜晶体管电性连接的像素电极、共用电极以及位于共用电极与像素电极之间的绝缘层。像素电极且具有多个第一像素分支。共用电极具有多个第一共用分支。多个第一像素分支与多个第一共用分支交替排列。第一像素分支的延伸方向与第一共用分支的延伸方向夹有第一锐角。
在根据本发明的实施例的像素结构中,多个第一共用分支定义多个第一共用狭缝,每一第一像素分支与对应的一个第一共用狭缝部分重叠且与对应的一个第一共用分支部分重叠。
在根据本发明的实施例的像素结构中,像素电极还具有多个第二像素分支,其中多个第一像素分支的延伸方向与多个第二像素分支的延伸方向不同。共用电极还具有多个第二共用分支,其中多个第一共用分支的延伸方向与多个第二共用分支的延伸方向相反。多个第二像素分支与多个第二共用分支交替排列,而多个第二像素分支的延伸方向与多个第二共用分支的延伸方向夹有第二锐角。
在根据本发明的实施例的像素结构中,多个第二共用分支定义多个第二共用狭缝,每一第二像素分支与对应的一个第二共用狭缝部分重叠且与对应的一个第二共用分支部分重叠。
在根据本发明的实施例的像素结构中,像素电极还具有多个像素弯曲部。多个像素弯曲部连接于多个第一像素分支与多个第二像素分支之间。多个第一像素分支、多个第二像素分支以及多个像素弯曲部定义像素电极的多个像素狭缝。
在根据本发明的实施例的像素结构中,共用电极还具有多个共用弯曲部。多个共用弯曲部连接于多个第一共用分支与多个第二共用分支之间。
在根据本发明的实施例的像素结构中,像素电极还具有多个像素弯曲部。多个像素弯曲部连接于多个第一像素分支与多个第二像素分支之间,而多个像素弯曲部与多个共用弯曲部重叠。
在根据本发明的实施例的像素结构中,共用电极还具有连接于多个共用弯曲部之间的连接部。
在根据本发明的实施例的像素结构中,连接部的延伸方向与多个第一共用分支部的延伸方向以及多个第二共用分支的延伸方向垂直。
在根据本发明的实施例的像素结构中,连接部、多个共用弯曲部以及多个第一共用分支定义共用电极的多个第一共用狭缝。连接部、多个共用弯曲部以及多个第二共用分支定义共用电极的多个第二共用狭缝。多个第一共用狭缝及多个第二共用狭缝分别位于连接部的相对两侧。
附图说明
包含附图以便进一步理解本发明,且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例,并与描述一起用于解释本发明的原理。
图1是本发明一实施例的像素结构的上视示意图;
图2是本发明一实施例的像素结构的剖面示意图;
图3为第一比较例的像素结构的上视示意图;
图4示出本发明一实施例的像素结构的像素电极与共用电极之间的等电位曲线;
图5示出第一比较例的像素结构的像素电极与共用电极之间的等电位曲线;
图6示出本发明一实施例的部分像素结构所在处的亮度;
图7示出第二比较例的部分像素结构所在处的亮度;
图8为第三比较例的像素结构的上视示意图;
图9示出采用本发明一实施例的像素结构的液晶显示屏的驱动电压对穿透率的曲线,以及采用第三比较例的像素结构的液晶显示屏的驱动电压对穿透率的曲线。
附图标号说明
100、200、300、400:像素结构;
110:基板;
120、130、150:绝缘层;
130a、150a:贯孔;
140、240、340、440:共用电极;
140a:第一共用狭缝;
140b:第二共用狭缝;
142:第一共用分支;
144:第二共用分支;
146:共用弯曲部;
148a、148b、148c、168、169:连接部;
149:周边部;
160:像素电极;
160a:像素狭缝;
162:第一像素分支;
164:第二像素分支;
166:像素弯曲部;
340a、440a:狭缝;
A-A’、B-B’:剖线;
DL:数据线;
D:漏极;
G:栅极;
R:区域;
SL:扫描线;
S:源极;
SE:半导体层;
S100、S400:曲线;
T:薄膜晶体管;
x、y、-y、z、d1、d2:方向;
θ1:第一锐角;
θ2:第二锐角;
α、β:钝角。
具体实施方式
现将详细地参考本发明的示范性实施例,示范性实施例的实例说明于附图中。只要有可能,相同元件符号在附图和描述中用来表示相同或相似部分。
图1是本发明一实施例的像素结构的上视示意图。图2是本发明一实施例的像素结构的剖面示意图。特别是,图2对应于图1的剖线A-A’及B-B’。请参照图1及图2,像素结构100配置于基板110上。在本实施例中,基板110的材质可以是玻璃、石英、有机聚合物、不透光/反射材料(例如:晶圆、陶瓷、或其它可适用的材料)、或是其它可适用的材料。
请参照图1及图2,像素结构100包括薄膜晶体管T。薄膜晶体管T包括栅极G、半导体层SE、源极S与漏极D。源极S与漏极D分别与半导体层SE的不同两区电性连接。在本实施例中,栅极G配置于基板110上,绝缘层120覆盖栅极G,半导体层SE配置于绝缘层120上,源极S与漏极D分别覆盖半导体层SE的不同两区。在本实施例中,栅极G位于半导体层SE的下方,而薄膜晶体管T例如是底部栅极型薄膜晶体管(bottom gate TFT)。然而,本发明不限于此,在其它实施例中,薄膜晶体管T也可以是顶栅极型薄膜晶体管(top gate TFT)或其它适当型式的薄膜晶体管。
在本实施例中,像素结构100还包括彼此交错的数据线DL及扫描线SL。数据线DL与薄膜晶体管T的源极S电性连接。扫描线SL与薄膜晶体管T的栅极G电性连接。在本实施例中,源极S可以是由数据线DL向外延伸的分支,栅极G可以是由扫描线SL向外延伸的分支。然而,本发明不限于此,在其它实施例中,源极S也可以是数据线DL的一部分,栅极G也可以是扫描线SL的一部分。基于导电性的考量,数据线DL、扫描线SL、栅极G、源极S与漏极D一般是使用金属材料,但本发明不限于此,在其他实施例中,数据线DL、扫描线SL、栅极G、源极S和/或漏极D也可以使用其他导电材料,例如:合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其它导电材料的堆叠层。
像素结构100包括共用电极140。举例而言,在本实施例中,像素结构100还包括绝缘层130,绝缘层130覆盖薄膜晶体管T及绝缘层120,而共用电极140可以选择性地配置于绝缘层130上,但本发明不以此为限。
共用电极140具有多个第一共用分支142。在本实施例中,每一第一共用分支142可以是直线分支。多个第一共用分支142彼此平行且具有相同的延伸方向y。在本实施例中,第一共用分支142可选择性地平行于数据线DL,但本发明不以此为限。在本实施例中,共用电极140还具有多个第二共用分支144。每一第二共用分支144可以是直线分支。多个第二共用分支144彼此平行且具有相同的延伸方向-y。第一共用分支142的延伸方向y与第二共用分支144的延伸方向-y相反。在本实施例中,多个第二共用分支144可选择性地平行于数据线DL,但本发明不以此为限。
在本实施例中,共用电极140还具有多个共用弯曲部146。每一共用弯曲部146连接于对应的一个第一共用分支142与对应的一个第二共用分支144之间。举例而言,在本实施例中,每一共用弯曲部146可以是ㄑ字型图案,所述ㄑ字型图案的两端分别与对应的一个第一共用分支142及对应的一个第二共用分支144连接。所述ㄑ字型图案(即共用弯曲部146)的两个直线部不与第一共用分支142及第二共用分支144平行。
在本实施例中,共用电极140还具有连接部148a。连接部148a连接于多个共用弯曲部146之间。详细而言,连接部148a连接于多个共用弯曲部146的多个转折处之间。在本实施例中,共用电极140还包括周边部149。周边部149围绕多个第一共用分支142、多个第二共用分支144、多个共用弯曲部146以及连接部148a。每一第二共用分支144未与共用弯曲部146连接的一端可连接至周边部149。在本实施例中,共用电极140还包括连接部148b及连接部148c。连接部148b连接于最右侧的一个共用弯曲部146与周边部149之间。连接部148c连接于最左侧的一个共用弯曲部146与周边部149之间。连接部148a、连接部148b、连接部148c及共用弯曲部146形成枝状导电图案,其能防止共用电极140在制程中断线的疑虑。在本实施例中,连接部148a、连接部148b及连接部148c的延伸方向x与第一共用分支142的延伸方向y及第二共用分支144的延伸方向-y可垂直,但本发明不以此为限。
在本实施例中,连接部148a、连接部148b、连接部148c、共用弯曲部146、多个第一共用分支142及周边部149定义共用电极140的多个第一共用狭缝140a。连接部148a、连接部148b、连接部148c、共用弯曲部146、多个第二共用分支144及周边部149定义共用电极140的多个第二共用狭缝140b。多个第一共用狭缝140a及多个第二共用狭缝140b分别位于连接部148a、连接部148b及连接部148c的相对两侧。第一共用分支142、第二共用分支144、共用弯曲部146、连接部148a、连接部148b、连接部148c及周边部149属于同一导电层且彼此电性连接。在本实施例中,共用电极140例如是透明电极层。透明电极层的材质包括金属氧化物,例如:铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物、或其它合适的氧化物、或者是上述至少二者的堆叠层。然而,本发明不限于此,在其它实施例中,共用电极140也可以是反射电极层、或反射电极层与透明电极层的组合。
像素结构100包括绝缘层150。绝缘层150位于共用电极140与像素电极160之间。举例而言,在本实施例中,绝缘层150可覆盖共用电极140,像素电极160可配置于绝缘层150上。换句话说,在本实施例中,像素电极160在上,而共用电极140在下。然而,本发明不限于此,根据其它实施例,也可以是,共用电极140在上,像素电极160在下。在本实施例中,绝缘层150的材料可以是无机材料(例如:氧化硅、氮化硅、氮氧化硅、或上述至少二种材料的堆叠层)、有机材料或上述的组合。
像素结构100包括像素电极160。像素电极160与薄膜晶体管T电性连接。举例而言,在本实施例中,绝缘层150及绝缘层130分别具有贯孔150a及贯孔130a。贯孔150a与贯孔130a相连通。像素电极160可延伸至贯孔150a及贯孔130a内,以和薄膜晶体管T的漏极D电性连接。共用电极140与像素电极160之间的电位差用以驱动显示介质(例如:液晶)。应用像素结构100的液晶显示屏可以是边缘场切换(Fringe-Field Switching,FFS)模式的液晶显示屏。
像素电极160具有多个第一像素分支162。在本实施例中,每一第一像素分支162可以是直线分支。多个第一像素分支162彼此平行且具有相同的延伸方向d1。多个第一像素分支162与多个第一共用分支142交替排列,且多个第一像素分支162的延伸方向d1与多个第一共用分支142的延伸方向y夹有第一锐角θ1。举例而言,在本实施例中,1°≤θ1≤20°,但本发明不以此为限。在本实施例中,第一像素分支162与对应的第一共用狭缝140a部分(partially)重叠且与第一共用分支142部分重叠。更进一步地说,在垂直投影方向z上,每一第一像素分支162的大部分面积位于第一共用狭缝140a内,每一第一像素分支162的少部分面积位于第一共用狭缝140a外。
在本实施例中,像素电极160还具有多个第二像素分支164。在本实施例中,每一第二像素分支164可以是直线分支。多个第二像素分支164彼此平行且具有相同的延伸方向d2。第一像素分支162的延伸方向d1与第二像素分支164的延伸方向d2不同。举例而言,在本实施例中,第一像素分支162可向图1的右下方延伸,第二像素分支164可向图1的右上方延伸,第一像素分支162的延伸方向d1与第二像素分支164的延伸方向d2可夹有钝角α,但本发明不以此为限。多个第二像素分支164与多个第二共用分支144交替排列,且多个第二像素分支164的延伸方向d2与多个第二共用分支144的延伸方向-y夹有第二锐角θ2。举例而言,在本实施例中,1°≤θ2≤20°。第一锐角θ1与第二锐角θ2可相等,但本发明不以此为限。在本实施例中,第二像素分支164与第二共用狭缝140b部分重叠且与第二共用分支144部分重叠。更进一步地说,在垂直投影方向z上,每一第二像素分支164的大部分面积位于第二共用狭缝140b内,每一第二像素分支164的少部分面积位于第二共用狭缝140b外。
在本实施例中,像素电极160还具有多个像素弯曲部166。每一像素弯曲部166连接于对应的一个第一像素分支162与对应的一个第二像素分支164之间。多个像素弯曲部166分别与多个共用弯曲部146重叠。举例而言,在本实施例中,每一像素弯曲部166可以是ㄑ字型图案,所述ㄑ字型图案的两端分别与对应的一个第一像素分支162及对应的一个第二像素分支164连接。所述ㄑ字型图案(即像素弯曲部166)的两直线部不与第一像素分支162及第二像素分支164平行。更进一步地说,在本实施例中,所述ㄑ字型图案(即像素弯曲部166)的两直线部可夹有钝角β,钝角β可小于钝角α,但本发明不以此为限。
在本实施例中,像素电极160还具有位于第一像素分支162、第二像素分支164及像素弯曲部166外的连接部168及连接部169。每一第一像素分支162未与像素弯曲部166连接的一端连接至连接部168。每一第二像素分支164未与像素弯曲部166连接的一端连接至连接部169。多个第一像素分支162,多个第二像素分支164、多个像素弯曲部166、连接部168及连接部169定义像素电极160的多个像素狭缝160a。在本实施例中,于垂直投影方向z上,每一第一共用分支142的大部分面积位于像素狭缝160a内,每一第一共用分支142的少部分区域位于像素狭缝160a外;在垂直投影方向z上,每一第二共用分支144的大部分面积位于像素狭缝160a内,每一第二共用分支144的少部分面积位于像素狭缝160a外。多个第一像素分支162,多个第二像素分支164、多个像素弯曲部166、连接部168及连接部169属于同一导电层且彼此电性连接。在本实施例中,像素电极160例如是透明电极层。透明电极层的材质包括金属氧化物,例如:铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物、或其它合适的氧化物、或者是上述至少二者的堆叠层。然而,本发明不限于此,在其它实施例中,像素电极160也可以是反射电极层、或反射电极层与透明电极层的组合。
图3为第一比较例的像素结构的上视示意图。请参照图1及图3,第一比较例的像素结构200与本实施例的像素结构100类似,惟第一比较例的像素结构200的共用电极240为整面状而不具狭缝。图4示出本发明一实施例的像素结构100的像素电极160与共用电极140之间的等电位曲线。图5示出第一比较例的像素结构200的像素电极160与共用电极240之间的等电位曲线。请参照图1,在本实施例中,多个第一像素分支162与多个第一共用分支142交替排列,且第一像素分支162的延伸方向d1与第一共用分支142的延伸方向y夹有第一锐角θ1。也就是说,共用电极140的第一共用狭缝140a大致上呈直条状且与倾斜的第一像素分支162重叠。请参照图4及图5,藉此,相较于第一比较例的像素结构200,本实施例的像素结构100能使第一像素分支162与共用电极140之间的电位曲线更向上(即朝图1及图3所示的垂直投影方向z的反方向)分布,进而缩短采用像素结构100的液晶显示屏的反应时间(response time)。类似地,在本实施例中,多个第二像素分支164与多个第二共用分支144交替排列,且第二像素分支164的延伸方向d2与第二共用分支144的延伸方向-y夹有第二锐角θ2。也就是说,共用电极140的第二共用狭缝140b大致上呈直条状且与倾斜的第二像素分支164重叠。请参照图4及图5,藉此,相较于第一比较例的像素结构200,本实施例的像素结构100能使第二像素分支164与共用电极140之间的电位曲线更向上分布,进而缩短反应时间。举例而言,采用第一比较例的像素结构200的液晶显示屏的反应时间为38.14毫秒(ms),采用本实施例的像素结构100的液晶显示屏的反应时间为35.65毫秒(ms),采用本实施例的像素结构100的液晶显示屏的反应时间缩短7%。
此外,在本实施例中,第一像素分支162的延伸方向d1与第二像素分支164的延伸方向d2不同,因此分别位于第一像素分支162与第二像素分支164上的液晶会朝不同方向排列,而形成多个区域(domains)。藉此,采用像素结构100的液晶显示屏不但能缩短反应时间,还保有广视角及低色偏的特性。
图6示出本发明一实施例的部分像素结构100所在处的亮度。图7示出第二比较例的部分像素结构300所在处的亮度。第二比较例的像素结构300与本实施例的像素结构100类似,惟第二比较例的像素结构300的共用电极340不具本实施例的共用电极140的共用弯曲部146、连接部148a、连接部148b及连接部148c。也就是说,如图7所示,第二比较例的共用电极340具有多个直条状狭缝340a,且每一直条状狭缝340a与对应的一个第一像素分支162及一个第二像素分支164重叠。请参照图7,在第二比较例中,像素弯曲部166附近区域R的液晶排列不佳,而暗线(disclination line)形成的面积较大。请参照图6,在本实施例中,通过连接部148a、连接部148b、连接部148c及共用弯曲部146形成的枝状导电图案,像素电极160的像素弯曲部166附近区域R的液晶排列较佳,暗线的形成面积很小。因此,采用本实施例的像素结构100的液晶显示屏的穿透率佳。
图8为第三比较例的像素结构的上视示意图。请参照图1及图8,第三比较例的像素结构400与本实施例的像素结构100类似,惟第三比较例的像素结构400的共用电极440的狭缝440a非直条状,第三比较例的共用电极440的狭缝440a与像素狭缝160a切齐(align)。图9示出采用本发明一实施例的像素结构100的液晶显示屏的驱动电压对穿透率的曲线S100,以及采用第三比较例的像素结构400的液晶显示屏的驱动电压对穿透率的曲线S400。由图9可知,采用本实施例的像素结构100的液晶显示屏在各驱动电压下的穿透率明显高于采用第三比较例的像素结构400的液晶显示屏。
综上所述,本发明一实施例的像素结构包括薄膜晶体管、与薄膜晶体管电性连接的像素电极、共用电极以及位于共用电极与像素电极之间的绝缘层。像素电极且具有多个第一像素分支。共用电极具有多个第一共用分支。多个第一像素分支与多个第一共用分支交替排列,且多个第一像素分支的延伸方向与多个第一共用分支的延伸方向夹有第一锐角。藉此,第一像素分支与共用电极之间的等电位曲线会向上分布,进而缩短采用像素结构的液晶显示屏的反应时间。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (10)
1.一种像素结构,其特征在于,包括:
薄膜晶体管;
像素电极,与所述薄膜晶体管电性连接,且具有多个第一像素分支;
共用电极,具有多个第一共用分支,其中所述多个第一像素分支与所述多个第一共用分支交替排列,且所述多个第一像素分支的延伸方向与所述多个第一共用分支的延伸方向夹有第一锐角;以及
绝缘层,位于所述共用电极与所述像素电极之间。
2.根据权利要求1所述的像素结构,其特征在于,所述多个第一共用分支定义多个第一共用狭缝,每一第一像素分支与对应的一个第一共用狭缝部分重叠且与对应的一个第一共用分支部分重叠。
3.根据权利要求1所述的像素结构,其特征在于,所述像素电极还具有多个第二像素分支,其中所述多个第一像素分支的延伸方向与所述多个第二像素分支的延伸方向不同;所述共用电极还具有多个第二共用分支,其中所述多个第一共用分支的延伸方向与所述多个第二共用分支的延伸方向相反,所述多个第二像素分支与所述多个第二共用分支交替排列,而所述多个第二像素分支的延伸方向与所述多个第二共用分支的延伸方向夹有第二锐角。
4.根据权利要求3所述的像素结构,其特征在于,所述多个第二共用分支定义多个第二共用狭缝,每一第二像素分支与对应的一个第二共用狭缝部分重叠且与对应的一个第二共用分支部分重叠。
5.根据权利要求3所述的像素结构,其特征在于,所述像素电极还具有多个像素弯曲部,所述多个像素弯曲部连接于所述多个第一像素分支与所述多个第二像素分支之间,其中所述多个第一像素分支、所述多个第二像素分支以及所述多个像素弯曲部定义所述像素电极的多个像素狭缝。
6.根据权利要求3所述的像素结构,其特征在于,所述共用电极还具有多个共用弯曲部,连接于所述多个第一共用分支与所述多个第二共用分支之间。
7.根据权利要求6所述的像素结构,其特征在于,所述像素电极还具有多个像素弯曲部,所述多个像素弯曲部连接于所述多个第一像素分支与所述多个第二像素分支之间,而所述多个像素弯曲部与所述多个共用弯曲部重叠。
8.根据权利要求6所述的像素结构,其特征在于,所述共用电极还具有连接部,连接于所述多个共用弯曲部之间。
9.根据权利要求8所述的像素结构,其特征在于,所述连接部的延伸方向与所述多个第一共用分支部的延伸方向以及所述多个第二共用分支的延伸方向垂直。
10.根据权利要求8所述的像素结构,其特征在于,所述连接部、所述多个共用弯曲部以及所述多个第一共用分支定义所述共用电极的多个第一共用狭缝,所述连接部、所述多个共用弯曲部以及所述多个第二共用分支定义所述共用电极的多个第二共用狭缝,所述多个第一共用狭缝及所述多个第二共用狭缝分别位于所述连接部的相对两侧。
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JP2003186034A (ja) * | 2001-12-19 | 2003-07-03 | Hitachi Ltd | アクティブマトリクス型液晶表示装置 |
CN202583658U (zh) * | 2012-05-28 | 2012-12-05 | 京东方科技集团股份有限公司 | 一种tft阵列基板、液晶面板以及液晶显示器 |
US20160187736A1 (en) * | 2014-12-30 | 2016-06-30 | Xiamen Tianma Micro-Electronics Co., Ltd. | Array substrate, display panel and display device |
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JP2003186034A (ja) * | 2001-12-19 | 2003-07-03 | Hitachi Ltd | アクティブマトリクス型液晶表示装置 |
CN202583658U (zh) * | 2012-05-28 | 2012-12-05 | 京东方科技集团股份有限公司 | 一种tft阵列基板、液晶面板以及液晶显示器 |
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