CN109765147A - A kind of ultrasonic phased array levitation device and its working method - Google Patents
A kind of ultrasonic phased array levitation device and its working method Download PDFInfo
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- CN109765147A CN109765147A CN201811573404.4A CN201811573404A CN109765147A CN 109765147 A CN109765147 A CN 109765147A CN 201811573404 A CN201811573404 A CN 201811573404A CN 109765147 A CN109765147 A CN 109765147A
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Abstract
The invention discloses a kind of ultrasonic phased array levitation device and its working methods, PC host computer takes one-way communication, four impulse ejection modules are successively separately connected after USB serial communication modular and FPGA delay algorithm computing module, four impulse ejection modules are connected through corresponding signal gain sine output module and ultrasonic phase array probe respectively；PC host computer is for sending focal coordinates, USB serial communication modular is for carrying out data transmission PC host computer and FPGA delay algorithm computing module, FPGA delay algorithm computing module for realizing delayed data calculating and transmission, impulse ejection module is used to send the pulse signal after delay, signal gain sine output module is used to exporting ultrasonic probe resonance into sinusoidal signal, and ultrasonic phase array is popped one's head in for issuing ultrasonic wave.Circuit design of the present invention is simple, and difficulty is small, cheap, focuses and delay precision height is, it can be achieved that delay control precision reaches 1ns, output sine wave signal channel is more.
Description
Technical field
The invention belongs to supersonic wave suspended technical fields, and in particular to a kind of ultrasonic phased array levitation device and its work
Method.
Background technique
Supersonic wave suspended is using high-intensitive sound field, and generation acoustic radiation pressure balances each other with the gravity for being suspended object, thus
It is suspended the object being put into sound field；Typical standing-wave arrangement (commonly referred to as uniaxial) by a circular energy converter and
One reflector composition, these energy converters are coaxially arranged and are separated by a distance.When the reflection end and transmitting terminal of ultrasonic wave
Between distance be ultrasonic wave half-wavelength integral multiple when, ultrasonic wave can be superimposed repeatedly between transmitting terminal and reflection end, thus
The standing wave of a high pressure amplitude is established between transmitter and concave reflector.The high sound intensity standing wave of formation will be by medium by spoke
It penetrates acoustic pressure to act on the sample in stationary field, allows for sample in this way and suspend.Ultrasound suspending technology and magnetic suspension surpass
The technologies such as suspension, pneumatic suspension difference is led, acoustic levitation has the advantages that any substance that suspends, to the physical chemistry for being suspended object
Property is mainly used for the research of individual particle or droplet etc. without particular/special requirement.
Commonly used luffing rod-type ultrasonic transducer in the prior art does standing wave suspension research and then needs equipment by transmitting terminal
It is formed with reflection end, luffing rod-type ultrasonic transducer is sufficiently bulky, is not easy to move, and expensive, the transducing of a set of single shaft
Device price members up to ten thousand.Ultrasound suspending can also be made into phased array form, be chiefly used in studying the mobile transport etc. of object, phased formation
Formula can meet most suspension application, but be made into phased array using luffing rod-type ultrasonic transducer then cost volume substantially mentions
Height, and ultrasonic transducer itself and its matched driving equipment circuit are very complicated, power consumption is very big, needs tens to arrive several hectowatts
Driving power causes the piezoelectric material in energy converter easily to generate heat, and cannot work long hours.Traditionally, postponed using programmable silicon
Line is used for delay compensation, however for dynamic focusing, this large amount of delay tap of focusing system needs may be programmed with complicated
Multipath delay line circuit.Other than system complexity, the hardware of delay line is bulky and expensive, it is also difficult to accomplish accurate
Delay positioning, ultrasound focusing effect are bad；Driving equipment mostly uses sinewave output, it is therefore desirable to analog-digital chip, due to
Pin limitation is difficult to the sinewave output on 100 tunnels or more, to circuit design requirements height.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is that providing a kind of design difficulty
It is small, it is cheap, it focuses and delay precision is high, export the ultrasonic phased array levitation device more than sinusoidal signal channel and its work
Method, improve large volume existing for current luffing rod-type ultrasonic transducer, high-power, circuit is complicated, delay low precision, output just
The problems such as string signal channel is few.
The invention adopts the following technical scheme:
A kind of ultrasonic phased array levitation device, including PC host computer, USB serial communication modular, FPGA delay algorithm meter
Calculate module, impulse ejection module, signal gain sine output module and ultrasonic phase array probe；PC host computer takes one-way communication
Mode, is successively separately connected four impulse ejection modules after USB serial communication modular and FPGA delay algorithm computing module, and four
A impulse ejection module is connected through corresponding signal gain sine output module and ultrasonic phase array probe respectively；PC host computer is used
In sending focal coordinates, USB serial communication modular is used to PC host computer and FPGA delay algorithm computing module carrying out data biography
Defeated, FPGA delay algorithm computing module is for realizing the calculating and transmission of delayed data, and impulse ejection module is for sending delay
Pulse signal afterwards, signal gain sine output module are used to ultrasonic probe resonance exporting sinusoidal signal, ultrasonic phase array
Probe is for issuing ultrasonic wave.
Specifically, FPGA delay algorithm computing module includes fpga chip, SDRAM chip, Flash chip, jtag interface
Circuit, power interface and voltage transformation module, usb communication chip, crystal oscillating circuit and reset circuit；SDRAM chip and Flash core
Piece is connected respectively on the pin of fpga chip；JTAG interface circuit connects on the specific download debugging pin of fpga chip, uses
It is debugged in the downloading of program and plate grade；Power interface and voltage transformation module export the accurate voltage confession of 3.3,2.5,1.2V respectively
FPGA and other circuits use；Usb communication chip uses serial I/O mode, is connected with the common pin of fpga chip；
Crystal oscillating circuit uses the frequency of 50M, provides accurate clock source signals for fpga chip；Reset circuit and fpga chip it is general
Pin connection, the reset for program.
Further, FPGA delay algorithm computing module is connected using 13*4+1 root twisted pair with 4 impulse ejection modules.
Specifically, ultrasonic phase array probe includes ultrasonic phase array plate and ultrasonic probe, on each ultrasonic phase array plate solely
It erects and sets 100 ultrasonic probes, each ultrasonic probe is individually connect with a signal gain sine output module, uses sine wave
The each ultrasonic probe of independent control, the optional diameter of ultrasonic probe are 10~16mm.
A kind of working method of ultrasonic phased array levitation device, comprising the following steps:
S1, PC host computer are communicated by USB serial communication modular with FPGA delay algorithm computing module, by need to focus
Coordinate point data XYZ is sent to FPGA delay algorithm computing module after the conversion of USB serial communication modular for realizing next stage
Delay algorithm；
S2, FPGA delay algorithm computing module carry out data communication with 4 impulse ejection modules respectively；
The realization of S3, FPGA delay algorithm computing module delay algorithm；
S4, each impulse ejection module realize the independent delayed pulse signal in 100 tunnels；
S5, signal gain sine output module increase the 40KHZ square-wave pulse that upper level impulse ejection module exports
Benefit amplification；
S6, the clock signal that clock is become to 4 tunnel phase phase difference 1ns using PLL IP kernel program by the method for phase shift,
Realize high-precision delay pulse emission control when ultrasonic phase array probe focusing delay.
Specifically, FPGA delay algorithm computing module uses 13*4+1 root twisted pair and 4 impulse ejection moulds in step S2
Block is connected, and 12 in 13 twisted pairs are transmitted as data, and the data that simultaneous transmission is one 12 are up to the decimal system
4096, remaining 1 is read the enable signal r_ of the data fifo in FPGA delay algorithm computing module as impulse ejection module
En informs that the FPGA delay algorithm computing module data fifo is read by next stage impulse ejection module, notice FPGA delay
Algorithm computing module sends delayed data in the FIFO in corresponding impulse ejection module；Last 1 twisted pair is as number
According to total clock line of transmission, it is connected respectively with 4 impulse ejection modules.
Specifically, using four kinds of multipliers of addition subtraction multiplication and division, generating the road 100*4 delayed data in step S3 and respectively corresponding 4
Impulse ejection module, and the 100*4 data are respectively present in 4 FIFO, it calls, owns for corresponding impulse ejection module
FPGA program write using Quartus II.
Further, by delay compensation algorithm FIFO is serially read in the way of be converted into reading parallel in the way of, surpass
The fixed vibration frequency position of sonic probe is 40KHZ, and clock signal position CLK_1, CLK_1/40KHZ are LPM_COUNTER IP kernel meter
The number device greatest measure MAX to be counted, delayed data keep initial value if being less than MAX, if more than MAX, then subtract the whole of MAX
Multiple, until being less than MAX and being positive number, then using the value as the delayed data amount in the channel；
Coordinate points are sent to FPGA delay algorithm computing module from host computer, are carried out delayed data calculating, are stored in the grade
In FIFO, impulse ejection module obtains delayed data from upper level FPGA delay algorithm computing module, is stored in this grade of FIFO and carries out
In data buffer storage, data fifo write-in reads as serial mode, when needing to call data, the series read-out from this grade of FIFO,
One clock cycle reads a data, and each data are subtracted to the reading bring retardation of the data, realizes serial turn simultaneously
Capable reading data.
Specifically, utilizing LPM_COUNTER IP kernel counter program and side in each impulse ejection module in step S4
Wave impulse sends program, and by two parts integration procedure to top-level module, top-level module is calculated by receiving upper level FPGA delay
The delayed data calculated in method computing module is compensated into the top-level module, and LPM_COUNTER IP kernel counter journey is arrived in compensation
In sequence, according to delay data, delay data is set in counter by LPM_COUNTER IP kernel counter, and is started counting,
One is provided after counting completely and counts full enable signal, notifies square-wave pulse to send program and start to send one group of square wave arteries and veins with this
Punching；Square-wave pulse sends program and realizes the timing reversion of level using clock signal and counter to realize.
Specifically, square-wave pulse signal is transported to pulse transformer through power amplifier chips gain in step S5, using level-one
Resonant LC-circuit makes pulse transformer, lc circuit, reaches resonant state, configuration circuit ginseng in 40KHZ jointly with ultrasonic probe
Number makes 40KHZ square-wave pulse resonance export the positive and negative alternate sine wave exciting signal of 40KHZ to ultrasonic probe.
Compared with prior art, the present invention at least has the advantages that
A kind of ultrasonic phased array levitation device of the present invention, the present invention is by simple circuit design with regard to exportable sine wave
Signal is avoided using complicated circuit caused by digital-to-analogue chip, delay line chip etc., and using the method for digital delay, is passed through
Delay compensation algorithm and phase shifting method are realized and export high-precision delay pulse, and single I/O mouthfuls i.e. exportable sine wave all the way is believed
Number, therefore exportable signal path number greatly improves.
Further, using the realization of hardware realization delay algorithm, main purpose is to improve FPGA delay algorithm meter
The speed for calculating module and the transmission of impulse ejection module data, using the GPIO interface of FPGA, using 12 radicals according to transmission twisted pair,
Hardware circuit can be not only simplified, and simplify other in the data of rising edge simultaneous transmission one 12 of a clock
The complexity of communication protocol bring program.
Further, using unconventional amplitude transformer ultrasonic transducer, but cheap ranging ultrasonic probe, it should
The optional diameter of ultrasonic probe is desirable in 10~16mm range, volume very little, is easy to rearrange various phased array shapes, and big
Amplitude reduction design cycle and cost.
Invention additionally discloses a kind of working method of ultrasonic phased array levitation device, using delay compensation algorithm by FIFO
The mode serially read is converted into the mode of " parallel " reading, using by clock phase shifting method become 4 tunnel phase phase difference 1ns when
Clock signal can realize delay control essence by clock chip selection signal since each channel has independent driving circuit
Degree reaches 1ns.To realize probe focusing delay when high-precision delay pulse emission control, reduce sound wave minor lobe influence and
Acoustic pressure loss, improves supersonic wave suspended.
Further, the present invention does not use the i.e. exportable high-precision pulse in 100 road of digital-to-analogue chip expended more than GPIO mouthfuls
Sine wave signal, but the output of sine wave is directly realized using resonance circuit, therefore each GPIO mouthfuls is passed through late-class circuit
Exportable sine wave avoids traditional approach using digital-to-analogue chip to the limitation more than pin out requirements, therefore avoids to adopt originally
The sine wave on more than ten tunnels can only be exported with the identical fpga chip, the few limitation of paths increases substantially port number.
Further, impulse ejection module realizes the independent delayed pulse signal in 100 tunnels, which is prolonged by receiving FPGA
The delayed data of slow algorithm computing module, without directly reading from ROM/RAM or SDRAM, therefore greatly reduces resource and accounts for
With rate, and convenient for doing real-time dynamic focusing.The purpose of the module is 100 road delayed pulse signals of output, respectively through correspondence
Signal gain sine output module after, for motivate ultrasonic probe generate ultrasonic wave.
In conclusion circuit design of the present invention is simple, difficulty is small, cheap, focuses and delay precision height is, it can be achieved that prolong
Control precision reaches 1ns late, and output sine wave signal channel is more.
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Detailed description of the invention
Fig. 1 is general structure schematic diagram of the present invention；
Fig. 2 is FPGA delay algorithm computing module connection schematic diagram of the present invention；
Fig. 3 is the procedure simulation schematic diagram of 100 road delay pulses of the invention；
Fig. 4 is the schematic diagram of pumping signal generation module of the present invention；
Fig. 5 is the arrangement schematic diagram of Ultrasonic Phased Array array of the present invention.
Specific embodiment
Referring to Fig. 1, the present invention provides a kind of ultrasonic phased array levitation device, including PC host computer, USB serial ports are logical
Believe module, FPGA delay algorithm computing module, impulse ejection module, signal gain sine output module and ultrasonic phase array are visited
Head；PC host computer takes one-way communication, successively after USB serial communication modular and FPGA delay algorithm computing module respectively
Four impulse ejection modules are connected, four impulse ejection modules are respectively through corresponding signal gain sine output module and ultrasonic phase
Control battle array probe connection.
PC host computer connects USB serial communication modular by usb bus, and USB serial communication modular connects FPGA delay and calculates
Method computing module, FPGA delay algorithm computing module are connected using 13*4+1 root twisted pair with 4 impulse ejection modules, 4 arteries and veins
Rush transmitting module be connected respectively with a signal gain sine output module and ultrasonic phase array plate and probe be connected.
FPGA delay algorithm computing module circuit is using the circuit structure first having, it is only necessary to do simplification appropriate, will to the greatest extent may be used
I/O structure more than energy is flowed out to export for signal and be used.FPGA delay algorithm computing module include fpga chip, SDRAM chip,
Flash chip, JTAG interface circuit, power interface and voltage transformation module, usb communication chip, crystal oscillating circuit, reset circuit its
His configuration circuit etc..SDRAM chip and Flash chip are connected respectively on the pin of fpga chip, remove power pins and clock
Pin connection all may be connected on the universal input output pin of fpga chip outside needing to pay attention to；JTAG interface circuit needs to connect
It connects on the specific download debugging pin of fpga chip, downloading and the debugging of plate grade for program；Power interface and voltage modulus of conversion
It is 5V that block, which needs input power, and by decompression chip, export 3.3 respectively, 2.5, the accurate voltage of 1.2V for FPGA and other
Circuit uses；Usb communication chip uses serial I/O mode, is connected with the common pin of fpga chip；Crystal oscillator electricity
Road uses the frequency of 50M, provides accurate clock source signals for fpga chip；Reset circuit is connected to the common pin of fpga chip
It is upper, the reset for program.
Fpga chip uses EC4CE10 model, which removes the configuration circuit of above-mentioned FPGA, it is general to have there remains 124
The reason of pin interface fully meets the requirement of 100 road signals of output, selects the signal is that the signal is common on the market, circuit
It is relatively simple, it is cheap.
Ultrasonic phase array probe includes 4 ultrasonic phase array plates and 400 ultrasonic probes, on each ultrasonic phase array plate solely
100 ultrasonic probes are found, each probe is individually connect with a signal gain sine output module, uses sine wave independent control
Each ultrasonic probe realizes accurate sound focusing and suspension function after joined time delay, as shown in Figure 5.
A kind of working method of ultrasonic phased array levitation device of the present invention, comprising the following steps:
S1, PC host computer are communicated by USB serial communication modular with FPGA delay algorithm computing module；
USB serial communication modular and FPGA delay algorithm computing module design and produce on the same pcb board, pass through data
Serial mode, PC host computer is by tri- data of coordinate point data XYZ for needing to focus by the conversion transmission of USB serial communication modular
The realization of next stage delay algorithm is carried out to FPGA delay algorithm computing module.
S2, FPGA delay algorithm computing module carry out data communication with 4 impulse ejection modules respectively；
To realize that the high speed data transfer being simply easily achieved, the present invention pass through the GPIO of FPGA delay algorithm computing module
Interface is respectively connected with using 13*4+1 root twisted pair and 4 impulse ejection modules, and 12 transmit as data in 13 twisted pairs,
Data that can be simultaneous transmission one 12 are up to the decimal system 4096,1 as impulse ejection module and read FPGA delay algorithm
The enable signal r_en of data fifo in computing module informs that the FPGA delay algorithm computing module data fifo is next
Grade impulse ejection module is read, and notice FPGA delay algorithm computing module sends delayed data in the impulse ejection module
In FIFO.There are also 1 total clock line as data transmission, which is connected simultaneously with 4 impulse ejection modules, makes
Entire data transmission procedure uses same clock signal, avoids bring delay error between different clocks, further increases transmission
Precision, as shown in Figure 2.
The realization of S3, FPGA delay algorithm computing module delay algorithm；
Using four kinds of multipliers of addition subtraction multiplication and division, i.e. calculation procedure, hardware realization focusing delay algorithm generates the road 100*4 and prolongs
Slow data respectively correspond 4 impulse ejection modules, and the 100*4 data are respectively present in 4 FIFO, for corresponding pulse
Transmitting module calls.All FPGA programs are write using Quartus II.Artificial debugging is carried out using Modelsim.
Delay compensation algorithm and clock phase shift algorithm
By delay compensation algorithm FIFO is serially read in the way of be converted into it is " parallel " read in the way of, fixed vibration of popping one's head in
Dynamic frequency position 40KHZ, clock signal position CLK_1, CLK_1/40KHZ are that LPM_COUNTER IP kernel counter to be counted
Greatest measure MAX, delayed data keeps initial value if being less than MAX, if more than MAX, then subtracts the integral multiple of MAX, until being less than
MAX and be positive number, then using the value as the delayed data amount in the channel, other delayed datas are similarly.
Coordinate points are sent to FPGA delay algorithm computing module from host computer, are carried out delayed data calculating, are stored in the grade
In FIFO, impulse ejection module obtains delayed data from upper level FPGA delay algorithm computing module, is stored in this grade of FIFO and carries out
In data buffer storage, data fifo write-in reads as serial mode, and when needing to call data, series read-out is from this grade of FIFO
Can, it is related to clock signal from FIFO series read-out, therefore serial read will bring delay error, but the reading of each data
It is regular, one data of a usually clock cycle reading, therefore the reading that each data subtract the data is brought
Retardation, the reading data of " transformation from serial to parallel " can be realized from algorithm, therefore each data subtract the reading of the data
Bring retardation calculates in advance in FPGA delay algorithm computing module.
S4, each impulse ejection module realize the independent delayed pulse signal in 100 tunnels；
Program is sent using LPM_COUNTER IP kernel counter program and square-wave pulse in each impulse ejection module, and
By two parts integration procedure to top-level module, top-level module is calculated by receiving in upper level FPGA delay algorithm computing module
Delayed data, compensate into the top-level module, actually compensation into LPM_COUNTER IP kernel counter program.According to
Delay data, delay data is set in counter by LPM_COUNTER IP kernel counter, and is started counting, after counting full
It provides one and counts full enable signal, notify square-wave pulse to send program and start to send one group of square-wave pulse with this.Square-wave pulse
Sending program is then to realize that the timing of level inverts to realize, as shown in Figure 3 using clock signal and counter.
S5, signal gain sine output module use the dedicated power amplifier chips of audio, and upper level impulse ejection module is exported
40KHZ square-wave pulse carry out gain amplification；
It is transported to pulse transformer by configuration circuit, and is passing through level-one resonant LC-circuit, makes pulse transformer, LC electricity
Road reaches resonant state in 40KHZ jointly with ultrasonic probe, and appropriately configured circuit parameter can make 40KHZ square-wave pulse humorous
The vibration output positive and negative alternate sine wave exciting signal of 40KHZ, as shown in Figure 4.
S6, the clock signal that clock is become to 4 tunnel phase phase difference 1ns using PLL IP kernel program by the method for phase shift,
Since each channel has independent driving circuit, it can realize that delay control precision reaches by clock chip selection signal
1ns.To realize high-precision delay pulse emission control when ultrasonic phase array probe focusing delay, reduce the minor lobe shadow of sound wave
The loss of loud and acoustic pressure, improves supersonic wave suspended.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being described and shown in usually here in attached drawing is real
The component for applying example can be arranged and be designed by a variety of different configurations.Therefore, below to the present invention provided in the accompanying drawings
The detailed description of embodiment be not intended to limit the range of claimed invention, but be merely representative of of the invention selected
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without creative efforts
The every other embodiment obtained, shall fall within the protection scope of the present invention.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press
According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention
Protection scope within.
Claims (10)
1. a kind of ultrasonic phased array levitation device, which is characterized in that prolong including PC host computer, USB serial communication modular, FPGA
Slow algorithm computing module, impulse ejection module, signal gain sine output module and ultrasonic phase array probe；PC host computer is taken
One-way communication is successively separately connected four pulse hairs after USB serial communication modular and FPGA delay algorithm computing module
Module is penetrated, four impulse ejection modules are connected through corresponding signal gain sine output module and ultrasonic phase array probe respectively；
PC host computer is used for for sending focal coordinates, USB serial communication modular by PC host computer and FPGA delay algorithm computing module
Carry out data transmission, calculating and transmission of the FPGA delay algorithm computing module for realizing delayed data, impulse ejection module use
Pulse signal after sending delay, signal gain sine output module are used to ultrasonic probe resonance exporting sinusoidal signal,
Ultrasonic phase array is popped one's head in for issuing ultrasonic wave.
2. ultrasonic phased array levitation device according to claim 1, which is characterized in that FPGA delay algorithm computing module
Including fpga chip, SDRAM chip, Flash chip, JTAG interface circuit, power interface and voltage transformation module, usb communication
Chip, crystal oscillating circuit and reset circuit；SDRAM chip and Flash chip are connected respectively on the pin of fpga chip；JTAG connects
Downloading and the debugging of plate grade on the specific download debugging pin of mouth circuit connection fpga chip, for program；Power interface and electricity
Pressure conversion module exports 3.3 respectively, 2.5, the accurate voltage of 1.2V uses for FPGA and other circuits；Usb communication chip uses
Serial I/O mode is connected with the common pin of fpga chip；Crystal oscillating circuit uses the frequency of 50M, mentions for fpga chip
For accurate clock source signals；The connection of the common pin of reset circuit and fpga chip, the reset for program.
3. ultrasonic phased array levitation device according to claim 2, which is characterized in that FPGA delay algorithm computing module
It is connected using 13*4+1 root twisted pair with 4 impulse ejection modules.
4. ultrasonic phased array levitation device according to claim 1, which is characterized in that ultrasonic phase array probe includes super
Sound phased array plate and ultrasonic probe are independently arranged 100 ultrasonic probes on each ultrasonic phase array plate, and each ultrasonic probe is independent
It is connect with a signal gain sine output module, using each ultrasonic probe of sine wave independent control, ultrasonic probe is optional straight
Diameter is 10~16mm.
5. a kind of working method of ultrasonic phased array levitation device according to claim 1, which is characterized in that including following
Step:
S1, PC host computer are communicated by USB serial communication modular with FPGA delay algorithm computing module, the coordinate that needs are focused
Point data XYZ is sent to FPGA delay algorithm computing module after the conversion of USB serial communication modular for realizing next stage delay
Algorithm；
S2, FPGA delay algorithm computing module carry out data communication with 4 impulse ejection modules respectively；
The realization of S3, FPGA delay algorithm computing module delay algorithm；
S4, each impulse ejection module realize the independent delayed pulse signal in 100 tunnels；
The 40KHZ square-wave pulse that upper level impulse ejection module exports is carried out gain and put by S5, signal gain sine output module
Greatly；
S6, the clock signal that clock is become to 4 tunnel phase phase difference 1ns using PLL IP kernel program by the method for phase shift are realized
High-precision delay pulse emission control when ultrasonic phase array probe focusing delay.
6. the working method of ultrasonic phased array levitation device according to claim 5, which is characterized in that in step S2,
FPGA delay algorithm computing module is connected using 13*4+1 root twisted pair with 4 impulse ejection modules, 12 in 13 twisted pairs
Root is transmitted as data, the data that simultaneous transmission is one 12, is up to the decimal system 4096, and remaining 1 is used as impulse ejection mould
Block reads the enable signal r_en of the data fifo in FPGA delay algorithm computing module, informs FPGA delay algorithm computing module
The data fifo is read by next stage impulse ejection module, and notice FPGA delay algorithm computing module sends delayed data to
In FIFO in corresponding impulse ejection module；Total clock line that last 1 twisted pair is transmitted as data, respectively with 4 arteries and veins
Transmitting module is rushed to be connected.
7. the working method of ultrasonic phased array levitation device according to claim 5, which is characterized in that in step S3, benefit
It with four kinds of multipliers of addition subtraction multiplication and division, generates the road 100*4 delayed data and respectively corresponds 4 impulse ejection modules, and by the 100*4
Data are respectively present in 4 FIFO, are called for corresponding impulse ejection module, and all FPGA programs are compiled using Quartus II
It writes.
8. the working method of ultrasonic phased array levitation device according to claim 7, which is characterized in that utilize delay compensation
The mode that algorithm serially reads FIFO is converted into the mode read parallel, and the fixed vibration frequency position of ultrasonic probe is 40KHZ, when
Clock signal position CLK_1, CLK_1/40KHZ are the LPM_COUNTER IP kernel counter greatest measure MAX to be counted, delay
Data keep initial value if being less than MAX, if more than MAX, then subtract the integral multiple of MAX, until being less than MAX and being positive number, then will
Delayed data amount of the value as the channel；
Coordinate points are sent to FPGA delay algorithm computing module from host computer, progress delayed data calculating is stored in this grade of FIFO,
Impulse ejection module obtains delayed data from upper level FPGA delay algorithm computing module, is stored in this grade of FIFO and carries out data buffer storage
In, data fifo write-in reads as serial mode, when needing to call data, the series read-out from this grade of FIFO, and a clock
Period reads a data, and each data are subtracted to the reading bring retardation of the data, realize the reading of transformation from serial to parallel
Data.
9. the working method of ultrasonic phased array levitation device according to claim 5, which is characterized in that in step S4, often
Program is sent using LPM_COUNTER IP kernel counter program and square-wave pulse in a impulse ejection module, and by two parts journey
Sequence is integrated into top-level module, and top-level module passes through the delayed data for receiving and calculating in upper level FPGA delay algorithm computing module,
It compensates in the top-level module, compensates into LPM_COUNTER IP kernel counter program, according to delay data, LPM_
Delay data is set in counter by COUNTER IP kernel counter, and is started counting, and provides a counting after counting completely
Full enable signal notifies square-wave pulse to send program and start to send one group of square-wave pulse with this；Square-wave pulse sends program and utilizes
Clock signal and counter realize that the timing of level inverts to realize.
10. the working method of ultrasonic phased array levitation device according to claim 5, which is characterized in that in step S5, side
Wave pulse signal is transported to pulse transformer through power amplifier chips gain, using level-one resonant LC-circuit, makes pulse transformer, LC
Circuit reaches resonant state in 40KHZ jointly with ultrasonic probe, and configuration circuit parameter exports 40KHZ square-wave pulse resonance
The positive and negative alternate sine wave exciting signal of 40KHZ is to ultrasonic probe.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110118593A (en) * | 2019-05-23 | 2019-08-13 | 浙江大学 | A kind of novel laboratory acoustic velocity measurement device |
| CN110921334A (en) * | 2019-11-21 | 2020-03-27 | 杭州电子科技大学 | Concave spherical surface double-emitter ultrasonic array axial suspension moving device and method |
| CN111439592A (en) * | 2020-04-06 | 2020-07-24 | 哈尔滨工业大学 | Compensation method for ultrasonic levitation transmission distance based on excitation phase |
| CN114217090A (en) * | 2021-12-07 | 2022-03-22 | 中国科学院大学 | Sensor control device, ultrasonic velocimeter and ultrasonic velocimetry system |
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| CN114217090B (en) * | 2021-12-07 | 2022-09-23 | 中国科学院大学 | Sensor control device, ultrasonic velocimeter and ultrasonic velocimetry system |
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