CN109755142A - Bonding structure and forming method thereof - Google Patents
Bonding structure and forming method thereof Download PDFInfo
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- CN109755142A CN109755142A CN201910002425.9A CN201910002425A CN109755142A CN 109755142 A CN109755142 A CN 109755142A CN 201910002425 A CN201910002425 A CN 201910002425A CN 109755142 A CN109755142 A CN 109755142A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
The present invention relates to a kind of bonding structures and forming method thereof, comprising: provides two substrates, each substrate includes the metal interconnection of dielectric layer and the exposed top surface being formed in the dielectric layer；Barrier layer is formed with respect to the metal interconnection surface at bonding position in two substrates, and when two substrates are with respect to metal interconnection is provided at bonding position, the top surface of the metal interconnection of larger size forms barrier layer at least in, and the barrier layer is conductive material and the diffusion for capableing of barrier metal atoms；By the opposite bonding in the surface of described two substrates, the barrier layer is located between the metal interconnection of two substrates.The barrier layer can diffusion of the metallic atom to neighbouring dielectric layer in barrier metal interconnection, avoid metallic atom diffusion that the electric property of device is caused to decline and less reliable, improve the reliability of bond devices.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of bonding structure and forming method thereof.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and again
The advantages that writing, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory
The bit density (Bit Density) of memory, while reducing a cost (Bit Cost), three-dimensional flash memories (3D
NAND) technology is rapidly developed.
CMOS electricity in 3D NAND flash memory structure, including memory array structure and above memory array structure
Line structure, the storage array knot and cmos circuit structure are usually respectively formed on two different wafers, then pass through key
Cmos circuit wafer and memory array structure wafer are mutually bonded by conjunction mode, so that the metal interconnection of memory array structure
Connection is bonded with the metal interconnection in cmos circuit structure.
But the bonding face of the metal interconnection of memory array structure and cmos circuit structure in the prior art, it is being bonded
In the heating of process and temperature-fall period and after bonding, metallic atom is easy to happen diffusion and electromigration, so that metal bonding
The problems such as generation hole, causes to leak electricity in face, and electromigration lifetime shortens, so that the reliability decrease of product.In the prior art,
In order to reduce the above problem, need to carry out many adjustment to the chemical mechanical milling tech for forming metal interconnection and can
By the control of property, lead to increased costs.
How to avoid the metal of metal throuth hole contact surface from diffusing in dielectric layer, is current urgent problem to be solved.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of bonding structures and forming method thereof, improve bonding structure
Reliability.
The present invention provides a kind of forming method of bonding structure, comprising: provides two substrates, each substrate includes being situated between
The metal interconnection of matter layer and the exposed top surface being formed in the dielectric layer；In two substrates with respect at bonding position
Metal interconnection surface form barrier layer, and when two substrates are with respect to metal interconnection is provided at bonding position, until
The top surface of few metal interconnection in wherein larger size forms barrier layer, and the barrier layer is conductive material and can
The diffusion of barrier metal atoms；By the opposite bonding in the surface of described two substrates, the barrier layer is located at the metal of two substrates
Between interconnection or between metal interconnection and opposite dielectric layer.
Optionally, before the surface of metal interconnection forms barrier layer, further includes: carried out to the metal interconnection
Selectivity is etched back to or chemical mechanical grinding processing so that selectivity be etched back to or chemical mechanical grinding treated that metal is mutual
Portion, company surface is lower than the dielectric layer surface.
It optionally, include: in the dielectric layer surface shape in the method that the surface of the metal interconnection forms barrier layer
At the mask layer with opening, described be open exposes the top surface of the metal interconnection；In the metal interconnection
Top surface and the exposure mask layer surface form barrier material layer；It removes the mask layer and is located at the mask layer table
The barrier material layer in face forms the barrier layer for being located at the top surface of metal interconnection.
Optionally, the method that the top surface of the metal interconnection forms barrier layer include: in the dielectric layer and
Barrier material layer is formed on the top surface of metal interconnection；Mask layer, the exposure mask are formed in the barrier material layer surface
Layer exposes the barrier material layer of the dielectric layer surface；It is located at dielectric layer surface as exposure mask removal using the mask layer to stop
Material layer；Remove the mask layer.
Optionally, barrier layer is respectively formed on the metal interconnection surface of described two substrates.
Optionally, the barrier layer with a thickness of 5nm~20nm.
Optionally, the material on the barrier layer includes at least one of Co, Ti, Ta, TiN and TaN.
Optionally, the forming method of the metal interconnection includes: the etching dielectric layer, the shape in the dielectric layer
At etched features；The metal material layer for filling the full etched features and overwrite media layer surface is formed, to the metal material
The bed of material carries out chemical mechanical grinding processing, removes the metal material layer of the dielectric layer surface, is formed and is located at the etched features
Interior metal interconnection, and make metal interconnection surface that there is recess, the depth of the recess and blocking to be formed
Thickness degree is related.
Optionally, described two substrates are respectively the first substrate and the second substrate, are formed with first in first substrate
Metal interconnection is formed with the second metal interconnection in second substrate, and the top surface of the first metal interconnection exists
The projection on the second metal interconnection surface is fully located in the top surface of the second metal interconnection；At least in institute
The top surface for stating the second metal interconnection forms barrier layer.
Optionally, further includes: before by the opposite bonding in the surface of described two substrates, to the base for being formed with barrier layer
Bottom surface carries out planarization process.
Technical solution of the present invention also provides a kind of bonding structure, comprising: two substrates, each substrate include medium
The metal interconnection of layer and the exposed top surface being formed in the dielectric layer；The surface of described two substrates is opposite to be bonded
Connection；Two substrates are formed with barrier layer with respect to the metal interconnection surface at bonding position, and when position opposite in two substrates
When the place of setting is provided with metal interconnection, the top surface of the metal interconnection of larger size is formed with blocking at least in
Layer, the barrier layer are conductive material and the diffusion for capableing of barrier metal atoms, and it is opposite that the barrier layer is located at two substrates
Between metal interconnection or between metal interconnection and opposite dielectric layer.
Optionally, the top surface that surface is formed with the metal interconnection on barrier layer is lower than the surface of the dielectric layer at place.
Optionally, the metal interconnection top surface of two substrates is each formed with barrier layer.
Optionally, the barrier layer with a thickness of 5nm~20nm.
Optionally, the material on the barrier layer includes at least one of Co, Ti, Ta, TiN and TaN.
Optionally, described two substrates are respectively the first substrate and the second substrate, are formed with first in first substrate
Metal interconnection is formed with the second metal interconnection in second substrate, and the top surface of the first metal interconnection exists
The projection on the second metal interconnection surface is fully located in the top surface of the second metal interconnection；At least in institute
The top surface for stating the second metal interconnection is formed with the barrier layer.
In the formation scheme of bonding structure of the invention, in two substrates with respect to the metal interconnection table at bonding position
Face forms barrier layer, and when two substrates are with respect to metal interconnection is provided at bonding position, at least in larger ruler
The top surface of very little metal interconnection forms barrier layer, and the barrier layer is conductive material, and is capable of barrier metal atoms
Diffusion；It is subsequent two substrates are bonded again during, can be avoided the intrabasement metal interconnection of bonding face two sides
Interior metallic atom is spread into neighbouring dielectric layer, avoids metallic atom diffusion that the electric property of device is caused to decline
And less reliable, to improve the reliability of the bond devices of formation.
Further, when two substrates are with respect to metal interconnection is provided at bonding position, only larger-size
Metal interconnection surface forms barrier layer, it is possible to reduce after processing step, and reduction bonding between the metal interconnection of two sides
Barrier layer thickness, reduce the connection resistance after bonding between metal interconnection, and the barrier layer also can after bonding
Enough complete support size lesser metal interconnection surfaces, while the metallic atom of para-linkage face two sides plays diffusion barrier work
With.
Detailed description of the invention
Fig. 1 to Figure 13 is the structural schematic diagram of the bonding structure forming process of a specific embodiment of the invention.
Specific embodiment
The specific embodiment of bonding structure provided by the invention and forming method thereof is done specifically with reference to the accompanying drawing
It is bright.
In a specific embodiment of the invention, the forming method of the bonding structure includes: to provide two substrates, each
Substrate includes the metal interconnection of dielectric layer and the exposed top surface in the dielectric layer；It is opposite in two substrates
Metal interconnection surface at bonding position forms barrier layer, and when two substrates are with respect to being provided with metal at bonding position
When interconnection, the top surface of the metal interconnection of larger size forms barrier layer at least in, and the barrier layer is conduction
Material and the diffusion for capableing of barrier metal atoms；By the opposite bonding in the surface of described two substrates, the barrier layer is located at two
Between the opposite metal interconnection of substrate or between metal interconnection and opposite dielectric layer.
Referring to FIG. 1, providing the first substrate, first substrate includes first medium layer 100 and is situated between positioned at described first
First metal interconnection 110 of the exposed top surface in matter layer 100；Referring to FIG. 10, the second substrate is provided, described second
Substrate includes the second metal interconnection of second dielectric layer 1100 and the exposed top surface in the second dielectric layer 1100
Portion 1110.The first metal interconnection 110 and the second metal interconnection 1110 are located at first substrate and the second base
Bottom with respect to bonding position at.
In the specific embodiment, memory array structure, the company of illustrating only in Fig. 1 are also formed in first substrate
Connect the first metal interconnection 110 above the storage array.First metal interconnection, 110 bottom can connect to institute
Memory array structure or other metal interconnection structures are stated, for the memory array structure to be connected to external circuit.
The first metal interconnection 110 can be single structure, and the material of the first metal interconnection 110 can be with
For metal materials such as Cu, Al, Au or Ag.
The first medium layer 100 can for silicon oxide layer, silicon nitride or including silicon oxide layer, silicon nitride layer it is more
Layer heap stack structure.
In this specific embodiment, the first metal interconnection 110 includes the first metal layer 112 and covering institute
112 side wall of the first metal layer is stated, the first non-proliferation between the first metal layer 112 and first medium layer 100 stops
Layer 111.The material of the first metal layer 112 can be the metal materials such as Cu, Al, Au or Ag；First non-proliferation stops
Layer 111 can be one or more material layers in Ti layers, TiN layer, Ta layers and TaN layers.First non-proliferation barrier layer
111 can stop the metal material of the first metal layer 112 to expand along vertical sidewall direction into the first medium layer 100
It dissipates.
It is corresponding, it could be formed with CMOS peripheral circuit structure in second substrate.Connection institute is shown in Figure 11
State the second metal interconnection 1110 of cmos circuit structure.The second metal interconnection 1110 includes second metal layer 1102
Material with the second non-proliferation barrier layer 1101, the second metal layer 1102 can be the metal materials such as Cu, Al, Au or Ag；
Second non-proliferation barrier layer 1101 can be one or more material layers in Ti layers, TiN layer, Ta layers and TaN layers.
In the specific embodiment, the material of the first metal layer 112 and the second metal layer 1102 is Cu,
The material on first non-proliferation barrier layer 111 and second non-proliferation barrier layer 1101 is Ta or Ta/TaN lamination.
After the first substrate is bonded with the second substrate, the second metal interconnection 1110 and the first metal interconnection 110
Electrical connection.In other specific embodiments, first substrate and the second substrate can also be needed for other through bonding shape
At the wafer or underlying structure of electric connection.
In a specific embodiment of the invention, in two substrates with respect to the metal interconnection surface shape at bonding position
At barrier layer, and when two substrates are with respect to metal interconnection is provided at bonding position, larger size at least in
Metal interconnection surface forms barrier layer, and in bonding process, the barrier layer is located between the metal interconnection of two sides or gold
Belong between interconnection and opposite dielectric layer, can metallic atom effectively in barrier metal interconnection to neighbouring dielectric layer
Interior diffusion and migration.
Forming barrier layer on 110 surface of the first metal interconnection of the first substrate below is example, illustrates barrier layer
Forming process.
Referring to FIG. 2, chemical mechanical grinding processing (CMP) is carried out to the first metal interconnection 110, so that after CMP
110 surface of the first metal interconnection be slightly below 100 surface of first medium layer.
During forming the first metal interconnection 110 in first substrate, make described by CMP
The surface of one metal layer 112 is lower than the surface of the first medium layer 100.Specifically, in a specific embodiment, institute
The forming method for stating the first metal interconnection 110 includes: the etching first medium layer 100, in the first medium layer 100
Interior formation etched features；The metal material layer filled the full etched features and cover 100 surface of first medium layer is formed,
The metal material layer includes non-proliferation barrier material layer and metal layer；Being planarized to the metal material layer (can be with
Using chemical mechanical grinding mode), the metal material layer on 100 surface of first medium layer is removed, is formed and is located at the etching
The first metal interconnection 110 in figure, including the first metal layer 112 and the first non-proliferation barrier layer 111.Described in formation
It after first metal interconnection 110, can be handled with further progress CMP, so that 110 surface of the first metal interconnection has
Fluted 201, the depth of the groove 201 is related to the thickness on barrier layer to be formed.The groove 201 is by CMP process shape
At, specifically, during carrying out CMP to the first metal interconnection 110, it can be using to the first metal interconnection
110, especially there is more highly selective lapping liquid to grind the first metal layer 112.Appropriate adjustment can be passed through
The parameters such as milling time, lapping liquid concentration control the depth of groove of the first metal layer 112.
In another specific embodiment, quarter can also be returned by carrying out selectivity to the first metal interconnection 110
Erosion is so that 110 surface of the first metal interconnection after selectivity is etched back to is slightly below 100 surface of first medium layer.Specifically
, after carrying out planarization to metal material layer and forming the first metal interconnection 110, the first metal interconnection 110 is carried out
It is etched back to, to form the groove 201.In the specific embodiment, due to the selectivity being etched back to, only to first gold medal
112 etching effect of the first metal layer for belonging to interconnection 110 is obvious, so that the surface of the first metal layer 112 is lower than described the
The surface of one dielectric layer 100 forms groove 201.
In order to avoid the thickness on the first barrier layer being subsequently formed is excessive, cause resistance larger, the depth of the groove 201
Degree cannot be excessive；Preferably, the depth of the groove 201 can be 5nm~20nm.
It, can also be to the first metal layer 112 and the first non-proliferation barrier layer in other specific embodiments
111, which carry out selectivity, is etched back to or CMP.
Referring to FIG. 3, on the first medium layer 100 and the top of the first metal interconnection 110 (please referring to Fig. 2)
Barrier material layer 300 is formed on portion surface.Preferably, the full the first metal layer 112 of the filling of barrier material layer 300 pushes up
The groove 201 (please referring to Fig. 2) in portion.
The barrier material layer 300 is conductive material and the diffusion for capableing of barrier metal atoms.In specific reality of the invention
It applies in mode, the material of the barrier material layer 300 includes at least any one material in Co, Ti, Ta, TiN or TaN, or
Barrier material layer 300 described in person can also be lamination layer structure, may include Co layers, Ti layers, Ta layers, in TiN layer or TaN layers
At least one material layer；Or the material of the barrier material layer 300 can also be one in Co, Ti, Ta, TiN or TaN
The alloy material of kind or several compositions.In other specific embodiments, the barrier material layer 300 can also use other
It is capable of the conductive material of barrier metal atoms diffusion, herein without enumerating.It can be according to the first metal layer 112
Specific material, select the material of suitable barrier material layer 300.
The barrier material layer 300 can use physical gas-phase deposition (PVD), chemical vapor deposition process
(CVD), atom layer deposition process (ALD) or other depositing operations that can satisfy deposition uniformity are formed.It is specific at one
In embodiment, the barrier material layer 300 is formed using atom layer deposition process (ALD), it can be to the barrier material layer
300 thickness is accurately controlled.Preferably, the barrier material layer 300 is made to fill the full groove 201, and it is located at groove
300 surface of barrier material layer in 201 is flushed with 100 surface of first medium layer or the table of the slightly below described first medium layer 100
Face.
Referring to FIG. 4, forming mask layer 400 on 300 surface of barrier material layer, the mask layer 400 exposes institute
State the barrier material layer 300 on 100 surface of first medium layer.
The material of the mask layer 400 can be formed after exposure development for photoresist layer.The mask layer 400 is also
It can be other mask layers, such as SiO2, SiN, SiC, agraphitic carbon etc., the forming method packet of the mask layer 400
It includes: after 300 surface of barrier material layer forms mask layer, forming photoresist in the mask material layer surface
Layer, by exposure development and photoetching process, forms the mask layer 400.
It is formed during the mask layer 400, the light mask image used can be to form the first metal interconnection
When 110, the light mask image when first medium layer 100 is etched, it, can be with save the cost without increasing additional light shield.
The position of the mask layer 400 is corresponding with first non-proliferation barrier layer 111, the position of the first metal layer 112, size, makes
The first barrier layer that must be subsequently formed covers the first metal layer 112 and the first non-proliferation barrier layer 111.
In other specific embodiments, the mask layer 400 can also be only located at 112 top of the first metal layer,
So that the first barrier layer being subsequently formed only covers the first metal layer 112.
Referring to FIG. 5, being the blocking material that exposure mask removal is located at 100 surface of first medium layer with the mask layer 400
The bed of material 300 (please refers to Fig. 4), forms the first barrier layer 301；Then, the mask layer 400 (please referring to Fig. 4) is removed.
It can use and the barrier material layer 300 be performed etching with height dry etch process to form described
One barrier layer 301.It is formed after first barrier layer 301, can be removed using wet-etching technology or dry etch process
The mask layer 400.In a specific embodiment, the mask layer 400 is photoresist layer, can use wet etching
Or cineration technics removes the mask layer 400.It, further, can be to described first after removing the mask layer 400
Substrate surface is cleaned, and to remove the impurity on surface, improves subsequent bonding reliability.
Referring to FIG. 6, carrying out planarization process to the first substrate surface for being formed with the first barrier layer 301.
Since in the specific embodiment, the surface on first non-proliferation barrier layer 111 is higher than first after being etched back to
The surface of metal layer 112, so that the part that first barrier layer 301 is located at first non-proliferation barrier layer, 111 surface is high
In the surface of the first medium layer 100.Stop in other specific embodiments, when if forming first barrier layer 301
Material layer 300 (please referring to Fig. 4) thickness is excessive, so that the table on the first barrier layer 301 formed after etch stopper material layer 300
Face is higher than the surface of first medium layer 100.In order to further increase the flatness of the first substrate surface, so that first resistance
301 surface of barrier is flushed with 100 surface of first medium layer or the surface of the slightly below described first medium layer 100, this is specific
In embodiment, planarization process can be further carried out to first substrate surface, eliminate first barrier layer
301 protrusion.The planarization process can be carried out by chemical mechanical milling tech, pass through short time, the chemistry of low-pressure
The convex portion on the first barrier layer 301 is eliminated in mechanical lapping.
In other specific embodiments, if the thickness on first barrier layer 301 is smaller, raised not significant, para-linkage
Influence is smaller, can also be without planarization process.
The depth of first barrier layer, 301 final thickness and the groove 201 (please referring to Fig. 2) is close, be 5nm~
20nm.First barrier layer, 301 thickness is too low, will lead to, and described poor to the diffusion barrier function and effect of metal
The thickness on one barrier layer 301 is excessive and will lead to that resistance is excessive, influences the electrical property of bonding structure, can be according to described first
The specific material on barrier layer 301 selects suitable thickness.
First barrier layer 301 covers entire 112 surface of the first metal layer, avoids in the first metal layer 112
Metallic atom is to external migration or diffusion.And in the specific embodiment, 301 side-walls of the first barrier layer are also formed with
One non-proliferation barrier layer 111, first barrier layer 301 is with first non-proliferation barrier layer 111 jointly by first gold medal
Belong to layer 112 to surround, improves the blocking effect spread to metallic atom.
Fig. 7 to Fig. 9 is please referred to, is in another specific embodiment of the present invention, in the first metal interconnection of the first substrate
Surface forms the structural schematic diagram on the first barrier layer.
Referring to FIG. 7, being formed on 100 surface of first medium layer has opening 701 on the basis of Fig. 2 structure
Mask layer 700, the opening 701 expose the first metal layer 112.In other specific embodiments, the opening
701 can also expose the top of the top surface of the first metal layer 112 and the first non-proliferation barrier layer 111 simultaneously
Surface.
The mask layer 700 can be photoresist or other mask layers, in the specific embodiment, described in formation
During mask layer 700, the light mask image that uses can be to form the first metal interconnection 110 (please referring to Fig. 1)
When, etch the light mask image when first medium layer 100.Photoresist can use negtive photoresist so that exposure development with
And after etching, the opening 701 is formed.
Referring to FIG. 8, on 112 top surface of first non-proliferation barrier layer 111 and the first metal layer and described
700 surface of mask layer forms barrier material layer 800.
Using physical gas-phase deposition, such as magnetron sputtering technique, the barrier material layer 800 is formed, so that described
Barrier material layer 800 is only formed in 112 surface of top surface and the first metal layer of the mask layer 700, the blocking material
The bed of material 800 at least fills the full groove (please referring to Fig. 7), exposes the side wall of the mask layer 700.
Referring to FIG. 9, removing the mask layer 700 (please referring to Fig. 8) and the resistance positioned at 700 surface of mask layer
Obstructing material layer 800 (please refers to Fig. 8), is formed and is located at 112 surface of first non-proliferation barrier layer 111 and the first metal layer
First barrier layer 801.
The mask layer 700 is removed using wet-etching technology, specifically, along the side wall of the mask layer 700, to institute
It states mask layer 700 and carries out lateral etching.The barrier material layer 800 on 700 surface of mask layer is with the mask layer 700
Removal, loses support, is also removed therewith, to only retain first non-proliferation barrier layer 111 and the first metal layer 112
First barrier layer 801 on surface.Planarization process can also be carried out to the first substrate surface for being formed with the first barrier layer 801.
In above-mentioned specific embodiment, barrier layer is formed on the first metal interconnection surface of the first substrate to be bonded,
During stopping bonding, the metallic atom in the first metal interconnection influences bonding reliability to external diffusion.
Please refer to Figure 11, using with method identical in above embodiment, it is mutual in the second metal of second substrate
(the please referring to Figure 10) surface of portion, company 1110 forms the second barrier layer 1103.
Figure 12 is please referred to, by the opposite bonding in the surface of first substrate and the second substrate, first barrier layer 301
And second barrier layer 1103 between the first metal layer 112 and second metal layer 1102, the first metal interconnection
It is electrically connected between the second metal interconnection.
It in a specific embodiment, can be in such a way that dielectric layer be bonded, by first substrate and the second base
Bottom surface Direct Bonding.Pass through 301 He of the first barrier layer between the first metal layer 112 and second metal layer 1102
Second barrier layer 1103 forms electrical connection.Even if on first barrier layer 301 and 1103 surface of the second barrier layer
In the case where lower than place dielectric layer surface, since bonding process needs to carry out at high temperature, such as 25 DEG C~450 DEG C, first
The volume of metal layer 112 and second metal layer 1102 can expand, so that first barrier layer 301 and second resistance
1103 surface of barrier can still contact and be bonded, and form electrical connection.
, can also be after first substrate and the second substrate surface Direct Bonding in other specific embodiments, volume
Outer application pressure further increases the connection reliability between first barrier layer 301 and second barrier layer 1103.
In a specific embodiment of the invention, the top surface of the first metal interconnection is in second metal
The projection on interconnection surface is fully located in the top surface of the second metal interconnection.
Figure 13 is please referred to, in another embodiment of the present invention, the size of the second metal layer 1102 is greater than
The size of the first metal layer 112 only can also form the second barrier layer on the surface of the second metal layer 1102
1103 ', without 112 surface of the first metal layer formed barrier layer, can reduce the first metal layer 112 with it is described
Second metal layer 1102 between connection resistance.Since the 1103 ' size of the second barrier layer is larger, can completely cover
112 surface of the first metal layer, therefore the metallic atom in the first metal layer 112 can also be stopped to spread.
Due to only carrying out metal expansion by second barrier layer 1103 ' between first substrate and the second substrate
It dissipates and stops, the thickness on second barrier layer 1103 ' can be properly increased.In a specific embodiment of the invention, described
The thickness on two barrier layers 1103 ' can be 5nm~30nm.
Multiple metal interconnections, the opposite bonding position of two substrates are conventionally formed in two substrates for needing to be bonded
Place can be each formed with metal interconnection, at this time can be only in the larger-size metal interconnection top surface formation resistance in side
Barrier or opposite two metal interconnection top surfaces are respectively formed barrier layer, after bonding, the metal interconnection of two sides
Between formed electrical connection.
At the opposite bonding of two substrates, can also only have and be formed with metal interconnection in a wherein substrate, and another base
Bottom corresponding position is dielectric layer, needs to form barrier layer in the metal interconnection top surface of side substrate at this time.
In the forming process of the bonding structure of above-mentioned specific embodiment, in two substrates with respect to the gold at bonding position
Belong to interconnection surface and form barrier layer, and when two substrates are with respect to metal interconnection is provided at bonding position, at least exists
Wherein the metal interconnection surface of larger size forms electrically conductive barrier, stops in two substrate bonding process, bonding face two sides
The metallic atom of metal interconnection spread, to improve the reliability of bonding structure.
A specific embodiment of the invention also provides a kind of bonding structure formed using the above method.
Figure 12 is please referred to, is the structural schematic diagram of the bonding structure of the embodiment of the invention.
The bonding structure includes two substrates, and each substrate includes dielectric layer and is formed in the dielectric layer
The metal interconnection of exposed top surface；The surface of described two substrates is opposite to be bonded connection；Two substrates are with respect to bonding position
The metal interconnection surface at place is each formed with barrier layer, and works as in two substrates and be provided with metal interconnection at relative position
When, the top surface of the metal interconnection of larger size is formed with barrier layer at least in, and the barrier layer is conductive material
And it is capable of the diffusion of barrier metal atoms；The surface of described two substrates is opposite to be bonded connection, and the metal of described two substrates is mutual
Company is electrically connected between portion, and the barrier layer is located between the metal interconnection of two substrates.
In the specific embodiment, described two substrates, respectively the first substrate and the second substrate, first substrate
First metal interconnection of the exposed top surface including first medium layer 100 and in the first medium layer 100, institute
Stating the first metal interconnection includes the first metal layer 112 and the first non-proliferation barrier layer 111；Second substrate includes second
Second metal interconnection of dielectric layer 1100 and the exposed top surface in the second dielectric layer 1100, described second
Metal interconnection includes second metal layer 1102 and the second non-proliferation barrier layer 1101.
It is respectively formed on the first metal layer 112 of first substrate, the surface of the second metal layer 1102 of the second substrate
There are the first barrier layer 301 and the second barrier layer 1103.And the surface of the first metal layer 112 and second metal layer 1103 is equal
Lower than the surface of the dielectric layer at place, the surface on first barrier layer 301 and the second barrier layer 1103 is located at described
In one dielectric layer 100 and second dielectric layer 200.
First barrier layer 301 and second barrier layer 1103 include at least appointing in Co, Ti, Ta, TiN or TaN
Anticipate a kind of material or first barrier layer 301 and second barrier layer 1103 can also be lamination layer structure, respectively
Including Co layers, Ti layers, Ta layers, at least one of TiN layer or TaN layers material layer；Or first barrier layer 301 and institute
The material for stating the second barrier layer 1103 can also be the alloy material of one or more of Co, Ti, Ta, TiN or TaN composition.
The thickness on first barrier layer 301 and second barrier layer 1103 is too low, will lead to the diffusion resistance to metal
It is poor to keep off function and effect, and the thickness on first barrier layer 301 and second barrier layer 1103 is excessive will lead to electricity
It hinders excessive, influences the electrical property of bonding structure, it can be according to first barrier layer 301 and second barrier layer 1103
Specific material selects suitable thickness.When of the invention one is specific in embodiment, the thickness on first barrier layer 301
Degree be 5nm~20nm, second barrier layer 1103 with a thickness of 5nm~20nm.
Figure 13 is please referred to, for the structural schematic diagram of the bonding structure of another specific embodiment of the present invention.
In the specific embodiment, the top surface of the first metal interconnection is in the second metal interconnection table
The projection in face is fully located in the top surface of the second metal interconnection, and the size of the first metal layer 112 is less than described
The size of second metal layer 1102.It only is formed with the second barrier layer 1103 ' on the surface of the second metal layer 1102, it can be with
Reduce the connection resistance between the first metal layer 112 and the second metal layer 1102.Due to second barrier layer
1103 ' sizes are larger, can completely cover 112 surface of the first metal layer, therefore can also stop the first metal layer
Metallic atom in 112 is spread.
Due to only carrying out metal expansion by second barrier layer 1103 ' between first substrate and the second substrate
It dissipates and stops, the thickness on second barrier layer 1103 ' can be properly increased.In a specific embodiment of the invention, described
The thickness on two barrier layers 1103 ' can be 5nm~30nm.
At the other positions of bonding structure, it is also possible to that there is metal interconnection in the substrate of side, and other side substrate
Relative position at be dielectric layer, at this point, the metal interconnection top surface is also formed with barrier layer, so that barrier layer position
Between metal interconnection and opposite dielectric layer.
In two substrates of above-mentioned bonding structure, two substrates are formed with respect to the metal interconnection surface at bonding position
There is barrier layer, and when being provided with metal interconnection at relative position in two substrates, at least in the gold of larger size
Belong to interconnection surface and be formed with electrically conductive barrier, metallic atom in the metal interconnection of bonding face two sides can be stopped to expand
It dissipates, to improve the reliability of bonding structure.
In addition, application of the invention is not limited to memory wafer and the diffusion of peripheral cmos circuit wafer bonding hinders
Barrier.Anti-metal is former after bonding can improve bonding by the way of of the invention between actually any form or type wafer
The ability of son diffusion.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications should also regard
For protection scope of the present invention.
Claims (16)
1. a kind of forming method of bonding structure characterized by comprising
Two substrates are provided, each substrate includes the metal of dielectric layer and the exposed top surface being formed in the dielectric layer
Interconnection；
Barrier layer is formed with respect to the metal interconnection surface at bonding position in two substrates, and is bonded position when two substrates are opposite
When the place of setting is provided with metal interconnection, the top surface of the metal interconnection of larger size forms barrier layer at least in,
The barrier layer is conductive material and the diffusion for capableing of barrier metal atoms；
Be bonded the surface of described two substrates is opposite, the barrier layer be located between the opposite metal interconnection of two substrates or
Between metal interconnection and opposite dielectric layer.
2. the forming method of bonding structure according to claim 1, which is characterized in that formed on the surface of metal interconnection
Before barrier layer, further includes: be etched back to metal interconnection progress selectivity or chemical mechanical grinding is handled, so that selection
Property be etched back to or chemical mechanical grinding treated metal interconnection surface is lower than the dielectric layer surface.
3. the forming method of bonding structure according to claim 1, which is characterized in that on the surface of the metal interconnection
The method for forming barrier layer includes: to form the mask layer with opening in the dielectric layer surface, and the opening exposes described
The top surface of metal interconnection；Barrier material is formed in the top surface of the metal interconnection and the exposure mask layer surface
Layer；The mask layer and the barrier material layer positioned at the exposure mask layer surface are removed, the top for being located at metal interconnection is formed
The barrier layer on surface.
4. the forming method of bonding structure according to claim 1, which is characterized in that at the top of the metal interconnection
The method that surface forms barrier layer includes: to form barrier material layer on the dielectric layer and the top surface of metal interconnection；
Mask layer is formed in the barrier material layer surface, the mask layer exposes the barrier material layer of the dielectric layer surface；With
The mask layer is that exposure mask removal is located at dielectric layer surface barrier material layer；Remove the mask layer.
5. the forming method of bonding structure according to claim 1, which is characterized in that mutual in the metal of described two substrates
Portion, company surface is respectively formed barrier layer.
6. the forming method of bonding structure according to claim 1, which is characterized in that the barrier layer with a thickness of 5nm
~20nm.
7. the forming method of bonding structure according to claim 1, which is characterized in that the material on the barrier layer includes
At least one of Co, Ti, Ta, TiN and TaN.
8. the forming method of bonding structure according to claim 1, which is characterized in that the formation side of the metal interconnection
Method includes: the etching dielectric layer, forms etched features in the dielectric layer；It is formed and fills the full etched features and cover
The metal material layer of lid dielectric layer surface carries out chemical mechanical grinding processing to the metal material layer, removes the dielectric layer
The metal material layer on surface forms the metal interconnection being located in the etched features, and makes metal interconnection surface
With recess, the depth of the recess is related to barrier layer thickness to be formed.
9. the forming method of bonding structure according to claim 1, which is characterized in that described two substrates are respectively first
Substrate and the second substrate are formed with the first metal interconnection in first substrate, are formed with the second gold medal in second substrate
Belong to interconnection, projection of the top surface of the first metal interconnection on the second metal interconnection surface is fully located at institute
In the top surface for stating the second metal interconnection；At least barrier layer is formed in the top surface of the second metal interconnection.
10. the forming method of bonding structure according to claim 1, which is characterized in that further include: by described two bases
Before the opposite bonding in the surface at bottom, planarization process is carried out to the substrate surface for being formed with barrier layer.
11. a kind of bonding structure characterized by comprising
Two substrates, each substrate include the metal interconnection of dielectric layer and the exposed top surface being formed in the dielectric layer
Portion；
The surface of described two substrates is opposite to be bonded connection；
Two substrates are formed with barrier layer with respect to the metal interconnection surface at bonding position, and when relative position in two substrates
When place is provided with metal interconnection, the top surface of the metal interconnection of larger size is formed with barrier layer at least in,
The barrier layer is conductive material and the diffusion for capableing of barrier metal atoms, and the barrier layer is located at the opposite metal of two substrates
Between interconnection or between metal interconnection and opposite dielectric layer.
12. bonding structure according to claim 11, which is characterized in that surface is formed with the metal interconnection on barrier layer
Surface of the top surface lower than the dielectric layer at place.
13. bonding structure according to claim 11, which is characterized in that the metal interconnection top surface of two substrates is equal
It is formed with barrier layer.
14. bonding structure according to claim 11, which is characterized in that the barrier layer with a thickness of 5nm~20nm.
15. bonding structure according to claim 11, which is characterized in that the material on the barrier layer include Co, Ti, Ta,
At least one of TiN and TaN.
16. bonding structure according to claim 11, which is characterized in that described two substrates are respectively the first substrate and
Two substrates are formed with the first metal interconnection in first substrate, the second metal interconnection are formed in second substrate,
Projection of the top surface of the first metal interconnection on the second metal interconnection surface is fully located at second gold medal
In the top surface for belonging to interconnection；At least the barrier layer is formed in the top surface of the second metal interconnection.
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| WO2023272941A1 (en) * | 2021-07-01 | 2023-01-05 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
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