CN109752992B

CN109752992B - FPGA +8051 system controller

Info

Publication number: CN109752992B
Application number: CN201811487495.XA
Authority: CN
Inventors: 秦术; 张永龙; 冯基伟
Original assignee: Guizhou Aerospace Electronic Technology Co Ltd
Current assignee: Guizhou Aerospace Electronic Technology Co Ltd
Priority date: 2018-12-06
Filing date: 2018-12-06
Publication date: 2022-01-21
Anticipated expiration: 2038-12-06
Also published as: CN109752992A

Abstract

The invention provides an FPGA +8051 system controller; the system comprises a power supply module, an FPGA system module, an AD conversion module, an input isolation conversion module, an output isolation driving module, an 8051 singlechip system and a network communication interface module; the purpose of replacing PLC by adopting an FPGA +8051 control module is as follows: a mature FPGA +8051 architecture mode is used for realizing logic control and network communication control; by improving the quality grade of the components, rechecking and recalculating the circuit design and carrying out derating design, the I-grade derating of the components is ensured, and the working reliability of the controller is improved; the internal circuit can be clearly known, so that the product can be quickly positioned and eliminated after the product has a fault; the power supply mode and the mechanical interface of the product are consistent with those of the PLC, and the FPGA +8051 control module can be used for completely replacing the PLC after the PLC is stopped production or updated and upgraded.

Description

FPGA +8051 system controller

Technical Field

The invention relates to an FPGA +8051 system controller.

Background

The use of PLC in the military industry presents a number of drawbacks, in particular as follows:

(1) the PLC belongs to an imported industrial device, and due to the defects of component quality grade and mechanical design in the process of military grade assessment, the PLC controller needs to be reinforced when in use, and the printed board is sprayed with three proofings and is encapsulated by related devices. In the processing process, circuits and components can be damaged, so that the PLC needs to be screened and used after reinforcement. The processing flow is relatively complicated and is easy to break down.

(2) Network communication interface uses RJ45 to connect among the PLC, and contact failure phenomenon probably appears at the in-process of vibration, adopts for military use level connector to connect when designing the FPGA controller, guarantees that the product is reliable.

(3) The PLC device belongs to a universal device, and in the using process, the functions really used are few, and controller resources are wasted. The FPGA controller is designed in a targeted manner, so that resource waste is avoided.

(4) The bottom layer software of the PLC controller is developed for Siemens, a specific source code is mastered by Siemens, logic programming is carried out on the source code in the using process, whether a back door is left is unclear, and potential safety hazards exist.

(5) The PLC has a long purchasing period and the condition of version upgrading and updating exists, so that the maintenance and the guarantee of military products are not facilitated. In addition, because the internal circuit principle of the PLC and the distribution of the printed boards are not clear, when the PLC fails, the fault is not easy to troubleshoot and process, and only the whole processing mode of replacing the PLC can be adopted.

Disclosure of Invention

In order to solve the technical problem, the invention provides an FPGA +8051 system controller.

The invention is realized by the following technical scheme.

The invention provides an FPGA +8051 system controller; the system comprises a power supply module, an FPGA system module, an AD conversion module, an input isolation conversion module, an output isolation driving module, an 8051 singlechip system and a network communication interface module;

the power supply module converts an externally input direct current power supply into a power supply signal of the FPGA system module;

the FPGA system module generates clock signals of each module in the FPGA after the clock signals are subjected to frequency division or frequency multiplication processing by the FPGA internal system module, the FPGA outputs control signals for controlling the AD module, the AD data is input into the FPGA for processing, and corresponding current signals are output by controlling the DA module;

the input isolation conversion module and the output isolation driving module convert the I/O signals into low-speed I/O digital signals and high-speed digital pulse signals;

the 8051 single chip microcomputer system realizes Ethernet communication by controlling the network communication interface module and receives signals of an upper computer.

The power module comprises a primary power conversion module and a secondary power conversion module, wherein the primary power conversion module converts a 24V direct-current voltage ring input from the outside into a 5V direct-current power output, and the secondary power conversion module converts 5V voltage signals into 3.3V and 1.2V voltages respectively.

The FPGA system module comprises an FPGA control chip, the FPGA control chip is connected with a JTAG interface and the FLASH storage module, and the JTAG interface is arranged outside the FPGA control chip.

The 8051 single chip microcomputer is communicated with the FPGA chip through an RS232 serial port, and an FIFO memory space is arranged in the 8051 single chip microcomputer to store instructions or data.

The FPGA control chip and the 8051 singlechip Ethernet communication module are distributed on a circuit board, and the interfaces of the FPGA control chip and the 8051 singlechip Ethernet communication module are consistent with the PLC interface through the interfaces JXS0, JXS1 and JXS2 outside the circuit board.

The communication flow of the network communication interface is that after the power module is powered on, the MCU is initialized, then the Ethernet control chip CP2200 is configured, after the configuration is finished, the interruption is started, then the interruption signal is waited for, and the corresponding interruption is responded.

And a soft core CPU is embedded in the FPGA chip.

The invention has the beneficial effects that: the electrical interface and the structure of the original PLC are not changed, and the PLC control module is completely compatible. The circuit adopts the modularized design, has improved the degree of automation and the integrated level of equipment. The method has the advantages of high acquisition precision, high communication efficiency, fault display and the like. The FPGA +8051 control module adopts methods of redundancy protection, component derating and the like, has high reliability, and can reach 735h of continuous working time. The environment adaptability has obvious advantages, and the performances of vibration resistance, impact resistance, extreme temperature resistance, salt spray mold resistance and the like can meet the requirements of the use environment.

The FPGA +8051 controller is compatible with the Siemens PLC in the aspects of installation mode, power supply mode, digital signal range, analog signal range, communication protocol and the like, and the dependence of a domestic system on the Siemens PLC can be effectively reduced by the production of the domestic PLC.

Drawings

FIG. 1 is a software architecture diagram of the present invention;

FIG. 2 is a schematic diagram of the control circuit of the present invention;

FIG. 3 is a schematic diagram of the internal interface of the control software of the present invention;

FIG. 4 is a schematic diagram of a network communication process according to the present invention;

fig. 5 is a schematic diagram of a circuit board connection structure of the control module according to the present invention.

Detailed Description

The technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.

An FPGA +8051 system controller; the system comprises a power supply module, an FPGA system module, an AD conversion module, an input isolation conversion module, an output isolation driving module, an 8051 singlechip system and a network communication interface module;

And a soft core CPU is embedded in the FPGA chip.

The FPGA +8051 control module comprises all system resources of the PLC: 14-path 24V digital input (comprising 3 100K and 3 30K high-speed counting input ports), 2-path 0-10V analog input, 10-path 24V digital output and an Ethernet communication interface. The CPU of the PLC combines the microprocessor, the integrated power supply, the input and output circuit, the built-in PROFINET, the high-speed motion control I/O and the onboard analog quantity input into a shell with compact design to form a controller, so that the functions of the FPGA and the single chip microcomputer control module are completely consistent with the functions realized by the PLC.

In the invention, the FPGA +8051 control module comprises a power supply module, an FPGA system module, an AD conversion module, an input isolation conversion module, an output drive module, a C8051F340 singlechip system, a network communication interface module and the like. The internal circuit module is shown in fig. 2. The working principle of the control module is as follows:

an externally input 24V direct current power supply is converted by the power supply module and then outputs a 5V direct current power supply, and the secondary power supply processing chip converts 5V voltage signals into 3.3V voltage and 1.2V voltage respectively and serves as power supply signals of the FPGA chip of the module. After the module is powered on, an external clock module inputs a 40MHz clock signal into the FPGA, and the clock signal is subjected to frequency division or frequency multiplication processing by a digital clock management module inside the FPGA to generate clock signals of all modules in the FPGA. The FPGA outputs a control signal for controlling the AD module, acquires data after AD processing, inputs the AD data into the FPGA for processing, and outputs a corresponding current signal by controlling the DA module, and the AD and DA modules meet the requirements of digital-to-analog control and analog-to-digital conversion control and are suitable for the requirements of different products on AD and DA signal processing. The FPGA can meet the requirements of low-speed I/O digital signal processing and high-speed digital pulse signal processing after the I/O signals are processed by the input isolation conversion module and the output isolation conversion module. The JTAG interface of the FPGA is designed outside the module, and the software upgrading task can be completed without opening the cover. The FPGA controls the FLASH module to write and read data, and the functions of the module meet the functions of caching data, storing key test instructions, solidifying system programs and the like. The FPGA and the 8051 single chip microcomputer are communicated through RS232 serial ports, the function of data interaction between the single chip microcomputer and the FPGA is met, the single chip microcomputer achieves Ethernet communication through a control network protocol chip CP2000, after receiving instructions of an upper computer (or network equipment with an Ethernet communication protocol), the single chip microcomputer conducts data analysis, and then sends the data or the instructions to the FPGA through the serial ports, and control over modules of a product is achieved.

The FPGA is used as a main control chip of the control module, the 8051 singlechip is used as an auxiliary chip of the control module, the FPGA realizes control of functional modules of different products through programming, corresponding functional modules can be compiled according to the characteristics of different products, the FPGA internal programming module can adopt an architecture mode of embedding a soft core CPU to realize FLASH read-write control, AD acquisition data processing, RS232 serial port communication control, data communication between the bottom FPGA and the soft core CPU and other technologies, a digital clock manager module (DCM module) with perfect internal integration of the FPGA, IP soft core modules with different functions and self-defined functional modules meet software compiling requirements of different products. The single chip microcomputer is used as an auxiliary chip to realize data forwarding and processing work, after receiving instructions or data of an upper computer, an FIFO memory space is opened up in the single chip microcomputer to store the instructions or the data, after analysis and processing, the single chip microcomputer interacts the data and the instructions with the FPGA through a serial port, and the control of each module of a product using the control module is realized through the corresponding instructions. An FIFO memory mode is developed in the single chip microcomputer, the processing scheme that the high communication rate of the Ethernet is not matched with the low communication rate of the serial port is met, and the communication coordination and the data consistency are met.

The circuit system is divided into two circuit boards, the power supply conversion module and the input/output isolation circuit module are distributed on one printed board, and the FPGA control system and the 8051 singlechip Ethernet communication module are distributed on one circuit board. The connection relationship between the external input interface signals and the signals between the boards is shown in fig. 3. The external interfaces JXS0, JXS1, JXS2 are consistent with the original PLC interfaces. The high level signal and the low level signal are physically separated. The structural schematic diagram of the PLC module is shown in FIG. 4, so that the PLC module can completely replace the original PLC module. The module is compact in internal layout, the structural layout is divided into a control circuit board and an interface circuit board according to different functional modules, wherein the control circuit board completes communication data processing, AD and DA processing and the like, and the interface circuit board completes functions of signal switching, signal isolation and the like. The modules are arranged in a miniaturized, modular structure.

In the control module, the key network communication flow chart is shown in fig. 4. After power-on, the MCU is initialized, then the Ethernet control chip CP2200 is configured, after configuration is completed, interruption is started, then an interruption signal is waited, and corresponding interruption is responded.

1. On the basis of not changing the communication structure, the communication method is compatible with the MODbus communication protocol, can carry out communication after data message encapsulation according to general TCP/IP and UDP protocols, has a flexible communication mode, meets the requirements of industrial Ethernet and general Ethernet data message encapsulation, and can carry out communication with 5 computers simultaneously.

2. And the flexible architecture of FPGA logic signal processing and embedded soft core CPU rapid data processing is adopted, so that the rapid communication requirement of the control system is met. The system has abundant clock resources and high-speed optical couplers, realizes high-speed digital signal processing, and has the high-speed optical coupler rate of 10MHz which is far greater than the processing capacity of 100KHz of a PLC control unit.

3. An embedded soft core CPU (MicroBlaze) technology is adopted. The FPGA bottom layer logic signal processing and the data processing module of the embedded soft core CPU are adopted, after AD digital-analog conversion is realized, the acquired signals are quickly processed, data are transmitted into the embedded CPU through the bottom layer logic unit module, the requirements of data correction, data high-low order separation, data size end processing and the like are realized in the embedded CPU, the processed data are transmitted into the 8051 module through the RS232 module controlled by the embedded CPU through the RS232 serial port communication bus, and the 8051 module corrects the data. The operation of writing instructions and reading instructions of the memory can be realized according to the instructions and data of the received signals and the read-write time sequence requirements of the memory device, and the received instructions and data are stored in Flash. The software architecture diagram of the home-made PLC is shown in fig. 2.

4. The software processing inside the FPGA +8051 control module is divided into 7 modules, namely a clock management module, an A/D sampling module, a storage operation module, a signal processing module and a control signal processing module (an input control signal processing module and an output control signal processing module). And the total number of the 9 internal interfaces is respectively a clock-to-signal processing interface, a clock-to-A/D interface, a clock-to-control signal processing interface, a clock-to-storage operation interface, a signal processing-to-A/D interface, a signal processing-to-control signal processing module interface, a signal processing-to-storage operation interface, a storage operation-to-signal processing interface and an A/D-to-signal processing interface. The schematic diagram of the internal interface of the control software is shown in figure 3.

5. Mature programming language and flexible data processing technology, mature Verilog and C language are used for realizing bottom layer logic control and data processing, communication control requirements, and a user can write corresponding processing functions according to the complexity of required data, and can realize data processing such as arithmetic operation, Fourier transform, triangular transform and the like. The siemens PLC processes data using a data processing module (ladder processing module) provided inside, and cannot satisfy diverse data processing requirements of users.

6. An FPGA +8051 dual-core architecture mode is adopted, 8051 is specially responsible for network communication, the FPGA is responsible for logic control, the defect of insufficient single-core operation resources is overcome, and the FPGA realizes operation and control of signal acquisition and processing, system peripheral module control, peripheral input signal processing, Flash data storage and processing and the like through bottom layer logic signal control and an embedded soft core CPU. The 8051 module is responsible for outputting corresponding control signals to the Cp2000 control module, so as to realize Ethernet communication and control. And 8051 realizes data interaction with the console through control of the ethernet communication module. By means of a dual-core architecture mode of FPGA +8051, the load capacity of a control chip during full load in the system operation process can be effectively reduced.

Claims

1. An FPGA +8051 system controller, characterized by: the system comprises a power supply module, an FPGA system module, an AD conversion module, an input isolation conversion module, an output isolation driving module, an 8051 singlechip system and a network communication interface module;

the FPGA system module generates clock signals of each module in the FPGA after the clock signals are subjected to frequency division or frequency multiplication processing by the FPGA internal system module, the FPGA outputs control signals for controlling the AD module, the control signals of the AD module are input into the FPGA for processing, and corresponding current signals are output by controlling the DA module;

the 8051 single chip microcomputer system realizes Ethernet communication by controlling the network communication interface module and receives signals of an upper computer;

the power supply module comprises a primary power supply conversion module and a secondary power supply conversion module, wherein the primary power supply conversion module converts an externally input 24V direct current voltage loop into a 5V direct current power supply for output, and the secondary power supply conversion module converts a 5V voltage signal into 3.3V voltage and 1.2V voltage respectively;

2. The FPGA +8051 system controller of claim 1, wherein: the 8051 single chip microcomputer is communicated with the FPGA chip through an RS232 serial port, and an FIFO memory space is arranged in the 8051 single chip microcomputer to store instructions or data.

3. The FPGA +8051 system controller of claim 1, wherein: the FPGA control chip and the 8051 singlechip Ethernet communication module are distributed on a circuit board, and the interfaces of the FPGA control chip and the 8051 singlechip Ethernet communication module are consistent with the PLC interface through the interfaces JXS0, JXS1 and JXS2 outside the circuit board.

4. The FPGA +8051 system controller of claim 1, wherein: the communication flow of the network communication interface is that after the power module is powered on, the MCU is initialized, then the Ethernet control chip CP2200 is configured, after the configuration is finished, the interruption is started, then the interruption signal is waited for, and the corresponding interruption is responded.

5. The FPGA +8051 system controller of claim 1, wherein: and a soft core CPU is embedded in the FPGA chip.