CN109358547B - Data acquisition method of implanted control system - Google Patents
Data acquisition method of implanted control system Download PDFInfo
- Publication number
- CN109358547B CN109358547B CN201811271904.2A CN201811271904A CN109358547B CN 109358547 B CN109358547 B CN 109358547B CN 201811271904 A CN201811271904 A CN 201811271904A CN 109358547 B CN109358547 B CN 109358547B
- Authority
- CN
- China
- Prior art keywords
- unit
- interface
- bus
- data
- stm32 singlechip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Small-Scale Networks (AREA)
- Communication Control (AREA)
Abstract
The invention belongs to the technical field of automatic measurement, and discloses an implanted control system data acquisition method, which aims to solve the problems in the high-speed acquisition of control system data in the prior art. The signal acquisition of high-speed change in the control system is accurate, the process data is effectively acquired, the accuracy of the acquired data is high, and the installation and the debugging are convenient and reliable.
Description
Technical Field
The invention relates to the technical field of automatic measurement, in particular to a data acquisition method of an implanted control system.
Background
The collection and storage of process data in the operation of a control system is very important, and the operation conditions of the control system and related peripheral equipment can be observed through the data, so that the method is also an important means for daily management of equipment and equipment fault analysis. In general, the data acquisition of the control system is recorded and stored through the trend function of the human-computer interface program. Because the core task of the control system is to ensure that the control program is accurately and effectively executed, the software and hardware resources for communication between the control system and the external equipment are limited, the data acquisition capacity of the human-computer interface program is limited, the data access time interval of the external equipment to the control system is limited, the data access time interval is generally required to be larger than 0.1s, the data refreshing time interval of the human-computer interface program HMI in a general industrial control system is generally set to be between 0.1s and 1s, and the refreshing time interval is generally set to be 1s, so that the observation and control requirements of operators on the equipment can be met.
According to the sampling theorem, when the sampling frequency fs.max is greater than 2 times of the highest frequency fmax in the signal (fs.max is greater than 2 fmax), the sampled digital signal completely retains the information in the original signal, and the sampling frequency is ensured to be 2.56-4 times of the highest frequency of the signal in general practical application, namely: fs.max > (2.56-4) fmax. For example, a signal with the frequency of 10Hz is effectively collected, the collection frequency should reach 25.6-40Hz, the time interval for acquiring data should be between 39ms and 25ms, the details of the signal with the too large interval are lost, the too small interval can cause the waste of software and hardware resources, in practice, the sampling time interval should be smaller in order to effectively capture some random signals by reasonably selecting according to specific requirements.
Under the normal condition, the data acquisition interval of 0.1s-1s can meet the requirements in a plurality of control operation tasks with low movement speed, and the historical trend of the process data obtained under the condition can objectively reflect the change of the working process state of the equipment. However, the process data acquired by the high-speed variable signals at the acquisition interval cannot meet the requirements, and the high-speed acquisition of the control system data at home and abroad is generally realized by adopting matched special hardware, so that the method is high in price and poor in universality, and is generally applied to large-scale control systems such as rolling mills. There are also pure software implementations, but they are generally applied to control systems with low accuracy requirements, and the control systems with high accuracy requirements cannot meet the requirements, so that the above technical problems cannot be solved in the prior art.
Disclosure of Invention
The invention aims to solve the problems in the high-speed acquisition of the control system data in the prior art, and provides an implanted control system data acquisition device which can acquire the process data of a control system at high speed and is convenient and reliable to install and debug.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
an implantable control system data acquisition device comprises a field bus unit, an FPGA unit, an STM32 singlechip system, a memory unit and a network interface unit;
the field bus unit comprises a bus driving circuit which is connected in a bidirectional manner and a bus protocol controller, and the bus driving circuit is connected with a field bus;
the bus protocol controller is connected with the FPGA unit in a bidirectional way, the FPGA unit comprises a protocol chip control logic interface, a capacity memory logic interface, a kernel management function unit and an internal resource coordination function unit, the protocol chip control logic interface is connected with the bus protocol controller and the internal resource coordination function unit in a bidirectional way, the protocol chip control logic interface is connected with the capacity memory logic interface in a unidirectional way, the capacity memory logic interface is connected with the internal resource coordination function unit in a bidirectional way, the internal resource coordination function unit is connected with the kernel management function unit in a unidirectional way,
the capacity memory logic interface is connected with the memory unit in a bidirectional way, the internal resource coordination function unit is connected with the STM32 singlechip system in a bidirectional way, and the STM32 singlechip system is connected with the network interface unit.
Further, the memory unit comprises an SDRAM memory and an expandable TF card memory, and the SDRAM memory, the expandable TF card memory and the capacity memory logic interface are connected in a bidirectional manner.
Further, the network interface unit comprises an Ethernet interface unit and an RS232 interface unit, the Ethernet interface unit is connected with an output physical interface of the Ethernet interface circuit, the RS232 interface unit is connected with an output physical interface of the RS232 interface circuit, and the Ethernet interface unit and the RS232 interface unit are connected with the STM32 singlechip system.
Further, an operation indicator lamp and a system state double-color indicator lamp are connected to the STM32 single-chip microcomputer system.
Another object of the present invention is to provide a method for acquiring data of an implantable control system, which adopts the following technical scheme:
an implantable control system data acquisition method comprises the following steps:
1) After the power-on is started, the FPGA unit and the STM32 singlechip system start to be initialized at the same time, and the FPGA unit initializes a protocol chip control logic interface, a capacity memory logic interface, a kernel management function unit and an internal resource coordination function unit and performs self-checking;
2) Initializing a bus protocol controller, then performing self-checking on the bus protocol controller, the SDRAM memory and the expandable TF card memory, and starting to receive and process instructions of the STM32 singlechip system after the self-checking is normal;
the method comprises the steps that field bus data are converted into TTL signals which can be identified by a bus protocol controller through a bus driving circuit from RS485 signals on the field bus, then the bus protocol controller converts bus coding signals on the bus driving circuit into digital signals in binary format which can be identified by an internal protocol chip control logic interface, the internal protocol chip control logic interface transmits the signals to a capacity memory logic interface, and the capacity memory logic interface compresses the data signals according to a set acquisition rate and adds a time stamp to store the compressed data signals in an expandable TF card memory;
3) After initializing the STM32 singlechip system, carrying out self-checking on the RS232 interface unit and the Ethernet interface unit, transmitting self-checking data of the FPGA unit to the STM32 singlechip system, and after the self-checking is normal, starting to receive and process instruction data from the RS232 interface unit and the Ethernet interface unit by the STM32 singlechip system;
4) When data is required to be inquired, an instruction is sent to an internal resource coordination functional unit through an STM32 singlechip system, then the data in the expandable TF card memory is inquired through a capacity memory logic interface, and an inquiry result is output through an RS232 interface unit or an Ethernet interface unit;
5) When the external equipment needs to read real-time data on the field bus unit, the STM32 singlechip system sends an instruction to the internal resource coordination function unit, the internal resource coordination function unit sends an instruction to the bus protocol controller through the protocol chip control logic interface, the bus driving circuit reads the real-time data from the field bus, and the read data is transmitted by the STM32 singlechip system through the RS232 interface unit or the Ethernet interface unit.
Further, in step 2), if the self-checking of the bus protocol controller, the SDRAM memory or the expandable TF card memory is abnormal, the status code is sent to the STM32 singlechip system for processing through the kernel management function unit, and is displayed through the system status bi-color indicator lamp.
Further, in step 3), if the self-checking of the RS232 interface unit and the ethernet interface unit is abnormal, the status code is sent to the STM32 singlechip system for processing through the kernel management function unit, and is displayed through the system status bicolor indicator.
Compared with the prior art, the invention has the following beneficial effects:
the invention can be mapped into a data space of the control system, which is only visible to the data area. All the operations on the data are realized through the corresponding logic interfaces of the FPGA, and the control logic circuit is formed by the protocol chip control logic interface, the capacity memory logic interface, the kernel management function unit and the internal resource coordination function unit through programming the FPGA. And the functions of all the areas of the logic units are independent and independent logically. Because the control system refreshes the data area formed by the field bus unit mapping in each scanning period, the device has a hardware foundation for rapidly reading the data area and is matched with a corresponding software system to form a high-speed data acquisition device implanted into the control system. The invention can be conveniently applied to other types of field bus networks by replacing the field bus units. The invention is accurate to the signal collection of the high-speed change in the control system, effectively collects the process data of the control system, has higher data collection precision and is convenient and reliable to install and debug. The Ethernet interface unit of the invention provides an Ethernet communication physical interface to the outside, can carry out data communication with other external devices with Ethernet interfaces conforming to a communication protocol, and the RS232 interface unit provides a standard RS232 communication physical interface to the outside, and can carry out data communication with other external devices with RS232 interfaces conforming to the communication protocol.
Drawings
FIG. 1 is a schematic diagram of the connection of the present invention.
Fig. 2 is a schematic view of the internal arrangement of the present invention.
Fig. 3 is a flow chart of the data operation processing of the present invention.
The reference numerals have the following meanings: 1. a bus driving circuit; 2. a bus protocol controller; an FPGA unit; SDRAM memory; 5. an expandable TF card memory; STM32 singlechip system; 7. an Ethernet interface unit; an rs232 interface unit; 9. a field bus unit; 10. a protocol chip control logic interface; 11. a capacity memory logical interface; 12. a kernel management function unit; 13. an internal resource coordination function unit; an output physical interface of the rs232 interface circuit; 15. an output physical interface of the ethernet interface circuit; 16. a field bus; 17. operating an indicator light; 18. system status bi-color indicator lights.
Detailed Description
The invention is further described below with reference to the drawings and the detailed description.
As shown in fig. 1-2, an implantable control system data acquisition device includes a field bus unit 9, an FPGA unit 3, an STM32 singlechip system 6, a memory unit 19, and a network interface unit 20; the field bus unit 9 comprises a bus driving circuit 1 and a bus protocol controller 2 which are connected in a bidirectional manner, the bus driving circuit 1 is connected with the field bus 16, the field bus 16 is connected with a control system, the bus driving circuit 1 converts an RS485 signal from the field bus 16 into a TTL signal which can be identified by the bus protocol controller 2, and otherwise, the TTL signal sent by the bus protocol controller 2 can be converted into the RS485 signal to be sent to the field bus 16. The bus protocol controller 2 is composed of an intelligent chip comprising a field bus protocol stack, the bus protocol controller 2 is connected with the FPGA unit 3 in a two-way, and can convert the datagram or command report in a common binary format sent by the protocol chip control logic interface 10 inside the FPGA unit 3 into a field bus coding signal, and then the field bus coding signal is sent to the field bus 16 through the bus protocol controller 2 and the bus driving circuit 1, otherwise, the bus protocol controller 2 can also convert the bus coding signal from the bus driving circuit 1 into a digital signal in a binary format which can be identified by the protocol chip control logic interface 10 inside the FPGA unit 3. The bus driving circuit 1, the bus protocol controller 2 and the auxiliary electronic components thereof together form a field bus unit 9 which is designed and arranged on the same printed circuit board.
The FPGA unit 3 is a field programmable gate array, and the internal functional units are all realized by hardware description language Verilog HDL programming. The FPGA unit 3 comprises a protocol chip control logic interface 10, a capacity memory logic interface 11, a kernel management function unit 12 and an internal resource coordination function unit 13, wherein the protocol chip control logic interface 10 is in bidirectional connection with the internal resource coordination function unit 13, the protocol chip control logic interface 10 is in unidirectional connection with the capacity memory logic interface 11, the capacity memory logic interface 11 is in bidirectional connection with the internal resource coordination function unit 13, the internal resource coordination function unit 13 is in unidirectional connection with the kernel management function unit 12, the capacity memory logic interface 11 is in bidirectional connection with the SDRAM memory 4 and the expandable TF card memory 5, the internal resource coordination function unit 13 is in bidirectional connection with the STM32 singlechip system 6, and the STM32 singlechip system 6 is connected with the network interface unit 20. The network interface unit 20 comprises an Ethernet interface unit 7 and an RS232 interface unit 8, the Ethernet interface unit 7 is connected with an output physical interface 15 of an Ethernet interface circuit, the RS232 interface unit 8 is connected with an output physical interface 14 of an RS232 interface circuit, and the Ethernet interface unit 7 and the RS232 interface unit 8 are connected with the STM32 singlechip system 6. The STM32 singlechip system 6 is connected with an operation indicator lamp 17 and a system state bicolor indicator lamp 18. The kernel management function unit 12 is responsible for setting the bus node address of the data acquisition device, detecting the bus address state and sending the bus state code to the STM32 singlechip system 6 for processing.
The protocol chip control logic interface 10 is responsible for communication with the fieldbus unit 9, and receives and forwards signals sent by the fieldbus unit 9 to the capacity memory logic interface 11 and the internal resource coordination function unit 13, respectively. The capacity memory logic interface 11 is responsible for temporarily storing the received signals in the SDRAM memory 4 after time stamping, and can also store the data in the expandable TF card memory 5 for long-term storage according to requirements. The data compression, data organization management and data access functions of the storage system are all implemented by the capacity memory logic interface 11. The internal resource coordination function unit 13 is responsible for processing commands and data between the STM32 singlechip system 6, when external equipment needs to read the data of the field bus unit 9 or the data in the expandable TF card memory 5, the STM32 singlechip system 6 sends instructions to the internal resource coordination function unit 13, then the internal resource coordination function unit 13 reads real-time data from the field bus 16 through the field bus unit 9 by the protocol chip control logic interface 10 or reads data from the expandable TF card memory 5 by the capacity memory logic interface 11, and the read data is sent by the STM32 singlechip system 6 through the RS232 interface unit 8 by the output physical interface 14 of the RS232 interface circuit or through the Ethernet interface unit 7 by the output physical interface 15 of the Ethernet interface circuit. The data acquisition device normally accesses the fieldbus 16 and operates the indicator light 17 green normally on when properly configured to the control system, otherwise the operating indicator light 17 green flashes. When no error is detected in the working process of the data acquisition device, the system state bicolor indicator 18 is not on, otherwise, corresponding indication is made according to the fault code, and the system state bicolor indicator 18 comprises a red indicator and an orange indicator. The red indicator light is normally on to indicate that the system has unrecoverable serious hardware faults, the red indicator light flashes to indicate that the bus address of the device collides with other device addresses on the field bus, the orange indicator light flashes to indicate that at least one sampling data loss occurs within a one-second time interval, the sampling data loss indicator light is not turned off again within ten seconds, and otherwise, the orange indicator light flashes to be turned into the orange indicator light to be normally on. When the faults occur simultaneously, only one state can be displayed according to the priority from high to low, and the priorities from high to low are respectively as follows: the red indicator lights are normally on, the red indicator lights are flashing, the orange indicator lights are normally on and the orange indicator lights are flashing.
The bus protocol controller 2 selects a special DP protocol management chip SPC3 of the Germany SIEMENS company, integrates a complete DP protocol, can independently complete the encoding and decoding of bus commands and bus control work, can effectively reduce the operation load of a processor, and can reach 12Mbaud based on the DP bus interface baud rate formed by the SPC 3.
The bus driving circuit 1 selects the bus driving chip ADM2486 of ADI company in the United states, the chip adopts a magnetic isolation technology, the power consumption is low, the transmission rate is high, and the SPC3 transmits and receives data messages on the bus at high speed through the bus driving circuit.
The FPGA unit 3 selects an industrial large-scale integrated circuit EP4CE10F17C8N produced by ALTERA company in the United states, and utilizes rich logic resource programming to realize a bus protocol chip control logic interface 10, a capacity memory logic interface 11, a kernel management function unit 12 and an internal resource coordination function unit 13, and the FPGA unit 3 can customize control logic individually to realize a personalized high-speed logic algorithm and control function.
The SDRAM memory 4 is made of korean Hynix product, the model number is H57V1262GTR, and is matched with a logic interface of the FPGA unit 3 for fast caching of bus process data, so that bottlenecks on a data transmission channel of the device can be effectively eliminated, and the high speed and reliability of the device can be improved.
The extensible TF card memory 5 can be inserted into a 4M to 64M capacity CLASS4 speed level TF card according to the requirement and is used for storing process data which needs to be stored for a long time, the data organization adopts a queue form, new data can continue to enter the queue after the data storage area is full of data, and the earliest stored data is automatically lost. In the running process, the bus process data is packaged and stored in the expandable TF card memory 5 after being time stamped.
The STM32 singlechip system 6 mainly realizes internal state management of the device and data communication function realization of the serial port and the Ethernet interface, the data acquisition working state is displayed by the running indicator lamp 17, and the data acquisition command sent by a data demander is processed by the STM32 singlechip system 6 according to a program. The request of the data required to be acquired by the external equipment is analyzed by the STM32 singlechip system 6, is taken out through the internal resource coordination function unit 13 and the capacity memory logic interface 11 of the FPGA unit 3, and is output through the RS232 interface unit 8 or the Ethernet interface unit 7. The ethernet interface unit 7 is selected from the integrated embedded networking device USR-K2. The RS232 interface unit 8 is composed of a MAX232 interface chip.
In use, the Fieldbus 16 is plugged into the Fieldbus system of the control system, and the control system then configures the data acquisition device, which is mapped into a bus site data field of the control system. The working mode of the data acquisition device can be set through an upper computer and is divided into an offline mode and an online mode, in the offline mode, field bus data are converted into TTL signals which can be identified by a bus protocol controller 2 through a bus driving circuit 1 from RS485 signals on a field bus 16, the bus protocol controller 2 converts bus coding signals from the bus driving circuit 1 into digital signals in a binary format which can be identified by an internal protocol chip control logic interface 10 of an FPGA chip 3, the internal protocol chip control logic interface 10 transmits the signals to a capacity memory logic interface 11, and the capacity memory logic interface 11 compresses the data signals according to a set acquisition rate and stores the compressed data signals in an expandable TF card memory 5 after adding a time stamp. When data is required to be inquired, an instruction can be sent to the internal resource coordination function unit 13 through the STM32 singlechip system 6, then the data of the expandable TF card memory 5 is inquired through the capacity memory logic interface 11, and the inquired result is output through the RS232 interface unit 8 or the Ethernet interface unit 7.
In the online mode, the external data demand equipment sends a request to the STM32 singlechip system 6 through the RS232 interface unit 8 or the Ethernet interface unit 7, and then the STM32 singlechip system 6 acquires the process data of the control system through the internal resource coordination function unit 13, the protocol chip control logic interface 10, the field bus unit 9 and the field bus interface 16.
Fig. 3 is a flow chart of data operation processing in the present invention, and after power-on, the chip (each functional unit) of the FPGA3 unit 3 and the STM32 singlechip system 6 start to be initialized at the same time. The FPGA unit 3 initializes the protocol chip control logic interface 10, the capacity memory logic interface 11, the kernel management function unit 12 and the internal resource coordination function unit 13, initializes the bus protocol controller 2, then performs self-checking on SDRAM memory and the like 4, and if the self-checking is normal, starts to receive and process instructions of the STM32 singlechip system 6, then performs field bus unit signal processing, and normally performs bus data compression, storage and transmission; the STM32 singlechip system 6 is also initialized immediately after being electrified, then self-checking of the RS232 interface unit 8, the Ethernet interface unit 7 and the like is carried out, after the self-checking is normal, instructions or data from the RS232 interface unit 8 or the Ethernet interface unit 7 are processed, and after analysis, the instructions or data enter corresponding functional subroutines and are executed repeatedly. If the self-test is abnormal, the kernel management function unit 12 sends the status code to the STM32 singlechip system 6 for processing, and displays the status code through the system status bicolor indicator 18. The specific method comprises the following steps:
1) After the power-on is started, the FPGA unit 3 and the STM32 singlechip system 6 start to be initialized at the same time, and the FPGA unit 3 initializes the protocol chip control logic interface 10, the capacity memory logic interface 11, the kernel management function unit 12 and the internal resource coordination function unit 13 and performs self-checking.
2) And initializing a bus protocol controller 2, then performing self-checking on the bus protocol controller 2, the SDRAM memory 4 and the expandable TF card memory 5, and starting to receive and process instructions of the STM32 singlechip system 6 after the self-checking is normal.
The field bus data is converted into a TTL signal which can be identified by the bus protocol controller 2 through the bus driving circuit 1 from an RS485 signal on the field bus 16, then the bus protocol controller 2 converts the bus coding signal from the bus driving circuit 1 into a digital signal in a binary format which can be identified by the internal protocol chip control logic interface 10, the internal protocol chip control logic interface 10 transmits the signal to the capacity memory logic interface 11, and the capacity memory logic interface 11 compresses the data signal according to a set acquisition rate and adds a time stamp and stores the compressed data signal into the expandable TF card memory 5.
3) In the step 1), after the initialization of the STM32 singlechip system 6, the self-checking of the RS232 interface unit 8 and the Ethernet interface unit 7 is carried out, meanwhile, the self-checking data of the FPGA unit 3 is transmitted to the STM32 singlechip system 6, and after the self-checking is normal, the STM32 singlechip system 6 starts to receive and process the instruction data from the RS232 interface unit 8 and the Ethernet interface unit 7.
4) When data is required to be inquired, an instruction is sent to the internal resource coordination function unit 13 through the STM32 singlechip system 6, then the data in the expandable TF card memory 5 is inquired through the capacity memory logic interface 11, and the inquired result is output through the RS232 interface unit 8 or the Ethernet interface unit 7.
5) When the external equipment needs to read real-time data on the field bus unit 9, the STM32 singlechip system 6 sends an instruction to the internal resource coordination function unit 13, then the internal resource coordination function unit 13 sends an instruction to the bus protocol controller 2 through the protocol chip control logic interface 10, the bus driving circuit 1 reads the real-time data from the field bus 16, and the read data is transmitted by the STM32 singlechip system 6 through the RS232 interface unit 8 or the Ethernet interface unit 7. If the self-checking of the bus protocol controller 2, the SDRAM memory 4 or the expandable TF card memory 5 is abnormal, the status code is sent to the STM32 singlechip system 6 for processing through the kernel management function unit 12, and is displayed through the system status bicolor indicator 18. If the self-check of the RS232 interface unit 8, the Ethernet interface unit 7 or the FPGA unit 3 is abnormal, the status code is sent to the STM32 singlechip system 6 for processing through the kernel management function unit 12, and is displayed through the system status bicolor indicator 18.
Claims (3)
1. The data acquisition method of the implantable control system is characterized by comprising a data acquisition device connected with the implantable control system, wherein the acquisition device comprises a field bus unit (9), an FPGA unit (3), an STM32 singlechip system (6), a memory unit (19) and a network interface unit (20);
the field bus unit (9) comprises a bus driving circuit (1) and a bus protocol controller (2) which are connected in a bidirectional manner, and the bus driving circuit (1) is connected with a field bus (16);
the bus protocol controller (2) is in bidirectional connection with the FPGA unit (3), the FPGA unit (3) comprises a protocol chip control logic interface (10), a capacity memory logic interface (11), a kernel management function unit (12) and an internal resource coordination function unit (13), the protocol chip control logic interface (10) is in bidirectional connection with the internal resource coordination function unit (13), the protocol chip control logic interface (10) is in unidirectional connection with the capacity memory logic interface (11), the capacity memory logic interface (11) is in bidirectional connection with the internal resource coordination function unit (13), and the internal resource coordination function unit (13) is in unidirectional connection with the kernel management function unit (12);
the capacity memory logic interface (11) is connected with the memory unit (19) in a bidirectional manner, the internal resource coordination function unit (13) is connected with the STM32 singlechip system (6) in a bidirectional manner, and the STM32 singlechip system (6) is connected with the network interface unit (20);
the memory unit (19) comprises an SDRAM memory and an expandable TF card memory (5), and the SDRAM memory and the expandable TF card memory (5) are both connected with the capacity memory logic interface (11) in a bidirectional manner;
the network interface unit (20) comprises an Ethernet interface unit (7) and an RS232 interface unit (8), wherein the Ethernet interface unit (7) is connected with an output physical interface (15) of an Ethernet interface circuit, the RS232 interface unit (8) is connected with an output physical interface (14) of an RS232 interface circuit, and the Ethernet interface unit (7) and the RS232 interface unit (8) are connected with an STM32 singlechip system (6);
an operation indicator lamp (17) and a system state double-color indicator lamp (18) are connected to the STM32 singlechip system (6);
the data acquisition method comprises the following steps:
1) after power-on and starting, an FPGA unit (3) and an STM32 singlechip system (6) start to be initialized at the same time, and the FPGA unit (3) initializes a protocol chip control logic interface (10), a capacity memory logic interface (11), a kernel management function unit (12) and an internal resource coordination function unit (13) and performs self-inspection;
2) Initializing a bus protocol controller (2), then performing self-checking on the bus protocol controller (2), an SDRAM (synchronous dynamic random access memory) memory (4) and an extensible TF card memory (5), and starting to receive and process instructions of an STM32 singlechip system (6) after the self-checking is normal;
the method comprises the steps that field bus data are converted into TTL signals which can be identified by a bus protocol controller (2) through a bus driving circuit (1) from RS485 signals on a field bus (16), then the bus protocol controller (2) converts bus coding signals on the bus driving circuit (1) into digital signals in a binary format which can be identified by an internal protocol chip control logic interface (10), the internal protocol chip control logic interface (10) transmits the signals to a capacity memory logic interface (11), and the capacity memory logic interface (11) compresses the data signals according to a set acquisition rate and stores the compressed data signals in an extensible TF card memory (5) after time stamping;
3) After initializing the STM32 singlechip system (6) in the step 1), carrying out self-checking on the RS232 interface unit (8) and the Ethernet interface unit (7), transmitting self-checking data of the FPGA unit (3) to the STM32 singlechip system (6), and after the self-checking is normal, starting to receive and process instruction data of the RS232 interface unit (8) and the Ethernet interface unit (7) by the STM32 singlechip system (6);
4) When data is required to be inquired, an instruction is sent to an internal resource coordination functional unit (13) through an STM32 singlechip system (6), then the data in an expandable TF card memory (5) is inquired through a capacity memory logic interface (11), and an inquiry result is output through an RS232 interface unit (8) or an Ethernet interface unit (7);
5) When the external equipment needs to read real-time data on the field bus unit (9), the STM32 singlechip system (6) sends an instruction to the internal resource coordination function unit (13), then the internal resource coordination function unit (13) sends an instruction to the bus protocol controller (2) through the protocol chip control logic interface (10), the bus driving circuit (1) reads the real-time data from the field bus (16), and the read data is transmitted by the STM32 singlechip system (6) through the RS232 interface unit (8) or through the Ethernet interface unit (7).
2. The method for acquiring data of an implantable control system according to claim 1, wherein: in the step 2), if the self-checking of the bus protocol controller (2), the SDRAM memory (4) or the expandable TF card memory (5) is abnormal, the status code is sent to the STM32 singlechip system (6) for processing through the kernel management function unit (12), and is displayed through the system status bicolor indicator lamp (18).
3. The method for acquiring data of an implantable control system according to claim 2, wherein: in the step 3), if the self-checking of the RS232 interface unit (8) and the Ethernet interface unit (7) is abnormal, the state code is sent to the STM32 singlechip system (6) for processing through the kernel management function unit (12), and is displayed through the system state double-color indicator lamp (18).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811271904.2A CN109358547B (en) | 2018-10-29 | 2018-10-29 | Data acquisition method of implanted control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811271904.2A CN109358547B (en) | 2018-10-29 | 2018-10-29 | Data acquisition method of implanted control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109358547A CN109358547A (en) | 2019-02-19 |
| CN109358547B true CN109358547B (en) | 2023-09-19 |
Family
ID=65347234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811271904.2A Active CN109358547B (en) | 2018-10-29 | 2018-10-29 | Data acquisition method of implanted control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109358547B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113156855A (en) * | 2021-04-07 | 2021-07-23 | 杭州永谐科技有限公司成都分公司 | Miniature data acquisition and processing system |
| CN114003521B (en) * | 2021-10-28 | 2022-09-20 | 北京机械工业自动化研究所有限公司 | STM32 and FPGA-based X-waveband light-weight accelerator data acquisition and transmission system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635487A (en) * | 2003-12-30 | 2005-07-06 | 中国科学院空间科学与应用研究中心 | A 386EX CPU based embedded computer system |
| CN101825894A (en) * | 2010-04-30 | 2010-09-08 | 北京航空航天大学 | SF6 high-voltage circuit breaker state intelligent monitoring and health management system |
| CN102339324A (en) * | 2011-09-15 | 2012-02-01 | 中国电力科学研究院 | High-speed data acquisition card implemented on basis of hardware |
| CN103218323A (en) * | 2013-03-25 | 2013-07-24 | 广东工业大学 | High-speed data acquisition and transmission device |
| CN103530263A (en) * | 2013-10-11 | 2014-01-22 | 上海航天测控通信研究所 | 1553B remote terminal device based on FPGA / MCU structure |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN209373376U (en) * | 2018-10-29 | 2019-09-10 | 甘肃酒钢集团宏兴钢铁股份有限公司 | A kind of implanted control system data acquisition facility |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012050934A2 (en) * | 2010-09-28 | 2012-04-19 | Fusion-Io, Inc. | Apparatus, system, and method for a direct interface between a memory controller and non-volatile memory using a command protocol |
| CN109752992B (en) * | 2018-12-06 | 2022-01-21 | 贵州航天电子科技有限公司 | FPGA +8051 system controller |
-
2018
- 2018-10-29 CN CN201811271904.2A patent/CN109358547B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635487A (en) * | 2003-12-30 | 2005-07-06 | 中国科学院空间科学与应用研究中心 | A 386EX CPU based embedded computer system |
| CN101825894A (en) * | 2010-04-30 | 2010-09-08 | 北京航空航天大学 | SF6 high-voltage circuit breaker state intelligent monitoring and health management system |
| CN102339324A (en) * | 2011-09-15 | 2012-02-01 | 中国电力科学研究院 | High-speed data acquisition card implemented on basis of hardware |
| CN103218323A (en) * | 2013-03-25 | 2013-07-24 | 广东工业大学 | High-speed data acquisition and transmission device |
| CN103530263A (en) * | 2013-10-11 | 2014-01-22 | 上海航天测控通信研究所 | 1553B remote terminal device based on FPGA / MCU structure |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN209373376U (en) * | 2018-10-29 | 2019-09-10 | 甘肃酒钢集团宏兴钢铁股份有限公司 | A kind of implanted control system data acquisition facility |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109358547A (en) | 2019-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103792928B (en) | A kind of industrial field data acquisition analysis system based on Modbus | |
| CN103123485B (en) | Intelligent data acquisition and control terminal and Internet of Things system with same | |
| CN107065706B (en) | A kind of distributed telemetry station working-condition monitoring system | |
| CN109358547B (en) | Data acquisition method of implanted control system | |
| CN105589438A (en) | Intelligent mobile communication base station energy management system | |
| CN107241232B (en) | Fault positioning system and method suitable for dispatching automation network analysis | |
| CN103941312A (en) | Remote rainfall monitoring system | |
| CN103676866A (en) | Embedded networked multivariate input and output system | |
| CN102932222A (en) | Communication converter supporting recommended standard (RS) 485 and Modbus multi-master station data acquisition | |
| CN203522340U (en) | Power consumption load monitoring system | |
| CN202837399U (en) | Synchronized phasor measurement apparatus | |
| CN110658752A (en) | Data acquisition system applied to remote cloud monitoring | |
| CN205176626U (en) | Intelligent movement communication base station energy management device | |
| CN209373376U (en) | A kind of implanted control system data acquisition facility | |
| CN102290864B (en) | Method and device for implementing virtual load management terminal | |
| CN201549934U (en) | Remote terminal device | |
| CN209373779U (en) | Power failure active reporting Intelligent meter box system | |
| CN215956553U (en) | Edge gateway device for virtual power plant | |
| CN202794917U (en) | Water supply data acquisition and analysis system | |
| CN110086261B (en) | Industrial feeder line distribution terminal | |
| CN210071174U (en) | Multifunctional wireless temperature measuring device for electrical contact | |
| CN211124041U (en) | Oil gas field thing networking intelligent terminal equipment | |
| CN112714105A (en) | Embedded OPC UA protocol conversion system | |
| CN210052032U (en) | Well site sharing intelligent remote terminal control device based on wireless network | |
| CN203630563U (en) | Remote intelligent measurement and control unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |