CN209373376U - A kind of implanted control system data acquisition facility - Google Patents

Abstract

The utility model belongs to automatic measurement technical field, disclose a kind of implanted control system data acquisition facility, to solve the problems, such as that the high speed of prior art control system data obtains, the implanted control system data acquisition facility includes fieldbus unit, FPGA unit, STM32 SCM system, memory cell and Network Interface Unit, fieldbus unit includes the bus driving circuits being bi-directionally connected and bus protocol switching controller, bus protocol switching controller is bi-directionally connected with FPGA unit, FPGA unit includes protocol chip control logic interface, internal mass memory storage logic interfacing, inner core managing functional unit and internal resource mediation function, the utility model can be by replacing fieldbus unit, facilitate and applies in other types of fieldbus networks.It is more accurate to the signal acquisition of the high speed variation in control system, process data is effectively acquired, and acquisition data precision is higher, installation and debugging are convenient and reliable.

Description

A kind of implanted control system data acquisition facility

Technical field

The utility model relates to automatic measurement technical fields, and in particular to a kind of implanted control system data acquisition dress It sets.

Background technique

The collection and preservation of the running process data of control system are extremely important, can observe control by these data The operating condition and equipment daily management of system and associated peripheral and the important means of equipment fault analysis.Usual feelings Control system data acquisition is all to be recorded, stored by the trend function of man-machine interface program under condition.Due to control system Core missions are to guarantee that control program accurate and effective executes, and the software and hardware resources of control system and peripheral device communication are limited , therefore man-machine interface program data acquisition capacity is limited, external equipment to control system data access time interval be by Limitation, generally require data access time interval to be greater than 0.1s, the man-machine interface program HMI number in general industry control system It is usually set between 0.1s-1s according to refresh interval, being normally set up refresh interval is 1s, thus can satisfy behaviour Make personnel to require the observation of equipment and control.

According to sampling thheorem it is found that when sample frequency fs.max is greater than in signal 2 times of highest frequency fmax (fs.max > 2fmax), the digital signal after sampling completely remains the information in original signal, guarantees to adopt in general practical application Sample frequency is 2.56~4 times of signal highest frequency, it may be assumed that fs.max > (2.56-4) fmax.Such as effectively acquire a frequency The signal of 10Hz, frequency acquisition should reach 25.6-40Hz, obtain data time interval should between 39ms-25ms, It is lost every excessive signal detail, interval too small will lead to software and hardware resources waste, is reasonably selected in practice according to specific requirement, is Effective some random signals of crawl, sampling time interval should be smaller.

0.1s-1s data acquisition intervals are ok in the not high control operation task of many movement velocitys under normal conditions It meets the requirements, the course data histories trend obtained in this state can also objectively respond equipment course of work state change. But the signal of high speed variation cannot be met the requirements in the process data that this acquisition interval obtains, at present both at home and abroad The high speed of control system data is obtained and is generally realized using mating specialized hardware, expensive and poor universality is generally answered In the large-scale control systems such as milling train.Also have using pure software implementation, but be typically employed in the not high control of required precision System processed, the control system high for required precision cannot be met the requirements, and the prior art can not solve above-mentioned technical problem.

Utility model content

The problem of purpose of the utility model is to solve the acquisitions of the high speed of prior art control system data, The process data and installation and debugging convenience, reliable implanted control system number of control system can be obtained at a high speed by providing one kind According to acquisition device.

In order to achieve the above object, the utility model uses following technical scheme:

A kind of implanted control system data acquisition facility, including fieldbus unit, FPGA unit, STM32 single-chip microcontroller System, memory cell and Network Interface Unit；

Fieldbus unit includes the bus driving circuits being bi-directionally connected and bus protocol switching controller, bus driver Circuit connection has fieldbus；

Bus protocol switching controller is bi-directionally connected with FPGA unit, and FPGA unit includes that protocol chip control logic connects Mouth, internal mass memory storage logic interfacing, inner core managing functional unit and internal resource mediation function, protocol chip Control logic Interface & Bus protocol conversion controller and internal resource mediation function are bi-directionally connected, protocol chip control Logic interfacing is unidirectionally connect with capacity memory logic interfacing, capacity memory logic interfacing and internal resource mediation function It being bi-directionally connected, internal resource mediation function is unidirectionally connect with inner core managing functional unit,

The capacity memory logic interfacing is bi-directionally connected with memory cell, internal resource mediation function with STM32 SCM system is bi-directionally connected, and STM32 SCM system is connect with Network Interface Unit.

Further, memory cell includes SRAM memory and expansible TF card memory, and SRAM memory, can Extension TF card memory is bi-directionally connected with capacity memory logic interfacing.

Further, Network Interface Unit includes Ethernet interface unit and RS232 interface unit, Ethernet interface list Member is connected with the output physical interface of ethernet interface circuit, and RS232 interface unit is connected with the output of RS232 interface circuit Interface is managed, and Ethernet interface unit and RS232 interface unit are connect with STM32 SCM system.

Further, run indicator and system mode bi-colour LED are connected on STM32 SCM system.

The utility model compared with the existing technology, has the advantages that

The utility model can map a data space as control system, and control system is only visible to data field. The operation of all pairs of data passes through the corresponding logic interfacing of FPGA and realizes that the utility model realizes agreement by programming to FPGA Chip controls logic interfacing, internal mass memory storage logic interfacing, inner core managing functional unit and internal resource coordination function Unit composition control logic circuit.Each regional function of these logic units is mutually indepedent simultaneously, also irrelevant in logic.Due to Control system maps fieldbus unit the data field to be formed and refreshes in each scan period, therefore device has fastly Fast reading takes the hardware foundation of data field, cooperates the high-speed data acquiring device of corresponding system composition implantation control system.This reality It can be facilitated and be applied in other types of fieldbus networks by replacing fieldbus unit with novel.The utility model It is more accurate to the signal acquisition of the high speed variation in control system, the process data of control system is effectively acquired, and acquires Data precision is higher, and installation and debugging are convenient and reliable.The Ethernet interface unit of the utility model externally provides ethernet communication object Interface is managed, data communication RS232 interface can be carried out with the other external equipments with Ethernet interface for meeting communications protocol Unit externally provides the RS232 communication physical interface of standard, can have the outer of RS232 interface with the other of communications protocol are met Portion's equipment carries out data communication.

Detailed description of the invention

Fig. 1 is the connection schematic diagram of the utility model.

Fig. 2 is the inside arrangement schematic diagram of the utility model.

Appended drawing reference meaning is as follows: 1. bus driving circuits；2. bus protocol switching controller；3.FPGA unit； 4.SRAM memory；5. expansible TF card memory；6.STM32 SCM system；7. Ethernet interface unit；8.RS232 connects Mouth unit；9. fieldbus unit；10. protocol chip control logic interface；11. internal mass memory storage logic interfacing；12. Inner core managing functional unit；13. internal resource mediation function；14.RS232 the output physical interface of interface circuit；15. with The too output physical interface of network interface circuit；16. fieldbus；17. run indicator；18. system mode bi-colour LED.

Specific embodiment

The utility model is described in further detail with reference to the accompanying drawings and detailed description.

As shown in Figs. 1-2, a kind of implanted control system data acquisition facility, including fieldbus unit 9, FPGA unit 3, STM32 SCM system 6, memory cell 19 and Network Interface Unit 20；Fieldbus unit 9 includes being bi-directionally connected Bus driving circuits 1 and bus protocol switching controller 2, bus driving circuits 1 access fieldbus 16, fieldbus 16 with RS485 signal on fieldbus 16 is converted into bus protocol converter 2 by control system connection, bus driving circuits 1 The TTL signal that can be identified, on the contrary the TTL signal that bus protocol converter 2 issues can also be converted into the transmission of RS485 signal Onto fieldbus 16.Bus protocol switching controller 2 is made of the intelligent chip that one includes field bus protocol stack, bus Protocol conversion controller 2 is bi-directionally connected with FPGA unit 3, can be by the protocol chip control logic interface inside FPGA unit 3 The datagram or order report of the 10 straight binary formats issued are converted into fieldbus encoded signal, then pass through bus protocol Switching controller 2 and bus driving circuits 1 are sent on fieldbus 16, otherwise bus protocol switching controller 2 can also be in the future Being converted into 3 internal agreement chip controls logic interfacing 10 of fpga chip from the bus code signal of bus driving circuits 1 can know The digital signal of other binary format.Bus driving circuits 1 and bus protocol switching controller 2 and its attached electronic member device Part collectively constitutes fieldbus unit 9, and design is mounted in same printed circuit board.

FPGA unit 3 is field programmable gate array, and inside function unit is by Hardware description language Verilog HDL programming is realized.FPGA unit 3 includes protocol chip control logic interface 10, internal mass memory storage logic interfacing 11, interior Core management function 12 and internal resource mediation function 13, protocol chip control logic interface 10 and internal resource are assisted Conditioning function unit 13 is bi-directionally connected, and protocol chip control logic interface 10 is unidirectionally connect with capacity memory logic interfacing 11, interior Portion's mass storage logic interfacing 11 is bi-directionally connected with internal resource mediation function 13, internal resource mediation function 13 unidirectionally connect with inner core managing functional unit 12, internal mass memory storage logic interfacing 11 and SRAM memory 4, expansible TF card memory 5 is bi-directionally connected, and internal resource mediation function 13 and STM32 SCM system 6 is bi-directionally connected, STM32 SCM system 6 is connect with Network Interface Unit 20.Network Interface Unit 20 includes that Ethernet interface unit 7 and RS232 connect Mouth unit 8, Ethernet interface unit 7 are connected with the output physical interface 15 of ethernet interface circuit, and RS232 interface unit 8 connects Be connected to the output physical interface 14 of RS232 interface circuit, and Ethernet interface unit 7 and RS232 interface unit 8 with STM32 SCM system 6 connects.Run indicator 17 and the double-colored instruction of system mode are connected on STM32 SCM system 6 Lamp 18.Inner core managing functional unit 12 is responsible for the bus node address of setting data acquisition facility, and detection bus address state is simultaneously Bus state code is sent to STM32 SCM system 6 to handle.

Wherein protocol chip control logic interface 10 is responsible for communicating with fieldbus unit 9, and fieldbus unit 9 is sent Signal receive and be transmitted to internal mass memory storage logic interfacing 11 and internal resource mediation function 13 respectively.It is internal Mass storage logic interfacing 11 is responsible for being temporarily stored in SDRAM memory 4 after the signal received is added timestamp, It can be saved for a long time according to requiring that data are stored in expansible TF card memory 5 simultaneously.The data compression of storage system, data Organization and administration, data access function are realized by internal mass memory storage logic interfacing 11.Internal resource mediation function 13 are responsible for order and data between processing and STM32 SCM system 6, when external equipment needs to read fieldbus unit 9 Instruction is issued to internal resource coordination function by STM32 SCM system 6 when data in data or expansible TF card memory 5 Then unit 13 passes through fieldbus unit by protocol chip control logic interface 10 by internal resource mediation function 13 9 read real time data from fieldbus 16, or by internal mass memory storage logic interfacing 11 from expansible TF card memory 5 Data are read, the data of reading pass through output of the RS232 interface unit 8 through RS232 interface circuit by STM32 SCM system 6 Physical interface 14 is sent by Ethernet interface unit 7 through the output physical interface 15 of ethernet interface circuit.The data obtain It takes device normally to access fieldbus 16 and 17 green of run indicator is always on when correct configuration is to control system, otherwise run and refer to Show 17 green flashing of lamp.System mode bi-colour LED 18 when any mistake being not detected in the data acquisition facility course of work It does not work, corresponding instruction is otherwise made according to fault code, system mode bi-colour LED 18 includes red indicating light and orange Indicator light.Red indicating light is always on expression system and expendable severe hardware failure occurs, and red indicating light flashing indicates dress It sets bus address to clash with other unit addresses on fieldbus, orange indicating light flashing indicated between the one second time of appearance Every it is interior appearance at least once sampled data lose, do not occur again within ten seconds sampled data lose indicator light extinguish, otherwise by Orange indicating light flashing is changed into orange indicating light and is always on.It can only according to priority be shown from high to low when above-mentioned failure occurs simultaneously Showing a kind of state, priority is respectively from high to low: red indicating light is always on, red indicating light flashes, orange indicating light is always on It is flashed with orange indicating light.

The bus protocol switching controller 2 selects the dedicated DP consultative management chip SPC3 of German SIEMENS company, Be integrated with complete DP agreement, can complete independently bus line command coding and decoding and bus marco work, can be effectively reduced place The computational load for managing device, the DP bus interface baud rate based on SPC3 composition can achieve 12Mbaud.

The bus driving circuits 1 select the bus driver chip ADM2486 of U.S. ADI company, the chip using magnetic every From technology, biography rate low in energy consumption is high, and SPC3 passes through bus driving circuits high speed sending and receiving data message in bus.

The FPGA unit 3 selects the industrial-scale mass integrated circuit of ALTERA company of the U.S's production EP4CE10F17C8N realizes bus protocol chip controls logic interfacing 10, inside great Rong using its logical resource programming abundant Measure memory logic interface 11, inner core managing functional unit 12 and and internal resource mediation function 13, FPGA unit 3 can With personalized customization control logic, personalized high speed logic algorithm and control function are realized.

The SDRAM memory 4 selects South Korea Hynix product, model H57V1262GTR, the logic with FPGA unit 3 Interference fit is used for bus procedure data fast cache, can effectively eliminate the bottleneck on device data transmission channel, improves device High speed and reliability.

The expansible TF card memory 5 can be inserted into the TF card of CLASS4 speed step of the 4M to 64M capacity as needed, For storing the process data for needing to save for a long time, data organization uses queue form, after data storage area is filled with data, New data will go successively to queue, while the data being stored in earliest are then lost automatically.Bus procedure data in operational process In addition being packaged into expansible TF card memory 5 after timestamp.

The main realization device internal state management of the STM32 SCM system 6 and serial ports and Ethernet interface data Communication function realizes that data acquisition working condition is shown by run indicator 17, the data acquisition life that data requirements person issues Order is handled by STM32 SCM system 6 according to program.External equipment needs the request of the data obtained by STM32 SCM system 6 passes through the internal resource mediation function 13 and internal mass memory storage logic of FPGA unit 3 after parsing Interface 11 takes out, and is then exported by RS232 interface unit 8 or Ethernet interface unit 7.Ethernet interface unit 7 selects collection At embedded networked devices USR-K2.RS232 interface unit 8 is made of MAX232 interface chip.

In application, in the field bus system that fieldbus 16 passes through plug access control system, then by control system Configuration is carried out to the data acquisition facility, which is mapped to a bus station data area of control system. The operating mode that the data acquisition facility can be set by host computer, is divided into offline mode and online mode, when offline mode RS485 signal on fieldbus 16 is converted into bus protocol conversion by bus driving circuits 1 by fieldbus data The TTL signal that device 2 can identify, bus protocol switching controller 2 convert the bus code signal from bus driving circuits 1 At the digital signal for the binary format that 3 internal agreement chip controls logic interfacing 10 of fpga chip can identify, internal agreement Signal is passed to internal mass memory storage logic interfacing 11, internal mass memory storage logic by chip controls logic interfacing 10 Storage is into expansible TF card memory 5 after data-signal is compressed according to the acquisition rate of setting and add timestamp by interface 11. When needing to inquire data can by STM32 SCM system 6, internally resource coordination functional unit 13 issues instruction, then by Internal mass memory storage logic interfacing 11 inquires expansible 5 data of TF card memory, and query result is by RS232 interface unit 8 Or Ethernet interface unit 7 exports.

External data demand equipment passes through RS232 interface unit 8 or Ethernet interface unit 7 to STM32 when online mode SCM system 6 issues request, then passes through internal resource mediation function 13, protocol chip by STM32 SCM system 6 Control logic interface 10, fieldbus unit 9, field-bus interface 16 directly acquire control system process data.

After electrifying startup, the chip (each functional unit) and STM32 SCM system 6 of FPGA3 unit 3 are started simultaneously at initially Change.Wherein FPGA unit 3 initialization establish protocol chip control logic interface 10, internal mass memory storage logic interfacing 11, Inner core managing functional unit 12 and internal resource mediation function 13, then initialization bus protocol controller 2, then carries out The self-tests such as SDRAM memory etc. 4, if self-test normally begins to receive and handle the instruction of STM32 SCM system 6, then Fieldbus unit signal processing is carried out, data are normally with regard to carrying out bus data compression, storage and transmission, in cycles；STM32 SCM system 6 also initializes immediately after powering on, and then carries out the self-tests such as RS232 interface unit 8, Ethernet interface unit 7, from Instruction or data from RS232 interface unit 8 or Ethernet interface unit 7 are started to process after inspection is normal, phase is entered after analysis Function subprogram is answered, is executed in cycles.If self-test is abnormal, state code is sent to by inner core managing functional unit 12 The processing of STM32 SCM system 6, and shown by system mode bi-colour LED 18.Method particularly includes:

1) after electrifying startup, FPGA unit 3 and STM32 SCM system 6 start simultaneously at initialization, and FPGA unit 3 is initial Change protocol chip control logic interface 10, internal mass memory storage logic interfacing 11, inner core managing functional unit 12 and inside Resource coordination functional unit 13 and self-test.

2) initialization bus protocol controller 2 after then carries out bus protocol controller 2, SDRAM memory 4, can expand The self-test for opening up TF card memory 5 starts the instruction for receiving and handling STM32 SCM system 6 after self-test is normal.

RS485 signal on fieldbus 16 is converted into bus by bus driving circuits 1 by fieldbus data The TTL signal that protocol converter 2 can identify, bus protocol switching controller 2 will be total on bus driving circuits 1 later Line coding signal is converted into the digital signal for the binary format that internal agreement chip controls logic interfacing 10 can identify, internal Signal is passed to internal mass memory storage logic interfacing 11, internal mass memory storage by protocol chip control logic interface 10 Data-signal is compressed according to the acquisition rate of setting and is stored in expansible TF card memory 5 after adding timestamp by logic interfacing 11 In.

3) RS232 interface unit 8, Ethernet interface unit 7 are carried out after STM32 SCM system 6 initializes in step 1) Self-test, while the self-inspection data of FPGA unit 3 passes to STM32 SCM system 6, after self-test is normal, STM32 single-chip microcontroller system System 6 starts to receive and handle the director data from RS232 interface unit 8, Ethernet interface unit 7.

4) by STM32 SCM system 6, internally resource coordination functional unit 13 issues instruction when needing to inquire data, Then the data in expansible TF card memory 5 are inquired by internal mass memory storage logic interfacing 11, query result is by RS232 Interface unit 8 or Ethernet interface unit 7 export.

5) it when external equipment needs to read the real time data on fieldbus unit 9, is sent out by STM32 SCM system 6 It is instructed out to internal resource mediation function 13, is then patrolled by internal resource mediation function 13 by protocol chip control It collects interface 10 and issues instructions to bus protocol converter 2, then read real-time number from fieldbus 16 by bus driving circuits 1 According to the data of reading are transmitted by STM32 SCM system 6 by RS232 interface unit 8 or by Ethernet interface unit 7.Such as The self-test of fruit bus protocol controller 2, SDRAM memory 4 or expansible TF card memory 5 is abnormal, then passes through inner core managing State code is sent to STM32 SCM system 6 and handled by functional unit 2, and is carried out by system mode bi-colour LED 18 Display.If the self-test of RS232 interface unit 8, Ethernet interface unit 7 or FPGA unit 3 is abnormal, pass through inner core managing State code is sent to STM32 SCM system 6 and handled by functional unit 2, and is carried out by system mode bi-colour LED 18 Display.

Claims (4)

1. a kind of implanted control system data acquisition facility, it is characterized in that: including fieldbus unit (9), FPGA unit (3), STM32 SCM system (6), memory cell (19) and Network Interface Unit (20)；

The fieldbus unit (9) includes the bus driving circuits (1) and bus protocol switching controller being bi-directionally connected (2), bus driving circuits (1) are connected with fieldbus (16)；

The bus protocol switching controller (2) is bi-directionally connected with FPGA unit (3), and FPGA unit (3) includes protocol chip control Logic interfacing (10), internal mass memory storage logic interfacing (11), inner core managing functional unit (12) and internal resource processed Mediation function (13), protocol chip control logic interface (10) are bi-directionally connected with internal resource mediation function (13), Protocol chip control logic interface (10) is unidirectionally connect with capacity memory logic interfacing (11), internal mass memory storage logic Interface (11) is bi-directionally connected with internal resource mediation function (13), internal resource mediation function (13) and inner core managing Functional unit (12) unidirectionally connects；

The internal mass memory storage logic interfacing (11) is bi-directionally connected with memory cell (19), internal resource coordination function Unit (13) is bi-directionally connected with STM32 SCM system (6), and STM32 SCM system (6) and Network Interface Unit (20) are even It connects.

2. a kind of implanted control system data acquisition facility according to claim 1, it is characterized in that: the memory list First (19) include SRAM memory (4) and expansible TF card memory (5), and SRAM memory (4), expansible TF card store Device (5) is bi-directionally connected with internal mass memory storage logic interfacing (11).

3. a kind of implanted control system data acquisition facility according to claim 1 or 2, it is characterized in that: the network Interface unit (20) includes Ethernet interface unit (7) and RS232 interface unit (8), and Ethernet interface unit (7) is connected with The output physical interface (15) of ethernet interface circuit, RS232 interface unit (8) are connected with the output of RS232 interface circuit It manages interface (14), and Ethernet interface unit (7) and RS232 interface unit (8) are connect with STM32 SCM system (6).

4. a kind of implanted control system data acquisition facility according to claim 3, it is characterized in that: the STM32 is mono- Run indicator (17) and system mode bi-colour LED (18) are connected in piece machine system (6).