CN109742145B - SOI device and manufacturing method thereof - Google Patents
SOI device and manufacturing method thereof Download PDFInfo
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- CN109742145B CN109742145B CN201811467318.5A CN201811467318A CN109742145B CN 109742145 B CN109742145 B CN 109742145B CN 201811467318 A CN201811467318 A CN 201811467318A CN 109742145 B CN109742145 B CN 109742145B
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Abstract
The invention relates to the technical field of radiation resistance, in particular to an SOI device and a manufacturing method thereof, which comprises the following steps: the buried oxide layer is located in the substrate, the heating resistor, the source electrode, the grid electrode, the drain electrode and the isolation layer are located above the buried oxide layer, the isolation layer is arranged around the outer sides of the source electrode and the drain electrode, a heat conduction layer is arranged between the isolation layer and the buried oxide layer, the heating resistor is arranged around the outer side of the isolation layer, and the heating resistor is provided with a first resistor port and a second resistor port which are used for applying voltage. The invention can realize the heating of the device by arranging the heating resistor in the SOI device and improve the temperature of the SOI device so as to improve the total dose resistance of the SOI device, and simultaneously, the voltage applied on the heating resistor can be dynamically adjusted, so that the technical effect of dynamically adjusting the total dose resistance of the SOI device can be realized by dynamically adjusting the voltage on the heating resistor, and the total dose resistance of the SOI device is improved.
Description
Technical Field
The invention relates to the technical field of radiation resistance, in particular to an SOI device and a manufacturing method thereof.
Background
When the device is continuously subjected to ionizing radiation, the threshold voltage of the device is shifted, the transconductance is reduced, the sub-threshold current is increased, the low-frequency noise is increased, and even the device is failed, namely the total dose irradiation effect. The total dose irradiation effect is mainly caused by charges and defects generated in the oxide layer and at the oxide layer or silicon interface by ionizing radiation.
Because the Silicon On Insulator (SOI) CMOS circuit realizes complete medium isolation, the area of a PN junction is small, and a parasitic field region MOS tube and a silicon controlled rectifier structure in a bulk silicon CMOS technology do not exist, the photocurrent generated by the radiation of the SOI CMOS circuit is nearly three orders of magnitude smaller than that of the bulk silicon CMOS circuit, and further, the SOI CMOS circuit has outstanding advantages in the aspects of single event resistance, instantaneous radiation resistance and the like and is widely applied. However, for partially depleted SOI devices, the buried oxide charge generated by the ionizing radiation may cause inversion at the back interface, thereby affecting device performance, such that the total dose exposure resistance of SOI devices of the same feature size is rather inferior to that of bulk silicon devices.
In the prior art, on one hand, the back channel of the SOI device can be highly doped in the process to improve the threshold voltage of the back gate, so that the bearing capacity of the back gate MOS tube on the change of the threshold voltage caused by irradiation is improved; on the other hand, a BUSFET structure may be employed in which the source region of the MOS transistor is not yet doped to the bottom of the silicon film, and although total dose irradiation also results in inversion of the back interface, the formation of a back channel is prevented because the source is above, so that the adverse effect of irradiation-induced charges in the buried oxide layer on the overall performance of the device is reduced to an extremely low level.
However, the above two methods can only improve the total dose resistance of the device to a certain extent, and once the process and the structure determine the total dose resistance, the total dose resistance is determined, and cannot be dynamically adjusted.
Disclosure of Invention
In view of the above, the present invention has been made to provide an SOI device and a method of fabricating the same that overcomes or at least partially solves the above problems.
The invention provides an SOI (silicon on insulator) device, which comprises a substrate, a buried oxide layer, a heating resistor, a source electrode, a grid electrode, a drain electrode, a heat conducting layer and an isolating layer, wherein the substrate is provided with a plurality of insulating layers;
the buried oxide layer is located in the substrate;
the heating resistor, the source electrode, the grid electrode, the drain electrode and the isolation layer are positioned above the buried oxide layer;
the isolation layer is arranged around the outer sides of the source electrode and the drain electrode, and the heat conduction layer is arranged between the isolation layer and the buried oxide layer;
the heating resistor is disposed around an outside of the isolation layer, and the heating resistor has a first resistor port and a second resistor port for applying a voltage.
Preferably, the isolation layer is ultra-shallow trench isolation.
Preferably, the thickness of the buried oxide layer is 1nm-1 um.
Preferably, if the type of the SOI device is NMOS, the heating resistor is an N-well resistor or an N-injection resistor.
Preferably, if the type of the SOI device is PMOS, the heating resistor is a P-well resistor or a P-implant resistor.
Preferably, the material of the heat conduction layer is silicon.
Preferably, the thickness of the heat conduction layer is 1nm-1 um.
The present invention also provides a method for manufacturing an SOI device, which is applied to manufacture the SOI device according to the foregoing embodiment, and the method includes:
forming a buried oxide layer in a substrate;
manufacturing a source electrode, a grid electrode and a drain electrode above the buried oxide layer;
forming an isolation layer above the buried oxide layer and around the outer sides of the source electrode and the drain electrode, and forming a heat conduction layer between the isolation layer and the buried oxide layer;
and manufacturing a heating resistor above the buried oxide layer and around the outer side of the isolation layer, wherein the heating resistor is provided with a first resistor port and a second resistor port for applying voltage.
According to the SOI device and the manufacturing method thereof of the present invention, the SOI device comprises a substrate, a buried oxide layer, a heating resistor, a source electrode, a gate electrode, a drain electrode, a heat conducting layer and an isolating layer, wherein the buried oxide layer is positioned in the substrate, the heating resistor, the source electrode, the gate electrode, the drain electrode and the isolating layer are positioned above the buried oxide layer, the isolating layer is arranged around the outer sides of the source electrode and the drain electrode, and the heat conducting layer is arranged between the isolating layer and the buried oxide layer, the heating resistor is arranged around the outer side of the isolating layer, and the heating resistor is provided with a first resistor port and a second resistor port for applying voltage, the heating resistor is arranged in the SOI device, the heating of the device can be realized by the heating resistor, the temperature of the SOI device is increased, so as to improve the total dose resistance performance of the SOI device, meanwhile, the voltage applied on the heating resistor can be dynamically adjusted, and the technical effect of dynamically adjusting the total dose resistance capability of the SOI device can be realized by dynamically adjusting the voltage on the heating resistor, the total dose resistance of the SOI device is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a top view of an SOI device in an embodiment of the invention;
FIG. 2 illustrates a cross-sectional view at A-A' of FIG. 1 in an embodiment of the present invention;
fig. 3 shows a flow chart of a method for fabricating an SOI device in an embodiment of the present invention.
The device comprises a substrate 1, a buried oxide layer 2, a source 3, a gate 4, a drain 5, an isolation layer 6, a heating resistor 7, a heat conduction layer 8, a first resistor port 71 and a second resistor port 72, wherein the buried oxide layer is formed on the substrate, the source 3 is formed on the isolation layer, the heating resistor 7 is formed on the heat conduction layer, and the first resistor port 72 is formed on the heat conduction layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The embodiment of the invention provides an SOI device which is shown in fig. 1 and fig. 2 and comprises a substrate 1, a buried oxide layer 2, a heating resistor 7, a source electrode 3, a grid electrode 4, a drain electrode 5, a heat conduction layer 8 and an isolation layer 6.
For the buried oxide layer 2, the buried oxide layer 2 is located in the substrate 1, and the buried oxide layer 2 is a box (buried oxide) layer. The buried oxide layer 2 is used for electrically isolating the substrate 1 from the heating resistor 7, so as to prevent the heating resistor 7 from influencing the substrate 1 after voltage is applied to the heating resistor 7, and further influencing devices on the whole chip. The buried oxide layer 2 may be made of any material used for the buried oxide layer 2 in the prior art. If the thickness of the buried oxide layer 2 is too thick, the heat transfer will be affected, and if the thickness of the buried oxide layer 2 is too thin, the voltage on the heating resistor 7 will affect the electric field distribution of the silicon film, therefore, in the embodiment of the present invention, preferably, the thickness of the buried oxide layer 2 is 1nm-1um, for example, the thickness of the buried oxide layer 2 may be 50nm, 100nm, 500nm, or 700nm, and by selecting the buried oxide layer 2 having the above thickness range, it can be ensured that the voltage applied to the heating resistor 7 will not affect the device while ensuring the heat transfer.
In the embodiment of the invention, the heating resistor 7, the source electrode 3, the gate electrode 4, the drain electrode 5 and the isolation layer 6 are positioned above the buried oxide layer 2. The isolation layer 6 is provided around the outside of the source electrode 3 and the drain electrode 5 with the heat conductive layer 8 between the isolation layer 6 and the buried oxide layer 2, the heating resistor 7 is provided around the outside of the isolation layer 6, and the heating resistor 7 has a first resistance port 71 and a second resistance port 72 for applying a voltage.
Specifically, the source 3, the gate 4 and the drain 5 are formed on the buried oxide layer 2, and the source 3, the gate 4 and the drain 5 are formed by a method known in the art, which is not limited in the present application.
Specifically, the isolation layer 6 and the buried oxide layer 2 have a space therebetween, which is the heat conductive layer 8. The heat of the heating resistor 7 can be rapidly transferred to the device by using the heat conducting layer 8 as a heat conducting channel. The material of the heat conducting layer 8 is silicon. The thickness of the heat conducting layer 8 is 1nm-1 um. In the actual manufacturing process, the isolation layer 6 is manufactured in the silicon material above the buried oxide layer 2 at a preset interval, so that the interval between the isolation layer 6 and the buried oxide layer 2 is the heat conduction layer 8, and the isolation layer 6 extends upwards to the surface of the device. The isolation layer 6 is used for isolating a device, the isolation layer 6 is a Very Shallow Trench Isolation (VSTI), the VSTI is a kind of STI, generally speaking, the STI can be isolated to be in contact with the buried oxide layer 2, but the VSTI cannot be isolated to be in contact with the buried oxide layer 2, so that a spacer layer exists between the VSTI and the buried oxide layer 2, the thickness of the VSTI can be determined jointly according to the distance between the surface of the buried oxide layer 2 and the surface of the device and the thickness of the heat conduction layer 8, the VSTI and the STI belong to the same process, and the thickness of the trench is controlled only by etching time when the trench is etched. As can be seen from fig. 1, the spacer 6 is disposed around the outside of the structure formed by the source 3 and the drain 5.
Specifically, the heating resistor 7 is formed on the upper surface of the buried oxide layer 2 and extends to the surface of the device, and as can be seen from fig. 1, the heating resistor 7 is disposed around the outside of the isolation layer 6, the inside of the isolation layer 6 is the source electrode 3 and the drain electrode 5, and the heating resistor 7 disposed around has a gap which makes the heating resistor 7 have two resistor ports, a first resistor port 71 and a second resistor port 72, and in a specific embodiment, the gap is located on the side close to the drain electrode 5.
In the embodiment of the invention, the heating resistor 7 is heated by applying voltage to the heating resistor 7, so that the heating resistor 7 heats the device, the technical effect of dynamically adjusting the total dose resistance of the SOI device can be realized, and the total dose resistance of the SOI device is improved. In the adjustment, voltages can be applied to the two ports of the heating resistor 7 during the operation time or the operation gap of the SOI device according to the size of the irradiation dose, wherein the larger the total irradiation dose and the larger the device degradation, the larger the voltage applied to the heating resistor 7 and the longer the voltage application time are required.
Further, since no influence other than temperature rise is exerted on the device performance when the device is heated, that is, only heat exchange is allowed between the heating resistor 7 and the SOI device, and no current is generated, the type of the heating resistor 7 must be limited, and the material of the heating resistor 7 corresponds to the type of the SOI device:
if the SOI device is NMOS type, the heating resistor 7 is an N-well resistor or an N-implant resistor. The square resistance values of the N trap resistor and the N injection resistor are different, the square resistance of the N injection resistor is small, the voltage required to be applied during heating is small, the square resistance of the N trap resistor is large, and the voltage required to be applied during heating is large. During heating, one resistor port is applied with voltage, and the other port is grounded, so that no current exists between the heating resistor 7 and the P well, and the characteristics of the SOI device are not influenced.
If the SOI device is PMOS type, the heating resistor 7 is a P-well resistor or a P-implant resistor. The sheet resistance values of the P well resistor and the P injection resistor are different, the sheet resistance of the P injection resistor is small, the voltage required to be applied during heating is small, the sheet resistance of the P well resistor is large, and the voltage required to be applied during heating is large. During heating, one resistor port is applied with voltage, and the other port is grounded, so that no current exists between the heating resistor 7 and the N well, and the characteristics of the SOI device are not influenced.
In the invention, the SOI device generates oxide trap charges and interface state charges after total dose irradiation, the temperature of the SOI device can be improved by heating the device by using the heating resistor 7, the total dose resistance of the SOI device can be improved by increasing the temperature of the SOI device for annealing, and meanwhile, the voltage applied on the heating resistor 7 can be dynamically adjusted, so that the technical effect of dynamically adjusting the total dose resistance of the SOI device can be realized by dynamically adjusting the voltage on the heating resistor 7, and the total dose resistance of the SOI device is improved.
It should be noted that in the embodiment of the present invention, the heating resistor 7 is disposed around the MOS device, but in order to electrically isolate the MOS device, an isolation layer 6 is required between the heating resistor 7 and the MOS device, and the heat conduction layer 8 is mainly used for transferring heat to the source 3, the drain 5 and the body region of the MOS device, where the body region is the region between the source 3 and the drain 5.
Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing the SOI device, where the method is shown in fig. 3, and the method includes:
step 301: forming a buried oxide layer 2 in a substrate 1;
step 302: manufacturing a source electrode 3, a grid electrode 4 and a drain electrode 5 above the buried oxide layer 2;
step 303: an isolation layer 6 is manufactured above the buried oxide layer 2 and around the outer sides of the source electrode 3 and the drain electrode 5, and a heat conduction layer 8 is formed between the isolation layer 6 and the buried oxide layer 2;
step 304: a heating resistor 7 is fabricated above the buried oxide layer 2 and around the outside of the isolation layer 6, wherein the heating resistor 7 has a first resistive port 71 and a second resistive port 72 for applying a voltage.
In the embodiment of the present invention, the formation method of the buried oxide layer 2, the formation method of the heating resistor 7, the formation method of the source electrode 3, the formation method of the gate electrode 4, the formation method of the drain electrode 5, the formation method of the heat conductive layer 8, and the formation method of the isolation layer 6 are conventional techniques, and the present application is not limited thereto.
In summary, according to the SOI device and the method for manufacturing the same of the present invention, the SOI device includes a substrate, a buried oxide layer, a heating resistor, a source, a gate, a drain, a heat conducting layer and an isolation layer, the buried oxide layer is located in the substrate, the heating resistor, the source, the gate, the drain and the isolation layer are located above the buried oxide layer, the isolation layer is disposed around the outer sides of the source and the drain, and the heat conducting layer is disposed between the isolation layer and the buried oxide layer, the heating resistor is disposed around the outer side of the isolation layer, and the heating resistor has a first resistor port and a second resistor port for applying a voltage The effect is to improve the total dose resistance of SOI devices.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. An SOI device is characterized by comprising a substrate, a buried oxide layer, a heating resistor, a source electrode, a grid electrode, a drain electrode, a heat conduction layer and an isolation layer;
the buried oxide layer is located in the substrate;
the heating resistor, the source electrode, the grid electrode, the drain electrode and the isolation layer are positioned above the buried oxide layer;
the isolation layer is arranged around the outer sides of the source electrode and the drain electrode, and the heat conduction layer is arranged between the isolation layer and the buried oxide layer; the isolation layer is an ultra-shallow groove isolation;
the heating resistor is disposed around an outside of the isolation layer, and the heating resistor has a first resistor port and a second resistor port for applying a voltage.
2. The SOI device of claim 1, wherein the buried oxide layer has a thickness of 1nm-1 um.
3. The SOI device of claim 1, wherein the heating resistor is an N-well resistor or an N-implant resistor if the SOI device is NMOS type.
4. The SOI device of claim 1, wherein the heating resistor is a P-well resistor or a P-implant resistor if the SOI device is PMOS in type.
5. The SOI device of claim 1, wherein the material of the thermally conductive layer is silicon.
6. The SOI device of claim 1, wherein the thermally conductive layer has a thickness of 1nm to 1 um.
7. A method of manufacturing an SOI device, for use in manufacturing an SOI device as claimed in any one of claims 1 to 6, the method comprising:
forming a buried oxide layer in a substrate;
manufacturing a source electrode, a grid electrode and a drain electrode above the buried oxide layer;
forming an isolation layer above the buried oxide layer and around the outer sides of the source electrode and the drain electrode, and forming a heat conduction layer between the isolation layer and the buried oxide layer;
and manufacturing a heating resistor above the buried oxide layer and around the outer side of the isolation layer, wherein the heating resistor is provided with a first resistor port and a second resistor port for applying voltage.
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| CN1790725A (en) * | 2004-11-12 | 2006-06-21 | 国际商业机器公司 | Structure and method for annealing trapped charge in a semiconductor device |
| JP2008147590A (en) * | 2006-12-13 | 2008-06-26 | Denso Corp | Semiconductor device |
| CN102347367A (en) * | 2011-11-03 | 2012-02-08 | 中国电子科技集团公司第五十八研究所 | Structure of radiation-resistant MOS (Metal Oxide Semiconductor) device based on partially-consumed type SOI (Silicon-On-Insulator) process |
| CN103022139A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Semiconductor structure with insulating buried layer and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7704847B2 (en) * | 2006-05-19 | 2010-04-27 | International Business Machines Corporation | On-chip heater and methods for fabrication thereof and use thereof |
| US20080142899A1 (en) * | 2006-08-04 | 2008-06-19 | Silicon Space Technology Corporation | Radiation immunity of integrated circuits using backside die contact and electrically conductive layers |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790725A (en) * | 2004-11-12 | 2006-06-21 | 国际商业机器公司 | Structure and method for annealing trapped charge in a semiconductor device |
| JP2008147590A (en) * | 2006-12-13 | 2008-06-26 | Denso Corp | Semiconductor device |
| CN102347367A (en) * | 2011-11-03 | 2012-02-08 | 中国电子科技集团公司第五十八研究所 | Structure of radiation-resistant MOS (Metal Oxide Semiconductor) device based on partially-consumed type SOI (Silicon-On-Insulator) process |
| CN103022139A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Semiconductor structure with insulating buried layer and manufacturing method thereof |
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