CN103022139A - Semiconductor structure with insulating buried layer and manufacturing method thereof - Google Patents
Semiconductor structure with insulating buried layer and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductors and discloses a semiconductor structure with an insulating buried layer. The semiconductor structure comprises a support substrate, a top semiconductor layer and an MOS (metal oxide semiconductor) transistor structure, wherein the top semiconductor layer is isolated from the support substrate via the insulating buried layer, and the MOS transistor structure is formed on the top semiconductor layer. The semiconductor structure is characterized by comprising a semiconductor buffer layer between the top semiconductor layer and the insulating buried layer, and forbidden bandwidth of the material for the semiconductor buffer layer is larger than that of the top semiconductor layer. The invention further provides a manufacturing method for the semiconductor structure with the insulating buried layer. The manufacturing method includes the steps of bonding a first semiconductor substrate covered by the insulating buried layer and a semiconductor substrate covered by the semiconductor buffer layer, and thinning the second semiconductor substrate to be served as the top semiconductor layer used for manufacturing semiconductor device structures.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly with semiconductor structure of insulating buried layer and preparation method thereof.
Background technology
Since nearly over half a century, the integrated circuit industry has obtained fast development, for the arriving of information age provides the guarantee on the hardware, also has been penetrated into social various aspects, comprises the fields such as Aero-Space with adverse circumstances, military affairs, nuclear power.
Yet, owing to existing a large amount of cosmic ray (such as α particle, gamma-rays, high energy neutrons etc.) in universe and the outer space, can produce the radiation effects such as accumulated dose, single event, instantaneous radiation to integrated circuit.If the integrated circuit that adopts in the radiation environment does not pass through special radiation hardening, the performance of these circuit will soon be degenerated so that lost efficacy.Therefore, device and circuit with high radiation preventing ability are very important for applications such as military affairs, spaces, and the radiation hardened technology of semiconductor device has become current study hotspot in the integrated circuit.
As everyone knows, metal-oxide semiconductor fieldeffect transistor (mosfet transistor) is the Important Components of integrated circuit fields, has the many merits such as high speed, high integration, low cost.Development along with semiconductor technology, device size constantly dwindles, integrated level is more and more higher, and the short-channel effect that exposes in the face of the body silicon semiconductor device, parasitic controllable silicon latch-up, shallow junction and contact more and more show especially out on problems such as the impact of rate of finished products and high power consumption, low velocity.And as the SOI(Silicon on insulator of Fully dielectric isolation, silicon-on-insulator) technology, the incomparable superiority of many body silicon technologies is arranged.That the SOI cmos device has is low in energy consumption, antijamming capability is strong, integration density high (the isolation area is little), speed high (parasitic capacitance is little), technique is simple, capability of resistance to radiation is strong and substrate has been eliminated the advantages such as parasitic latch-up of bulk-Si CMOS device.Therefore, more and more be subject to the favor of industry based on the semiconductor structure of SOI.
Fig. 1 is traditional SOI mos transistor structure schematic diagram.
As shown in Figure 1, the conventional SOI MOS transistor of using is prepared from based on the SOI substrate in the prior art, related semiconductor base comprises the top-layer semiconductor 130 that is used to form semiconductor device, and this top-layer semiconductor 130 is by silicon dioxide buried regions 120 and support substrates 110 isolation.And this MOS transistor is formed on the top-layer semiconductor 130, includes source region 101a/101b, at the channel region 104 between active area 101a, the 101b and be positioned at gate oxide 103 and the polysilicon gate 102 that covers above the channel region 104, successively top-layer semiconductor 130 surfaces.In addition, also be formed with fleet plough groove isolation structure 105 around the mos transistor structure, in order to realize the isolation between other semiconductor structures on itself and the top-layer semiconductor 130.
Compare with the Semiconductor substrate device of body silicon and other homogenous materials, the semiconductor device with insulating buried layer take the SOI device as representative, owing to structurally having introduced silicon dioxide buried regions 120, with mos transistor structure and support substrates 110 isolation, and in conjunction with shallow trench isolation from (Shallow Trench Isolation, STI) technology, realized isolating by insulating medium layer fully between the semiconductor device, the cmos circuit that MOS transistor is formed has been realized completely medium isolation, the PN junction area is little, do not have place metal-oxide-semiconductor and controllable silicon mechanism parasitic in the Bulk CMOS technology, so the photoelectric current that radiation produces can be than little nearly three orders of magnitude of Bulk CMOS circuit.
Yet the existence of oxygen buried layer is negative for the ability of SOI device resistant to total dose effect.When device is in when continuing to be subject to ionising radiation (such as X ray, gamma-rays etc.) in the radiation environment, can produce the integral dose radiation effect.And ionising radiation mainly in oxide layer and oxide layer-silicon interface produces electric charge and defective, thereby the threshold voltage shift, mutual conductance reduction, the subthreshold current that cause device increase, low-frequency noise increases.Emittance can be in oxide layer excitation electron-hole pair, electron-hole pair for the radiation generation, it is generally acknowledged, the electronics that produces can shift out oxide layer very soon, oxide layer also can be shifted out in part hole, another part hole then hole trap in the oxidized layer is captured and is become positive fixed charge, electronics be captured form negative electrical charge relatively want much less.Therefore, for SOI MOS transistor as shown in Figure 1, the radiation meeting produces positive charge in silicon dioxide buried regions 120, also can produce silicon dioxide buried regions 120-top-layer semiconductor 130/ support substrates 110 interface traps, MOS transistor is exhausted near the back of the body interface zone of silicon dioxide buried regions 120, even transoid, thereby form the leakage path 106 between MOS transistor active area 101a, the 101b, so that the quiescent dissipation of integrated circuit rises, cause the degeneration of circuit reliability even the inefficacy of function.
In order to improve the anti-integral dose radiation ability of SOI device, the special reinforcement technique of normal introducing in the prior art, such as Implanted Silicon in silicon dioxide buried regions 120, produce electronic defects, be absorbed in the positive charge of oxide layer with compensation, or adopting the SIMOX(injection oxygen isolation technology) oxygen that reduces in the SOI substrate preparation process during material injects metering, thus attenuate silicon dioxide buried regions 120 is realized consolidation effect.Yet, adopt reinforcement technique to a certain degree improving the anti-integral dose radiation ability of SOI device, effect is but also not obvious.Simultaneously, in reinforcing process, inevitably to the device surface injury, affect device performance.
Along with SOI CMOS integrated circuit obtains using more and more widely under radiation environment, how to suppress the unlatching of the spurious leakage passage that radiation causes, reduce total dose effect to the impact of SOI device, improve the radioresistance characteristic of device, significant.
Summary of the invention
Technology to be solved by this invention is, a kind of semiconductor structure with insulating buried layer is provided, and has good anti-single particle effect, anti-instantaneous radiation and anti-integral dose radiation effect, can improve the Radiation hardness of semiconductor structure.
Semiconductor structure with insulating buried layer provided by the invention comprises: support substrates, the top-layer semiconductor by the isolation of insulating buried layer and described support substrates, be formed at the mos transistor structure on the described top-layer semiconductor, wherein, also comprise semiconductor buffer layer between described top-layer semiconductor and the insulating buried layer, and the energy gap of described semiconductor buffer layer material is greater than the energy gap of described top-layer semiconductor material.
As optional technical scheme, described semiconductor buffer layer is any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, and described semiconductor buffer layer thickness is 3nm ~ 15nm.
As optional technical scheme, described top-layer semiconductor is monocrystalline silicon or strained silicon or germanium silicon or germanium; Described support substrates is monocrystalline substrate or germanium substrate or Sapphire Substrate, and described insulating buried layer is silicon dioxide layer.
As optional technical scheme, the described mos transistor structure that is formed on the top-layer semiconductor also comprises the fleet plough groove isolation structure around described MOS transistor.Further, described fleet plough groove isolation structure comprise be formed at the insulating barrier in the groove and be positioned at insulating barrier and top layer semiconductor lining between semiconductor buffer layer.
The present invention also provides a semiconductor preparation method with insulating buried layer simultaneously, and the method may further comprise the steps:
The first Semiconductor substrate is provided, and forms an insulating buried layer at described the first semiconductor substrate surface;
The second Semiconductor substrate is provided, and forms the semiconductor resilient coating at described the second semiconductor substrate surface;
Bonding is aimed at the semiconductor buffer layer surface in described insulating buried layer surface;
Described the second Semiconductor substrate is carried out attenuate and flattening surface, form top-layer semiconductor;
Form mos transistor structure in described top-layer semiconductor preparation.
Wherein, the energy gap of described semiconductor buffer layer is greater than the energy gap of described the second Semiconductor substrate.
As optional technical scheme, described insulating buried layer is silicon dioxide layer, adopts thermal oxidation or chemical gaseous phase depositing process to form, and described insulating buried layer thickness is 50nm ~ 1000nm; Described semiconductor buffer layer is any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, adopts extension or chemical gaseous phase depositing process to form, and described semiconductor buffer layer thickness is 3nm ~ 15nm.
As optional technical scheme, described the second Semiconductor substrate adopts wet etching or dry etching method attenuate, and adopts cmp method to realize flattening surface; The described top-layer semiconductor thickness that the second Semiconductor substrate attenuate forms is 50nm ~ 500nm.
As optional technical scheme, described the first Semiconductor substrate is monocrystalline substrate or germanium substrate or Sapphire Substrate, and described the second Semiconductor substrate is monocrystalline silicon or strained silicon or germanium silicon or germanium substrate.
As optional technical scheme, should also be included in the semiconductor structure preparation method of insulating buried layer top-layer semiconductor forms fleet plough groove isolation structure around the zone of described MOS transistor step.Further, the step of described formation fleet plough groove isolation structure further comprises:
Define shallow plough groove isolation area in top-layer semiconductor, and graphical etching forms groove;
In described groove, form the semiconductor buffer layer that covers described grooved inner surface;
In being coated with the groove of semiconductor buffer layer, described inner surface fills insulating barrier.
Semiconductor structure with insulating buried layer provided by the invention and preparation method thereof, the top-layer semiconductor and the support substrates that adopt insulating buried layer will prepare the semiconductor structures such as MOS transistor are isolated, anti-single particle effect and anti-instantaneous radiation that can the Effective Raise semiconductor structure; Simultaneously, be somebody's turn to do in the semiconductor structure with insulating buried layer, also has the semiconductor resilient coating between the top-layer semiconductor of the semiconductor structures such as preparation MOS transistor and the insulating buried layer, and the energy gap of this semiconductor buffer layer is greater than the energy gap of top-layer semiconductor, like this, because the semiconductor buffer layer energy gap of insulating buried layer top is larger, the difficulty that then forms the inversion layer charge carrier in this semiconductor buffer layer increases greatly, be equivalent to promote the threshold value that parasitic transistor leaks raceway groove, the unlatching of spurious leakage raceway groove after can establishment irradiation, play the effect of radiation hardened, thereby improved the ability of the anti-integral dose radiation of SOI integrated circuit.And this semiconductor structure preparation method and standard CMOS process are fully compatible, compare with conventional semiconductor structure preparation method, thin film deposition, bonding and attenuate step have only been increased, can't bring any damage to top-layer semiconductor and semiconductor structure, can when improving semiconductor structure Radiation hardness and device performance, ensure low cost and high finished product rate.
Description of drawings
Fig. 1 is traditional SOI mos transistor structure schematic diagram;
Fig. 2 is the semiconductor structure schematic diagram with insulating buried layer provided by the invention;
Fig. 3 is provided by the invention with fleet plough groove isolation structure schematic diagram in the semiconductor structure of insulating buried layer;
Fig. 4 is the semiconductor structure preparation method flow chart of steps with insulating buried layer provided by the invention;
Fig. 5 ~ Fig. 9 is each step structural representation of semiconductor structure preparation method with insulating buried layer provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing embodiments of the present invention are described in further detail.Those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be used by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
This embodiment provides a semiconductor structure with insulating buried layer.
The semiconductor structure schematic diagram with insulating buried layer that Fig. 2 provides for this embodiment.
As shown in Figure 2, the semiconductor structure with insulating buried layer that this embodiment provides comprises: support substrates 210, by insulating buried layer 211 top-layer semiconductor 220 with described support substrates isolation, be formed at the semiconductor structure 300 on the described top-layer semiconductor 220, wherein, also comprise semiconductor buffer layer 221 between described top-layer semiconductor 220 and the insulating buried layer 211, and the energy gap of described semiconductor buffer layer 221 materials is greater than the energy gap of described top-layer semiconductor 220 materials.
In this embodiment, described support substrates 210 is monocrystalline substrate or germanium substrate or Sapphire Substrate; Insulating buried layer 211 is silicon dioxide layer, and its thickness is 50nm ~ 1000nm; Top-layer semiconductor 220 is monocrystalline silicon or strained silicon or germanium silicon or germanium.Wherein, support substrates 210 and top-layer semiconductor 220 can also can be used for for other are known the III-V family material of semiconductor device preparation, and top-layer semiconductor 220 thickness are 50nm ~ 500nm, more excellent, its thickness is 200nm ~ 400nm, can mix for the P type, also can mix for N-type.
In this embodiment, as shown in Figure 2, the semiconductor structure 300 that is formed on the described top-layer semiconductor 220 is the semiconductor device take MOS transistor as representative, and can form cmos circuit.Wherein, be formed at active area 301a/301b that mos transistor structure 300 on the top-layer semiconductor 220 comprises that ion implantation doping forms, at the channel region 304 between active area 301a, the 301b and be positioned at gate oxide 303 and the polysilicon gate 302 that covers above the channel region 304, successively top-layer semiconductor 220 surfaces.This mos transistor structure 300 can be nmos pass transistor, also can be the PMOS transistor, and simultaneously, this mos transistor structure 300 can be full depletion mos transistor, also can be the part depletion MOS transistor.
As most preferred embodiment, semiconductor buffer layer 221 is single layer structure, and is concrete, can in carborundum, silicon nitride, gallium nitride, the GaAs any one, and these semiconductor buffer layer 221 thickness are 3nm ~ 15nm, better, its thickness is 10nm.
As optional embodiment, semiconductor buffer layer 221 is laminated construction, and is concrete, can be any several laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, and the gross thickness of this laminated semiconductor resilient coating 221 is 3nm ~ 15nm, and is more excellent, and its thickness is 15nm.
In this embodiment, as shown in Figure 2, be formed at semiconductor structure 300 on the top-layer semiconductor 220 and also comprise fleet plough groove isolation structure 305 around this semiconductor structure 300.Fig. 3 for this embodiment provide with fleet plough groove isolation structure schematic diagram in the semiconductor structure of insulating buried layer.As shown in Figure 3, this shallow trench isolation comprises the insulating barrier 352 that is formed in the groove and is positioned at insulating barrier 352 and the semiconductor buffer layer 351 of 220 of top-layer semiconductor from 305, and the energy gap of described semiconductor buffer layer 351 is greater than the energy gap of top-layer semiconductor 220.As optional embodiment, semiconductor buffer layer 351 is any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, and thickness is 3nm ~ 15nm.Need to prove, being somebody's turn to do can be identical at fleet plough groove isolation structure 305 insulating barriers 352 and the semiconductor buffer layer 351 of 220 of top-layer semiconductor and semiconductor buffer layer 221 dielectric materials between insulating buried layer 211 and top-layer semiconductor 220, also can be different, its thickness can be identical, also can be different.As most preferred embodiment, should be identical with semiconductor buffer layer 221 dielectric materials between insulating buried layer 211 and top-layer semiconductor 220 with the semiconductor buffer layer 351 of 220 of top-layer semiconductor at fleet plough groove isolation structure 305 insulating barriers 352, be carborundum, and thickness equates, is 10nm.
In this embodiment, monocrystalline silicon or germanium material energy gap at room temperature as top-layer semiconductor 220 are respectively 1.12eV and 0.66eV, and are respectively 2eV, 5.4eV, 5.47eV and 3.44eV as carborundum, silicon nitride, gallium nitride, the GaAs energy gap at room temperature of semiconductor buffer layer 221.This shows, the energy gap of semiconductor buffer layer 221 is much larger than the energy gap of top-layer semiconductor 220, like this, the difficulty that forms the inversion layer charge carrier in semiconductor buffer layer 221 increases greatly, suppressed the generation of electric leakage path between mos transistor structure 300 active area 301a, the 301b, be equivalent to promote parasitic transistor and leaked the threshold value of raceway groove, thereby improved the ability of IC semiconductor structure anti-integral dose radiation.
This embodiment also provides a semiconductor structure preparation method with insulating buried layer.
The semiconductor structure preparation method step schematic diagram with insulating buried layer that Fig. 4 provides for this embodiment.
As shown in Figure 4, this embodiment may further comprise the steps:
Step S1: the first Semiconductor substrate 210 is provided, and forms an insulating buried layer 211 on described the first Semiconductor substrate 210 surfaces.
As shown in Figure 5, the first Semiconductor substrate 210 is monocrystalline substrate or germanium substrate or Sapphire Substrate, covers its surperficial insulating buried layer 211 and is silicon dioxide layer.In this step, insulating buried layer 211 adopts thermal oxidation or chemical gaseous phase depositing process to form, and its thickness is 50nm ~ 1000nm.As most preferred embodiment, the first Semiconductor substrate 210 is monocrystalline substrate, and silicon dioxide insulator buried regions 211 adopts thermal oxidation process to realize, its thickness is 500nm.
Step S2: the second Semiconductor substrate 220 is provided, and forms semiconductor resilient coating 221 on described the second Semiconductor substrate 220 surfaces.
As shown in Figure 6, described the second Semiconductor substrate 220 is monocrystalline silicon or strained silicon or germanium silicon or germanium substrate, cover its surperficial semiconductor buffer layer 221 and be any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, adopt extension or chemical gaseous phase depositing process to form, described semiconductor buffer layer thickness is 3nm ~ 15nm.As most preferred embodiment, the second Semiconductor substrate 220 is monocrystalline substrate, and semiconductor buffer layer 221 is the carborundum single layer structure, and it adopts chemical gaseous phase depositing process to form, and described semiconductor buffer layer 221 thickness are 10nm.
In this step, the energy gap of semiconductor buffer layer 221 materials is greater than the energy gap of the second Semiconductor substrate 220 materials.
Step S3: bonding is aimed at semiconductor buffer layer 221 surfaces in described insulating buried layer 211 surfaces.
As shown in Figure 7, take insulating buried layer 211 surfaces that cover the first Semiconductor substrate 210 surfaces and semiconductor buffer layer 221 surfaces that cover the second Semiconductor substrate 220 as bonding face, with the two bonding, form the semiconductor-based bottom structure with insulating buried layer 210 take the first Semiconductor substrate 210 as support substrates.In this step, comprise that also the surface coverage before the bonding has the first Semiconductor substrate 210 of insulating buried layer 211 and surface clean and the activation processing of the second Semiconductor substrate 220 that surface coverage has insulating buried layer 221.
Step S4: described the second Semiconductor substrate 220 is carried out attenuate and flattening surface, form top-layer semiconductor.
As shown in Figure 8, adopt wet etching or dry etching method that the second Semiconductor substrate 220 is thinned to 50nm ~ 500nm, and the second semiconductor substrate surface after adopting cmp method to attenuate carry out planarization, formation top-layer semiconductor 220.As most preferred embodiment, the second Semiconductor substrate 220 adopts the wet etching method attenuate, and at this moment, the first semiconductor substrate surface adopts photoresist or other dielectric materials as mask, and top-layer semiconductor 220 thickness that form behind the attenuate are 300nm.
So far, finish for the preparation of the semiconductor base preparation of semiconductor device structure.This semiconductor base comprises: the support substrates that the first Semiconductor substrate 210 forms, top-layer semiconductor 220 for the preparation of semiconductor structure, with the insulating buried layer 211 of top-layer semiconductor 220 with support substrates 210 isolation, and the semiconductor buffer layer 221 between insulating buried layer 211 and top-layer semiconductor 220.
The order that it is pointed out that step S1, step S2 is not limited by this embodiment, also can first execution in step S2, execution in step S1 again, or the two is carried out simultaneously.
Step S5: form mos transistor structure 300 in described top-layer semiconductor 220 preparations.
This step further comprises: deposit successively the step that gate oxide 303 and polycrystalline silicon grid layer 302 and etching formation polysilicon gate and Implantation are formed with source region 301a, 301b on top-layer semiconductor 220 surfaces.
As shown in Figure 9, mos transistor structure 300 is prepared on the top-layer semiconductor 220, the Implantation degree of depth that is formed with source region 301a, 301b is top-layer semiconductor 220 thickness, that is: the active area 301a/301b of mos transistor structure 300 runs through whole top-layer semiconductor 220; The zone of top-layer semiconductor 220 between two active area 301a, 301b is the channel region 304 of mos transistor structure 300, and this mos transistor structure 300 also comprises and is positioned at channel region 304 tops, covers gate oxide 303 and the polysilicon gate 302 on top-layer semiconductor 220 surfaces successively.As optional embodiment, this mos transistor structure 300 can be full depletion mos transistor, also can be the part depletion MOS transistor; Simultaneously, this mos transistor structure 300 can be nmos pass transistor, also can be the PMOS transistor.
As most preferred embodiment, among the semiconductor structure preparation method with insulating buried layer that this embodiment provides, also comprise:
Step S6: form shallow trench isolation from 305 around the zone of described mos transistor structure 300 in top-layer semiconductor 220.
Formed fleet plough groove isolation structure 305 as shown in Figure 3 in this step.
This step is further comprising the steps:
Step S61: define shallow plough groove isolation area in top-layer semiconductor 220, and graphical etching forms groove.
In this step, shallow plough groove isolation area is positioned at mos transistor structure 300 sides, and around the mos transistor structure 300 on the top-layer semiconductor 220 and other semiconductor device.The definition of above-mentioned shallow plough groove isolation area adopts photolithographic exposure to realize, and adopts wet etching or dry etching method to be etched to expose semiconductor buffer layer 221 or insulating buried layer 211 surfaces, form etching groove.As most preferred embodiment, the etching of described groove adopts inductively coupled plasma etching to realize.
Step S62: in described groove, form the semiconductor buffer layer 351 that covers described grooved inner surface.
In this step, semiconductor buffer layer 351 adopts extension or chemical gaseous phase depositing process to realize, and the energy gap of described semiconductor buffer layer 351 is greater than the energy gap of top-layer semiconductor 220.As optional embodiment, semiconductor buffer layer 351 is any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, and thickness is 3nm ~ 15nm.Need to prove, being somebody's turn to do can be identical at fleet plough groove isolation structure 305 insulating barriers 352 and the semiconductor buffer layer 351 of 220 of top-layer semiconductor and semiconductor buffer layer 221 dielectric materials between insulating buried layer 211 and top-layer semiconductor 220, also can be different, its thickness can be identical, also can be different.As most preferred embodiment, semiconductor buffer layer 351 adopts epitaxy method to realize, it is identical with semiconductor buffer layer 221 dielectric materials, is silicon nitride, and thickness is equal, is 8nm.
Step S63: in described inner surface is coated with the groove of semiconductor buffer layer, fill insulating barrier 352.
In this step, insulating barrier 352 is silicon dioxide, adopts chemical gaseous phase depositing process to fill.
According to above-mentioned semiconductor structure preparation method, can prepare the semiconductor structure with insulating buried layer 211 as shown in Figure 2.The top-layer semiconductor 220 that this structure adopts insulating buried layer 211 will prepare the semiconductor structures such as MOS transistor is isolated with support substrates 210, anti-single particle effect and anti-instantaneous radiation that can the Effective Raise semiconductor structure; Simultaneously, be somebody's turn to do in the semiconductor structure with insulating buried layer 211, also has semiconductor resilient coating 221 between the top-layer semiconductor 220 of preparation MOS transistor 300 semiconductor structures such as grade and the insulating buried layer 211, and the energy gap of this semiconductor buffer layer 221 is greater than the energy gap of top-layer semiconductor 220, like this, because semiconductor buffer layer 221 energy gaps of insulating buried layer 211 tops are larger, the difficulty that then forms the inversion layer charge carrier in this semiconductor buffer layer 221 increases greatly, be equivalent to promote the threshold value that parasitic transistor leaks raceway groove, the unlatching of spurious leakage raceway groove after can establishment irradiation, play the effect of radiation hardened, thereby improved the ability of the anti-integral dose radiation of SOI integrated circuit.
In addition, the semiconductor structure preparation method that this embodiment provides and standard CMOS process are fully compatible, compare with conventional semiconductor structure preparation method, only increase thin film deposition, bonding and attenuate step, can't bring any damage to top-layer semiconductor and semiconductor structure.And generally speaking, the thickness of the inversion layer of high concentration only has several nanometers, and therefore, in order to reach good radioresistance characteristic, semiconductor buffer layer 221 thickness of broad stopband only need surpass this thickness and get final product, such as 3 ~ 15nm.The semiconductor buffer layer 220 of this thickness is very thin, and comparing with traditional soi structure only is to have made trickle change, and the preparation method is simple, can when improving semiconductor structure Radiation hardness and device performance, ensure low cost and high finished product rate.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (18)
1. semiconductor structure with insulating buried layer, comprise: support substrates, the top-layer semiconductor by the isolation of insulating buried layer and described support substrates, be formed at the mos transistor structure on the described top-layer semiconductor, it is characterized in that, also comprise semiconductor buffer layer between described top-layer semiconductor and the insulating buried layer, and the energy gap of described semiconductor buffer layer material is greater than the energy gap of described top-layer semiconductor material.
2. the semiconductor structure with insulating buried layer according to claim 1 is characterized in that, described semiconductor buffer layer is any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs.
3. the semiconductor structure with insulating buried layer according to claim 1 is characterized in that, described semiconductor buffer layer thickness is 3nm ~ 15nm.
4. the semiconductor structure with insulating buried layer according to claim 1 is characterized in that, described top-layer semiconductor is monocrystalline silicon or strained silicon or germanium silicon or germanium; Described support substrates is monocrystalline substrate or germanium substrate or Sapphire Substrate.
5. the semiconductor structure with insulating buried layer according to claim 1 is characterized in that, described insulating buried layer is silicon dioxide layer.
6. the described semiconductor structure with insulating buried layer of any one is characterized in that according to claim 1 ~ 5, and the described mos transistor structure that is formed on the top-layer semiconductor also comprises the fleet plough groove isolation structure around described MOS transistor.
7. the semiconductor structure with insulating buried layer according to claim 6 is characterized in that, described fleet plough groove isolation structure comprise be formed at the insulating barrier in the groove and be positioned at insulating barrier and top-layer semiconductor between semiconductor buffer layer.
8. semiconductor structure preparation method with insulating buried layer may further comprise the steps:
The first Semiconductor substrate is provided, and forms an insulating buried layer at described the first semiconductor substrate surface;
The second Semiconductor substrate is provided, and forms the semiconductor resilient coating at described the second semiconductor substrate surface;
Bonding is aimed at the semiconductor buffer layer surface in described insulating buried layer surface;
Described the second Semiconductor substrate is carried out attenuate and flattening surface, form top-layer semiconductor;
Form mos transistor structure in described top-layer semiconductor preparation.
9. the semiconductor structure preparation method with insulating buried layer according to claim 8 is characterized in that, the energy gap of described semiconductor buffer layer is greater than the energy gap of described the second Semiconductor substrate.
10. the semiconductor structure preparation method with insulating buried layer according to claim 9 is characterized in that, described insulating buried layer is silicon dioxide layer, adopts thermal oxidation or chemical gaseous phase depositing process to form.
11. the semiconductor structure preparation method with insulating buried layer according to claim 9 is characterized in that the thickness of described insulating buried layer is 50nm ~ 1000nm.
12. the semiconductor structure preparation method with insulating buried layer according to claim 9, it is characterized in that, described semiconductor buffer layer is any one or a few laminated construction in carborundum, silicon nitride, gallium nitride, the GaAs, adopts extension or chemical gaseous phase depositing process to form.
13. the semiconductor structure preparation method with insulating buried layer according to claim 9 is characterized in that described semiconductor buffer layer thickness is 3nm ~ 15nm.
14. the semiconductor structure preparation method with insulating buried layer according to claim 9 is characterized in that, described the second Semiconductor substrate adopts wet etching or dry etching method attenuate, and adopts cmp method to realize flattening surface.
15. the semiconductor structure preparation method with insulating buried layer according to claim 14 is characterized in that described top-layer semiconductor thickness is 50nm ~ 500nm.
16. the semiconductor structure preparation method with insulating buried layer according to claim 9, it is characterized in that, described the first Semiconductor substrate is monocrystalline substrate or germanium substrate or Sapphire Substrate, and described the second Semiconductor substrate is monocrystalline silicon or strained silicon or germanium silicon or germanium substrate.
17. the described semiconductor structure preparation method with insulating buried layer of any one is characterized in that according to claim 8 ~ 16, also be included in top-layer semiconductor around the zone of described MOS transistor form shallow trench isolation from step.
18. the semiconductor structure preparation method with insulating buried layer according to claim 17 is characterized in that, described formation shallow trench isolation from step further comprise:
Define shallow plough groove isolation area in top-layer semiconductor, and graphical etching forms groove;
In described groove, form the semiconductor buffer layer that covers described grooved inner surface;
In being coated with the groove of semiconductor buffer layer, described inner surface fills insulating barrier.
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| CN103066106A (en) * | 2012-12-31 | 2013-04-24 | 上海集成电路研发中心有限公司 | Transistor isolation structure and manufacture method thereof |
| CN104347522A (en) * | 2013-07-31 | 2015-02-11 | 浙江大学苏州工业技术研究院 | Implementation method based on III-V gallium nitride intelligent power integrated circuit |
| CN109742145A (en) * | 2018-12-03 | 2019-05-10 | 中国科学院微电子研究所 | SOI device and preparation method thereof |
| CN109801847A (en) * | 2019-01-07 | 2019-05-24 | 中国科学院微电子研究所 | A kind of SOI device structure and preparation method thereof |
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| CN103066106A (en) * | 2012-12-31 | 2013-04-24 | 上海集成电路研发中心有限公司 | Transistor isolation structure and manufacture method thereof |
| CN104347522A (en) * | 2013-07-31 | 2015-02-11 | 浙江大学苏州工业技术研究院 | Implementation method based on III-V gallium nitride intelligent power integrated circuit |
| CN109742145A (en) * | 2018-12-03 | 2019-05-10 | 中国科学院微电子研究所 | SOI device and preparation method thereof |
| CN109742145B (en) * | 2018-12-03 | 2022-01-11 | 中国科学院微电子研究所 | SOI device and manufacturing method thereof |
| CN109801847A (en) * | 2019-01-07 | 2019-05-24 | 中国科学院微电子研究所 | A kind of SOI device structure and preparation method thereof |
| CN109801847B (en) * | 2019-01-07 | 2020-06-23 | 中国科学院微电子研究所 | SOI device structure and preparation method thereof |
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| CN103022139B (en) | 2017-06-23 |
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