CN109742085B - SOI device and manufacturing method thereof - Google Patents
SOI device and manufacturing method thereof Download PDFInfo
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- CN109742085B CN109742085B CN201811456986.8A CN201811456986A CN109742085B CN 109742085 B CN109742085 B CN 109742085B CN 201811456986 A CN201811456986 A CN 201811456986A CN 109742085 B CN109742085 B CN 109742085B
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Abstract
The invention relates to the technical field of radiation resistance, in particular to an SOI device and a manufacturing method thereof, which comprises the following steps: the first buried oxide layer is positioned in the substrate; the heating resistor is positioned above the first buried oxide layer, and two ends of the heating resistor are provided with resistor ports exposed on the surface of the device; the two first isolation regions are positioned above the first buried oxide layer and positioned at the outer sides of two ends of the heating resistor; the second buried oxide layer is positioned above the heating resistor; the source electrode, the grid electrode and the drain electrode are positioned above the second buried oxide layer; one second isolation region is disposed between the source and the resistive port near the source, and the other second isolation region is disposed between the drain and the resistive port near the drain. The invention can realize the technical effect of dynamically adjusting the total dose resistance of the SOI device by utilizing the heating resistor, and can avoid the influence of the voltage applied to the heating resistor on the device by utilizing the first isolation region.
Description
Technical Field
The invention relates to the technical field of radiation resistance, in particular to an SOI device and a manufacturing method thereof.
Background
When the device is continuously subjected to ionizing radiation, the threshold voltage of the device is shifted, the transconductance is reduced, the sub-threshold current is increased, the low-frequency noise is increased, and even the device is failed, namely the total dose irradiation effect. The total dose irradiation effect is mainly caused by charges and defects generated in the oxide layer and at the oxide layer or silicon interface by ionizing radiation.
Because the Silicon On Insulator (SOI) CMOS circuit realizes complete medium isolation, the area of a PN junction is small, and a parasitic field region MOS tube and a silicon controlled rectifier structure in a bulk silicon CMOS technology do not exist, the photocurrent generated by the radiation of the SOI CMOS circuit is nearly three orders of magnitude smaller than that of the bulk silicon CMOS circuit, and further, the SOI CMOS circuit has outstanding advantages in the aspects of single event resistance, instantaneous radiation resistance and the like and is widely applied. However, for partially depleted SOI devices, the buried oxide charge generated by the ionizing radiation may cause inversion at the back interface, thereby affecting device performance, such that the total dose exposure resistance of SOI devices of the same feature size is rather inferior to that of bulk silicon devices.
In the prior art, on one hand, the back channel of the SOI device can be highly doped in the process to improve the threshold voltage of the back gate, so that the bearing capacity of the back gate MOS tube on the change of the threshold voltage caused by irradiation is improved; on the other hand, a BUSFET structure may be employed in which the source region of the MOS transistor is not yet doped to the bottom of the silicon film, and although total dose irradiation also results in inversion of the back interface, the formation of a back channel is prevented because the source is above, so that the adverse effect of irradiation-induced charges in the buried oxide layer on the overall performance of the device is reduced to an extremely low level.
However, the above two methods can only improve the total dose resistance of the device to a certain extent, and once the process and the structure determine the total dose resistance, the total dose resistance is determined, and cannot be dynamically adjusted.
Disclosure of Invention
In view of the above, the present invention has been made to provide an SOI device and a method of fabricating the same that overcomes or at least partially solves the above problems.
The invention provides an SOI (silicon on insulator) device, which comprises a substrate, a first buried oxide layer, a heating resistor, a second buried oxide layer, a source electrode, a grid electrode, a drain electrode, two first isolation regions and two second isolation regions, wherein the first buried oxide layer is arranged on the substrate;
the first buried oxide layer is located in the substrate;
the heating resistor is positioned above the first buried oxide layer, and two ends of the heating resistor are provided with resistor ports exposed on the surface of the device;
the two first isolation regions are positioned above the first buried oxide layer and positioned at the outer sides of two ends of the heating resistor;
the second buried oxide layer is positioned above the heating resistor;
the source, the gate and the drain are located above the second buried oxide layer;
one of the second isolation regions is disposed between the source and the resistive port near the source, and the other of the second isolation regions is disposed between the drain and the resistive port near the drain.
Preferably, the material of the heating resistor is a semiconductor material.
Preferably, the material of the heating resistor is silicon or germanium.
Preferably, the thickness of the heating resistor is 10nm-1 um.
Preferably, the thickness of the first buried oxide layer is 1nm-1 um.
Preferably, the material of the first isolation region is silicon dioxide.
Preferably, the second isolation region is a shallow trench isolation region.
The embodiment of the present invention further provides a method for manufacturing an SOI device, which is applied to manufacture the SOI device according to the foregoing embodiment, and the method includes:
forming a first buried oxide layer in a substrate;
manufacturing a heating resistor above the first buried oxide layer, and respectively leading out resistor ports exposed on the surface of the device from two ends of the heating resistor;
respectively manufacturing first isolation regions above the first buried oxide layer and outside the two ends of the heating resistor, so as to form two first isolation regions above the first buried oxide layer;
manufacturing a second buried oxide layer above the heating resistor;
manufacturing a source electrode, a grid electrode and a drain electrode above the second buried oxide layer;
and respectively manufacturing a second isolation region in a region between the source electrode and the resistance port close to the source electrode and a region between the drain electrode and the resistance port close to the drain electrode, thereby forming two second isolation regions above the second buried oxide layer.
According to the SOI device and the manufacturing method thereof of the present invention, the SOI device comprises a substrate, a first buried oxide layer, a heating resistor, a second buried oxide layer, a source, a gate, a drain, two first isolation regions and two second isolation regions, wherein the first buried oxide layer is located in the substrate, the heating resistor is located above the first buried oxide layer, and two ends of the heating resistor are provided with a resistor port exposed on the surface of the device, two first isolation regions are located above the first buried oxide layer and outside two ends of the heating resistor, the second buried oxide layer is located above the heating resistor, the source, the gate and the drain are located above the second buried oxide layer, one second isolation region is located between the source and the resistor port close to the source, and the other second isolation region is located between the drain and the resistor port close to the drain, utilize the heating resistor can realize the heating to the device, improve the temperature of SOI device, the mode of annealing can improve the anti total dose performance of SOI device through improving SOI device temperature, simultaneously, because the voltage of exerting on the heating resistor can dynamic adjustment, and then can also realize the technological effect of adjusting the anti total dose ability of SOI device through the voltage on the dynamic adjustment heating resistor, improve the anti total dose performance of SOI device, and utilize first isolation region to keep apart the heating resistor, can avoid exerting the voltage on the heating resistor and cause the influence to the device.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 illustrates a cross-sectional view of an SOI device in an embodiment of the present invention;
FIG. 2 illustrates a top view of an SOI device in an embodiment of the present invention;
fig. 3 shows a flow chart of a method for fabricating an SOI device in an embodiment of the present invention.
Wherein, 1 is a substrate, 2 is a first buried oxide layer, 3 is a heating resistor, 31 is a first resistor port, 32 is a second resistor port, 4 is a second buried oxide layer, 5 is a source, 6 is a gate, 7 is a drain, 8 is a first isolation region, and 9 is a second isolation region.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The embodiment of the invention provides an SOI device which is shown in fig. 1 and fig. 2 and comprises a substrate 1, a first buried oxide layer 2, a heating resistor 3, a second buried oxide layer 4, a source electrode 5, a grid electrode 6, a drain electrode 7, two first isolation regions 8 and two second isolation regions 9.
For the first buried oxide layer 2, the first buried oxide layer 2 is located in the substrate 1, and the first buried oxide layer 2 is a box (buried oxide) layer. The first buried oxide layer 2 is used to electrically isolate the substrate 1 from the heating resistors 3, so as to prevent the heating resistors 3 from being affected by the applied voltage on the substrate 1, and further, the devices on the whole chip are affected. The first buried oxide layer 2 may be formed by using any material used in the prior art. If the thickness of the first buried oxide layer 2 is too thick, the heat transfer will be affected, and if the thickness of the first buried oxide layer 2 is too thin, the voltage on the heating resistor 3 will affect the electric field distribution of the silicon film, therefore, in the embodiment of the present invention, it is preferable that the thickness of the first buried oxide layer 2 is 1nm-1um, for example, the thickness of the first buried oxide layer 2 may be 50nm, 100nm, 500nm, or 700nm, and by selecting the first buried oxide layer 2 having the above thickness range, it can be ensured that the voltage applied to the heating resistor 3 will not affect the device while ensuring the heat transfer.
In the embodiment of the present invention, the heating resistor 3 is located above the first buried oxide layer 2, and two ends of the heating resistor 3 have resistor ports exposed on the surface of the device, which are a first resistor port 31 and a second resistor port 32. Two first isolation regions 8 are located above the first buried oxide layer 2 and outside two ends of the heating resistor 3.
Specifically, the heating resistor 3 and two first isolation regions 8 are formed on the upper surface of the first buried oxide layer 2. Two first isolation regions 8 are respectively located at two ends of the heating resistor 3, one first isolation region 8 is located at the left side of the heating resistor 3, and the other first isolation region 8 is located at the right side of the heating resistor 3. The first isolation region 8 extends upwardly from the upper surface of the first buried oxide layer 2 to the device surface. The material of the first isolation region 8 is silicon dioxide. The first isolation region 8 is used to isolate the device.
For the heating resistor 3, by applying a voltage to the heating resistor 3, the heating resistor 3 generates heat, and then the heating resistor 3 heats the device above the heating resistor 3, the technical effect of dynamically adjusting the total dose resistance of the SOI device can be achieved, and the total dose resistance of the SOI device can be improved. In the adjustment, a voltage can be applied to the two ends of the heating resistor 3 during the operation time or the operation gap of the SOI device according to the size of the irradiation dose, wherein the larger the total irradiation dose and the larger the device degradation, the larger the voltage applied to the heating resistor 3 and the longer the voltage application time are required. When a voltage is applied to the heating resistor 3, the voltage can be applied to the heating resistor 3 through the first and second resistor ports 31 and 32 drawn out. The heating resistor 3 is made of a semiconductor material, specifically, the heating resistor 3 can be made of silicon or germanium, and since the device is manufactured by a silicon process, the heating resistor 3 is formed by silicon conveniently and quickly. The thickness of the heating resistor 3 is 10nm-1um, so that the adjusting of the total dose resistance of the SOI device can be ensured to have a good effect.
For the second buried oxide layer 4, the second buried oxide layer 4 is located above the heating resistor 3, the second buried oxide layer 4 is formed on the upper surface of the heating resistor 3, the second buried oxide layer 4 is also a BOX layer, and the second buried oxide layer 4 can be formed by using any material used in the prior art.
For the source 5, the gate 6 and the drain 7, the source 5, the gate 6 and the drain 7 are located above the second buried oxide layer 4, and the method for manufacturing the source 5, the gate 6 and the drain 7 is prior art and is not limited in this application.
As for the second isolation regions 9, one second isolation region 9 is disposed between the source 5 and the resistive port near the source 5 (i.e., the first resistive port 31), and the other second isolation region 9 is disposed between the drain 7 and the resistive port near the drain 7 (i.e., the second resistive port 32). The second isolation region 9 is a Shallow Trench Isolation (STI). The second isolation region 9 is used for device isolation.
In the invention, the SOI device generates oxide trap charges and interface state charges after total dose irradiation, the temperature of the SOI device can be improved by heating the device by using the heating resistor 3, the total dose resistance of the SOI device can be improved by increasing the temperature of the SOI device for annealing, and meanwhile, the voltage applied on the heating resistor 3 can be dynamically adjusted, so that the technical effect of dynamically adjusting the total dose resistance of the SOI device can be realized by dynamically adjusting the voltage on the heating resistor 3, and the total dose resistance of the SOI device is improved.
Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing the SOI device, where the method is shown in fig. 3, and the method includes:
step 301: a first buried oxide layer 2 is formed in a substrate 1. The thickness of the first buried oxide layer 2 is 1nm-1 um.
Step 302: and manufacturing a heating resistor 3 above the first buried oxide layer 2, and respectively leading out resistor ports exposed on the surface of the device from two ends of the heating resistor 3. The thickness of the heating resistor 3 is 10nm-1 um.
Step 303: a first isolation region 8 is formed above the first buried oxide layer 2 and outside the two ends of the heating resistor 3, so that two first isolation regions 8 are formed above the first buried oxide layer 2.
Step 304: a second buried oxide layer 4 is formed above the heating resistor 3.
Step 305: and manufacturing a source electrode 5, a grid electrode 6 and a drain electrode 7 above the second buried oxide layer 4.
Step 306: a second isolation region 9 is formed in the region between the source 5 and the resistive port near the source 5 and in the region between the drain 7 and the resistive port near the drain 7, respectively, so that two second isolation regions 9 are formed above the second buried oxide layer 4.
In the embodiment of the present invention, the forming method of the first buried oxide layer 2, the forming method of the heating resistor 3, the forming method of the first isolation region 8, the forming method of the second buried oxide layer 4, and the forming methods of the source 5, the gate 6, the drain 7, and the second isolation region 9 are all related to the prior art, and the present application is not limited thereto.
In summary, according to the SOI device and the method for fabricating the same of the present invention, the SOI device includes a substrate, a first buried oxide layer, a heating resistor, a second buried oxide layer, a source, a gate, a drain, two first isolation regions and two second isolation regions, the first buried oxide layer is located in the substrate, the heating resistor is located above the first buried oxide layer, and two ends of the heating resistor have a resistor port exposed on the surface of the device, two first isolation regions are located above the first buried oxide layer and outside two ends of the heating resistor, the second buried oxide layer is located above the heating resistor, the source, the gate and the drain are located above the second buried oxide layer, one second isolation region is located between the source and the resistor port near the source, the other second isolation region is located between the drain and the resistor port near the drain, by adding the first isolation region and the heating resistor in the SOI device, utilize the heating resistor can realize the heating to the device, improve the temperature of SOI device, the mode of annealing can improve the anti total dose performance of SOI device through improving SOI device temperature, simultaneously, because the voltage of exerting on the heating resistor can dynamic adjustment, and then can also realize the technological effect of adjusting the anti total dose ability of SOI device through the voltage on the dynamic adjustment heating resistor, improve the anti total dose performance of SOI device, and utilize first isolation region to keep apart the heating resistor, can avoid exerting the voltage on the heating resistor and cause the influence to the device.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. An SOI device is characterized by comprising a substrate, a first buried oxide layer, a heating resistor, a second buried oxide layer, a source electrode, a grid electrode, a drain electrode, two first isolation regions and two second isolation regions;
the first buried oxide layer is located in the substrate;
the heating resistor is positioned above the first buried oxide layer, and two ends of the heating resistor are provided with resistor ports exposed on the surface of the device;
the two first isolation regions are positioned above the first buried oxide layer and positioned at the outer sides of two ends of the heating resistor;
the second buried oxide layer is positioned above the heating resistor;
the source, the gate and the drain are located above the second buried oxide layer;
one of said second isolation regions being disposed between said source and a resistive port adjacent said source, and another of said second isolation regions being disposed between said drain and a resistive port adjacent said drain;
the method for adjusting the total dose resistance of the SOI device is realized by applying voltage to the heating resistor to enable the heating resistor to generate heat, and comprises the following steps:
and applying a voltage to the two ends of the heating resistor according to the irradiation dose and the working time or the working interval of the SOI device, wherein if the total irradiation dose is larger, the voltage applied to the heating resistor is required to be larger, and the voltage application time is longer.
2. The SOI device of claim 1, wherein the material of the heater resistors is a semiconductor material.
3. The SOI device of claim 1, wherein the material of the heater resistors is silicon or germanium.
4. The SOI device of claim 1, wherein the heater resistor has a thickness of 10nm-1 um.
5. The SOI device of claim 1, wherein the first buried oxide layer has a thickness of 1nm-1 um.
6. The SOI device of claim 1 wherein the material of the first isolation region is silicon dioxide.
7. The SOI device of claim 1, in which the second isolation region is a shallow trench isolation region.
8. A method of manufacturing an SOI device, for use in manufacturing an SOI device as claimed in any one of claims 1 to 7, the method comprising:
forming a first buried oxide layer in a substrate;
manufacturing a heating resistor above the first buried oxide layer, and respectively leading out resistor ports exposed on the surface of the device from two ends of the heating resistor;
respectively manufacturing first isolation regions above the first buried oxide layer and outside the two ends of the heating resistor, so as to form two first isolation regions above the first buried oxide layer;
manufacturing a second buried oxide layer above the heating resistor;
manufacturing a source electrode, a grid electrode and a drain electrode above the second buried oxide layer;
and respectively manufacturing a second isolation region in a region between the source electrode and the resistance port close to the source electrode and a region between the drain electrode and the resistance port close to the drain electrode, thereby forming two second isolation regions above the second buried oxide layer.
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| CN116779594A (en) * | 2023-07-03 | 2023-09-19 | 西北核技术研究所 | Bipolar device based on polycrystalline silicon heating and ionizing radiation damage repairing method thereof |
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| US7064414B2 (en) * | 2004-11-12 | 2006-06-20 | International Business Machines Corporation | Heater for annealing trapped charge in a semiconductor device |
| US7704847B2 (en) * | 2006-05-19 | 2010-04-27 | International Business Machines Corporation | On-chip heater and methods for fabrication thereof and use thereof |
| KR100799577B1 (en) * | 2006-08-31 | 2008-01-30 | 한국전자통신연구원 | Method for forming sensor for detecting gases and biochemical materials, integrated circuit including the sensor, and method for manufacturing the integrated circuit |
| US9276012B2 (en) * | 2010-11-03 | 2016-03-01 | Texas Instruments Incorporated | Method to match SOI transistors using a local heater element |
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