CN109728123A - Ultra-thin silicon PIN radiation detector and preparation method based on bonding substrate - Google Patents
Ultra-thin silicon PIN radiation detector and preparation method based on bonding substrate Download PDFInfo
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Abstract
The present invention provides a kind of silicon PIN radiation detectors and preparation method thereof, it include: device layer silicon wafer (1) and supporting layer silicon wafer (4), it is connected by way of bonding between the two, is formed with the first silicon dioxide layer (2) between the two；N+Area (3), be formed in device layer silicon wafer (1) for bonding surface；P+Area (6) is formed in surface opposite with the surface for being bonded on device layer silicon wafer (1), P+It is covered in area (6) thin metal layer (8), thin metal layer (8) edge is equipped with field plate (7)；Second silicon dioxide layer (5) is formed on device layer silicon wafer (1) except P+The surface of area (6) outside；Supporting layer silicon wafer (4) corresponds to N+The position in area (3) forms cavity structure (10), and surface both is covered with thick metal layers (11).The detector has many advantages, such as that thickness is thin, area is big, good mechanical property, detector thickness determine that preparation method is simple, at low cost, high yield rate.
Description
Technical field
The present invention relates to nuclear radiation detection field more particularly to a kind of ultra-thin silicon PIN radiation detections based on bonding substrate
Device and preparation method.
Background technique
Silicon PIN detector injects the momentary pulse current signal generated after detector by detection radiating particle to measure grain
Sub- energy and identification particle kind.Silicon PIN detector is simple with structure, high sensitivity, the linearity are good, time response is fast, dynamic
The features such as state range is big, vacuum performance is stablized has important application in the nuclear physics researchs such as the measurement and diagnosis of Pulsed radiation field
Value.
Ultra-thin silicon PIN radiation detector has important application, such as pulsed radiation detection device in nuclear radiation detection, can
The ultrafast signal pulse rise time is obtained, realizes the measurement to fast radiation pulsed beams time parameter.
Most direct ultra-thin detector manufacturing method is that grinding silicon chip is thinned to required thickness, but since such thin slice exists
It is easy to broken in manufacturing process, leads to not normally produce ultra-thin detector.In order to enhance the mechanical performance of ultra-thin detector,
Mainstream way is the ultra-thin detector for obtaining having support construction in such a way that borehole is thinned at present, and thinned method has dry method
It etches and corrodes two kinds of silicon chip with TMAH (tetramethylammonium hydroxide).The cavity sidewalls of dry etching and bottom surface angle in 90 °,
Bad mechanical property easily leads to fragment, and dry etching also be easy to cause surface damage, reduces the performance of detector.So one
As select TMAH corrosion silicon chip to certain thickness obtain ultra-thin detector.
Many problems are also brought along however, being thinned using TMAH corrosion silicon chip.Firstly, when this method passes through control corrosion rate
Between and corresponding etching condition under corrosion rate obtain the detector of required thickness, but corrosion rate is affected by many factors,
It is difficult to obtain a constant corrosion rate, this will lead to detector thickness and is difficult to control, and the thickness uniformity is poor, without can weigh
Renaturation is a fatal problem for production application.Because ultra-thin detector applies directly related to detector thickness, thickness
It is inconsistent mean just to be necessary for each detector and be equipped with corresponding processing system, can not use in batches.Secondly, wet process is rotten
Erosion inevitably will increase the roughening of detector surface, and leakage current is caused to increase, and then influence detector resolution, although
The relatively low corrosion surface of roughening can be obtained by reducing corrosion rate to control leakage current and improve detector
Resolution ratio, but the defect of this method can not be inherently eliminated.The time that corrosion rate increases corrosion is reduced, production is answered
With unfavorable.The above problem causes to be difficult to produce in enormous quantities specific thicknesses and the high-performance detector with same thickness.In addition, right
In the preparation of ultra-thin detector, reduces processing step and be conducive to improve yield rate.Therefore, it is necessary to develop a set of eased
Ultra-thin detector preparation method.
Summary of the invention
(1) technical problems to be solved
It is directed to existing technical problem, the present invention provides a kind of ultra-thin silicon PIN radiation detector based on bonding substrate
And preparation method, the Δ E-E telescope that this silicon PIN radiation detector can be applied in nuclear radiation detection is to identify particle kind
And measurement particle energy, time parameter etc..For at least partly solving the above technical problem.
(2) technical solution
One aspect of the present invention provides a kind of silicon PIN radiation detector, comprising:
Device layer silicon wafer 1 and supporting layer silicon wafer 4, are connected by way of bonding between the two, are formed between the two
One silicon dioxide layer 2；
N+Area 3, be formed in the form of doping device layer silicon wafer 1 for bonding surface；
P+Area 6 is formed in surface opposite with the surface for being bonded on device layer silicon wafer 1, P in the form of doping+Area
Thin metal layer 8 is covered on 6,8 edge of thin metal layer is equipped with field plate 7；
Second silicon dioxide layer 5 is formed on device layer silicon wafer 1 except the P+Surface outside area 6；
Supporting layer silicon wafer 4 corresponds to N+The position in area 3 is formed with the cavity structure 10 of inner narrow outer width, supporting layer silicon wafer 4 and sky
10 surface of cavity configuration is covered with thick metal layers 11.
Optionally, device layer silicon wafer 1 is the N-type silicon of<111>crystal orientation, and resistivity is greater than 1000 ohmcms, thickness
Less than or equal to 100 microns；Supporting layer silicon wafer 4 is the N-type silicon of<100>crystal orientation, resistivity less than 10 ohmcms, with a thickness of
300 microns~600 microns.
Optionally, the contact area of thin metal layer 8 and device layer silicon wafer 1 is less than P+The area in area 6；N+3 area of area and device
Area equation of the layer silicon wafer 1 for the surface of bonding.
Optionally, thin metal layer 8 with a thickness of 800 angstroms~to 1200 angstroms；The thickness of thick metal layers 11 at 0.8 micron extremely
In 1.4 micron ranges.
Optionally, the cross-sectional area of cavity structure 10 is octagon or circle, on supporting layer silicon wafer 4 be used to be bonded
Acute angle folded by the side wall of the opposite surface in surface and cavity structure 10 is 54.74 °.
Another aspect of the present invention provides a kind of preparation method of silicon PIN radiation detector, comprising:
S1 forms N on the surface in 1 one surface growth regulation of device layer silicon wafer, one silicon dioxide layer 2, and by ion implanting+Area 3；
S2 connects device layer silicon wafer 1 with supporting layer silicon wafer 4 by way of being bonded, and the first silicon dioxide layer 2 is in two
Between person；
S3, surface growth regulation two dioxy opposite with the surface for being bonded on device layer silicon wafer 1 and supporting layer silicon wafer 4
SiClx layer 5；
S4, the photoetching front detection window figure in the second silicon dioxide layer 5 of device layer silicon wafer 1, and detected in front
P is formed on 1 surface of device layer silicon wafer by ion implanting form at graph window+Area 6；
S5, the photoetching Metal And Silicon contact window figure in the second silicon dioxide layer 5 of device layer silicon wafer 1, removal metal/
The second silicon dioxide layer 5 in silicon contact window figure；
S6, in P+Corresponding 1 surface of device layer silicon wafer in area 6 forms the thin metal layer 8 with field plate structure 7；
S7, the surface deposited silicon nitride layer opposite with the surface for being bonded on device layer silicon wafer 1 and supporting layer silicon wafer 4
9；
S8, the photoetching back side detection window figure on the silicon nitride layer 9 on supporting layer silicon wafer 4 remove back side detection window
Silicon nitride layer 9 and the second silicon dioxide layer 5 in figure, exposure supporting layer silicon wafer 4；
S9 removes the supporting layer silicon wafer 4 in back side detection window figure, the cavity structure 10 of narrow outer width in formation, exposure
First silicon dioxide layer 2；
S10, the silicon nitride layer 9 on removal devices layer silicon wafer 1, the second silicon dioxide layer 5 on supporting layer silicon wafer 4 and nitridation
First silicon dioxide layer 2 of silicon layer 9 and cavity structure 10；
S11 sputters thick metal layers in supporting layer silicon wafer 4 surface and cavity structure 10 opposite with for bonding surface
11；
S12 carries out alloy treatment, and metal and silicon is made to form Ohmic contact.
Optionally, device layer silicon wafer 1 is the N-type silicon of<111>crystal orientation, and resistivity is greater than 1000 ohmcms, thickness
Less than 100 microns；Supporting layer silicon wafer 4 is the N-type silicon of<100>crystal orientation, and resistivity is micro- with a thickness of 300 less than 10 ohmcms
Rice~600 microns.
Optionally, the second silicon dioxide layer 5 with a thickness of 800 angstroms~1200 angstroms；Silicon nitride layer 9 with a thickness of 800 angstroms~
2000 angstroms.
Optionally, it is injected by phosphonium ion, forms the area N+ 3, injected by boron ion, form the area P+ 6.
Optionally, in aforesaid operations S9, using the supporting layer silicon in tetramethylammonium hydroxide corrosion back side detection window
Piece 4, the cavity structure 10 of narrow outer width in formation, the concentration of tetramethylammonium hydroxide corrosive liquid are 10wt% to 25wt%, corrosion
Temperature is 80 DEG C to 95 DEG C.
(3) beneficial effect
The present invention proposes a kind of ultra-thin silicon PIN radiation detector and preparation method based on bonding substrate, has with following
Beneficial effect:
A, ultra-thin PIN radiation detector has the advantages that thickness is thin, area is big, good mechanical property, detector thickness determine,
It can be mass-produced the ultra-thin detector of same thickness using such structure, and detector thickness is controllable.And the present invention from
The irregularities of TMAH wet etching or dry etching silicon bring detector surface are fundamentally eliminated, this is detected for reducing
Device leakage current plays a significant role.
B, high temperature is carried out using the silicon wafer of two panels different crystal orientations, different resistivity and is bonded obtained silicon chip, it is super for manufacturing
Thin detector.Wherein, the application of the device layer silicon wafer 1 of high resistant<111>crystal orientation advantageously reduces leakage current and carries out particle detection
When stronger signal can be obtained；The supporting layer silicon wafer 4 of low-resistance<100>crystal orientation is corroded suitable for TMAH solution, is conducive to
The completion of etching process, and manufacturing cost can be reduced using low-resistance silicon.
C, high temperature resistant photoresist is used in the preparation method of ultra-thin PIN detector make front P+The ion implanting in area is covered
Film only needs a photoetching that the thin aluminium figure in front just can be obtained, forms front thin window structure, and thin window structure can reduce Detector's Dead
Thickness improves detector resolution, and technology is simple, for the preparation of ultra-thin detector, can not only reduce cost,
And also improve the yield rate of ultra-thin detector.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the ultra-thin silicon PIN radiation detector based on bonding substrate of the embodiment of the present invention.
Fig. 2 is the preparation method flow chart of the ultra-thin silicon PIN radiation detector based on bonding substrate of the embodiment of the present invention.
Fig. 3 A-3J is that the ultra-thin silicon PIN radiation detector preparation method based on bonding substrate of the embodiment of the present invention is corresponding
Structural schematic diagram.
[appended drawing reference] same structure uses same appended drawing reference
1- device layer silicon wafer
The first silicon dioxide layer of 2-
3-N+Area
4- supporting layer silicon wafer 4
The second silicon dioxide layer of 5-
6-P+Area
7- field plate
8- thin metal layer
9- nitrogen oxidation layer
10- cavity structure
11- thick metal layers
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
One aspect of the present invention proposes that a kind of ultra-thin silicon PIN radiation detector based on bonding substrate, Fig. 1 are the ultra-thin silicon
The structural schematic diagram of PIN radiation detector, as shown in Figure 1, ultra-thin silicon PIN radiation detector includes:
Device layer silicon wafer 1 and supporting layer silicon wafer 4, the two connect composition bonding substrate, and device layer by way of bonding
The first silicon dioxide layer 2 is formed between silicon wafer 1 and supporting layer silicon wafer 4, wherein device layer silicon wafer 1 is preferably<111>crystal orientation
N-type silicon, resistivity are greater than 1000 ohmcms, and thickness is less than or equal to 100 microns；Supporting layer silicon wafer (4) is preferably<100>
The N-type silicon of crystal orientation, resistivity is less than 10 ohmcms, with a thickness of 300 microns~600 microns.In an embodiment of the present invention,
The resistivity of device layer silicon wafer 1 is greater than 4000 ohmcms, and with a thickness of 100 microns, supporting layer silicon wafer 4, resistivity is the Europe 2-4
Nurse centimetre, with a thickness of 400 microns.
P+Area 6 is formed in surface opposite with the surface for being bonded on device layer silicon wafer 1, P in the form of doping+Area
Thin metal layer 8 is covered on 6,8 edge of thin metal layer is equipped with field plate 7 to improve breakdown voltage.Wherein, thin metal layer 8 and device
The contact area of layer silicon wafer 1 is less than P+The area in area 6, with a thickness of 800 angstroms~to 1200 angstroms, preferred material aluminium, or
Other materials, the present invention are without restriction.
N+Area 3, be formed in the form of doping device layer silicon wafer 1 for bonding surface, the N+Area 3 covers entire device
Surface of the part layer silicon wafer 1 for bonding.Wherein, the N+Area 3 and P+Area 6 it is opposite be partially covered with thick metal layers 11, the thickness metal
Layer 11 with a thickness of 0.8 micron to 1.4 microns, rest part is covered with first between device layer silicon wafer 1 and supporting layer silicon wafer 4
Silicon dioxide layer 2, N+Area 3 and P+Area 6 forms PN junction.Wherein, 11 preferred material of thick metal layers is aluminium.
Second silicon dioxide layer 5 is formed on device layer silicon wafer 1 except P+Surface outside area 6.
In the corresponding N of supporting layer silicon wafer 4+3 position of area is formed with the cavity structure 10 of inner narrow outer width, supporting layer silicon wafer 4, sky
Cavity configuration 10 and 3 expose portion of the area N+ are covered with thick metal layers 11.The cross-sectional area of cavity structure 10 be octagon or circle,
Supporting layer silicon wafer 4 is 54.74 ° with acute angle folded by the side wall of the surface opposite for linken on surface and cavity structure 10.It is empty
Cavity configuration 10 is close
Wherein, the first silicon dioxide layer 2 between supporting layer silicon wafer 4 and device layer silicon wafer 1 and supporting layer silicon wafer 4 is provided with
Window, the P of the window face device layer silicon wafer 1+Area 6, window area is preferably greater than P+Area 6.Thick metal layers 11 are convenient for detection
Device is electrically connected.
Another aspect of the present invention provides a kind of preparation method of ultra-thin silicon PIN radiation detector based on bonding substrate, Fig. 2
For the preparation method flow diagram, as shown in Fig. 2, this method comprises:
S1 forms N on the surface in 1 one surface growth regulation of device layer silicon wafer, one silicon dioxide layer 2, and by ion implanting+Area 3.
Specifically, firstly, selecting a silicon wafer as device layer silicon wafer 1, which is preferably the N-type silicon of<111>crystal orientation,
Resistivity is greater than 1000 ohmcms, with a thickness of 300 microns to 600 microns.Then, in 1 one surface heat of device layer silicon wafer
The first silica 2 that growth thickness is 800 angstroms to 10000 angstroms, and injected by phosphonium ion, form N+Area 3.Wherein, ion
Dosage is preferably 1e15/cm2To 1e16/cm2, Implantation Energy is preferably between 80keV to 120keV, in fact of the invention one
Apply in example, the N-type silicon of<111>crystal orientation with a thickness of 300 microns, for the first silica 2 with a thickness of 800 angstroms, ion dose is preferred
For 1e16/cm2, Implantation Energy 100keV.Structure after the step is as shown in Figure 3A.
S2 connects device layer silicon wafer 1 with supporting layer silicon wafer 4 by way of being bonded, so that at the first silicon dioxide layer 2
In between the two.
Specifically, firstly, selecting another silicon wafer as supporting layer silicon wafer 4, the N-type of preferably<100>crystal orientation of supporting layer silicon wafer 4
Silicon, resistivity is less than 10 ohmcms, and with a thickness of 300 microns to 600 microns, surface is exposed silicon layer.Then, pass through height
Device layer silicon wafer 1 is prepared by the method for temperature bonding (1100 DEG C) with supporting layer silicon wafer 4 is bonded substrate, and grinding elements layer silicon wafer
1 to required thickness, and thickness is 1 less than or equal to 100 microns.For ease of description, by device layer silicon wafer 1 with the table that is used to be bonded
The opposite surface in face is referred to as to be bonded the front of substrate, and surface opposite with the surface for being used to be bonded on supporting layer silicon wafer 4 is claimed
For bonding substrate the back side.In an embodiment of the present invention, the resistivity of the N-type silicon of<100>crystal orientation is 2~4 ohm lis
Rice, with a thickness of 400 microns, grinding elements layer silicon wafer 1 is to 100 microns of required thickness.Structure after the step is as shown in Figure 3B.
S3, surface growth regulation two dioxy opposite with the surface for being bonded on device layer silicon wafer 1 and supporting layer silicon wafer 4
SiClx layer 5.
Specifically, para-linkage substrate makees conventional cleaning, in thermally grown one layer of second dioxy of front and back of bonding substrate
SiClx layer 5, second silicon dioxide layer 5 with a thickness of 800 angstroms to 1200 angstroms.In an embodiment of the present invention, the second titanium dioxide
Silicon layer 5 with a thickness of 1000 angstroms.
S4, the photoetching front detection window figure in the second silicon dioxide layer 5 of device layer silicon wafer 1, and detected in front
P is formed on 1 surface of device layer silicon wafer by ion implanting form at graph window+Area 6.
Specifically, in the positive photoetching detection window figure of bonding substrate, the front detection window figure is preferably circular,
It is preferred that carrying out boron ion injection in front, the area P+ 6 is formed, injection exposure mask is made using high temperature resistant photoresist, ion implantation dosage is excellent
It is selected as 1e14/cm2To 1e16/cm2, Implantation Energy is preferably 30keV to 50keV.Photoresist is removed after ion implanting, so
Short annealing afterwards, annealing temperature are preferably 850 DEG C to 1050 DEG C, and annealing time is preferably 30s to 60s.Implement in the present invention one
In example, ion implantation dosage is 1e15/cm2, Implantation Energy 40keV, annealing temperature is 950 DEG C, annealing time 40s.
Structure after the step is as shown in Figure 3 C.
S5, the photoetching Metal And Silicon contact window figure in the second silicon dioxide layer 5 of device layer silicon wafer 1, removal metal/
The second silicon dioxide layer 5 in silicon contact window figure, wherein the Metal And Silicon contact window centre of figure and front detecting window
The center of mouth figure is overlapped, and Metal And Silicon contact window figure is preferably less than the area P+ injection window (i.e. front detection window) figure
Shape, the hydrofluoric acid buffer solution corrosion of use, to remove the second silicon dioxide layer 5 in Metal And Silicon contact window figure.It should
Structure after step is as shown in Figure 3D.
S6, in P+Corresponding 1 surface of device layer silicon wafer in area 6 forms the thin metal layer 8 with field plate structure 7.
Specifically, para-linkage substrate carries out conventional cleaning, floats removing natural oxidizing layer, in one Bao Jin of front sputtering of silicon chip
Belong to layer 8 (preferably aluminium), photoetching, corrosion are carried out to thin metal layer 8, form field plate structure 7.Wherein, the thickness of the thin metal layer 8
Preferably 800 angstroms to 1200 angstroms.In an embodiment of the present invention, thin metal layer 8 with a thickness of 1000 angstroms, carried out using phosphoric acid rotten
Erosion is to form field plate structure 7.Structure after the step is as shown in FIGURE 3 E.
S7, the surface deposited silicon nitride layer opposite with the surface for being bonded on device layer silicon wafer 1 and supporting layer silicon wafer 4
9。
Specifically, para-linkage substrate carries out conventional cleaning, using low-pressure chemical vapour deposition technique (Low Pressure
Chemical Vapor Deposition, LPCVD) in front and back one layer of silicon nitride layer 9 of deposition of silicon chip, the nitridation
The thickness of silicon layer 9 is preferably 800 angstroms to 2000 angstroms.In an embodiment of the present invention, silicon nitride layer 9 with a thickness of 1000 angstroms.It should
Structure after step is as illustrated in Figure 3 F.
S8, the photoetching back side detection window figure on the silicon nitride layer 9 on supporting layer silicon wafer 4 remove back side detection window
Silicon nitride layer 9 and the second silicon dioxide layer 5 in figure, exposure supporting layer silicon wafer 4.
Specifically, photoetching back side detection window figure, first dry etching figure window on bonding substrate back silicon nitride layer 9
Silicon nitride layer 9 of the thickness within the scope of 800 angstroms to 2000 angstroms in mouthful, then with thickness in hydrofluoric acid buffer solution etch pattern window
The second silicon dioxide layer 5 in the range of 800 angstroms to 1200 angstroms is spent, the surface of supporting layer silicon wafer 4 is exposed.Wherein the back side is visited
Survey graph window is preferably circular or octagon, back side detection window centre of figure and the center of front detection window figure are heavy
It closes.In an embodiment of the present invention, the diameter of back side detection window figure is 12 millimeters.Structure such as Fig. 3 G institute after the step
Show.
S9 removes the supporting layer silicon wafer 4 in back side detection window figure, the cavity structure 10 of narrow outer width in formation, exposure
First silicon dioxide layer 2.
Specifically, corrode the supporting layer silicon wafer 4 exposed in the graphical window of the back side, anisotropic etchant used such as four
Ammonium hydroxide (TMAH) and potassium hydroxide (KOH), the present invention is preferred
Using TMAH corrosive liquid wet etching supporting layer silicon wafer 4, corrosion is to exposing the first silicon dioxide layer 2.The back side
Detection window is opposite with the center of front detection window, and back side detection window is greater than front detection window.The present invention is excellent
Select thickness in 800 angstroms to 1200 angstroms of the second silicon dioxide layer 5 and thickness in two layers of silicon nitride 9 of 800 angstroms to 2000 angstroms corrosion
Passivation layer protects the region other than rear window figure.The condition of TMAH corrosion silicon is: corrosive liquid concentration is preferably 10wt%
To the TMAH of 25wt%, corrosion temperature is preferably 80 DEG C to 95 DEG C, using heating water bath mode.In an embodiment of the present invention,
Using TMAH corrosive liquid, concentration 20wt%, corrosion temperature is 90 DEG C.Structure after the step is as shown in figure 3h.
S10, the silicon nitride layer 9 on removal devices layer silicon wafer 1, the second silicon dioxide layer 5 on supporting layer silicon wafer 4 and nitridation
First silicon dioxide layer 2 of silicon layer 9 and cavity structure 10.
Specifically, bonding substrate is etched away using the method for reactive ion etching (Reactive Ion Etching, RIE)
The silicon nitride layer 9 in front and the back side stops corrosion the second silicon dioxide layer 5 and cavity knot using the buffered hydrofluoric acid corrosion back side
First silicon dioxide layer 2 in structure 10.Structure after the step is as shown in fig. 31.
S11, on bonding substrate back (in supporting layer silicon wafer 4 surface and cavity structure 10 opposite with for bonding surface)
Thick metal layers 11 are sputtered, which is aluminium, and thickness is preferably 0.8 micron to 1.4 microns.In the present invention one
In embodiment, thick metal layers 11 with a thickness of 1 micron.Structure after the step is as shown in figure 3j.
S12 carries out alloy treatment, and metal and silicon is made to form Ohmic contact.
Specifically, alloy treatment carries out under the atmosphere in nitrogen, hydrogen, and alloy temperature is in 400 DEG C to 500 DEG C ranges
Interior, the alloy time is between 30 minutes to 60 minutes.In an embodiment of the present invention, alloy temperature is 430 DEG C, and the alloy time is
30 minutes.
In the above preparation method, once process procedure is particularly critical:
One, initial silicon wafer determine the thickness of detector, the planarization of upper and lower surface and mechanical performance and also can
The leakage current of subsequent corrosion technique and detector is influenced, so properties of the preparation of bonding substrate to detector
Suffer from direct influence.Therefore, the embodiment of the present invention preferably uses surface oxidation to have high resistant<111>crystal orientation N of silica
Type device layer silicon wafer 1 and low-resistance<100>crystal orientation N-type supporting layer silicon wafer 4 carry out high temperature and are bonded to obtain initial bonding substrate.High resistant <
The device silicon layer of 111 > crystal orientation advantageously reduces leakage current and carries out that stronger signal can be obtained when particle detection, is that radiation is visited
The common silicon wafer crystal orientation of device is surveyed, and the supporting layer of low-resistance<100>crystal orientation is then conducive to the completion of back side TMAH etching process, and
Manufacturing cost can be reduced using low-resistance silicon.
Secondly, the preferred TMAH corrosive liquid of the embodiment of the present invention, TMAH wet etching silicon is anisotropic etch, for < 100
The silicon wafer of>crystal orientation, bottom surface<100>face and side wall<111>face are at 54.74 ° of angles after corrosion, rather than 90 ° after dry etching
Right angle, therefore with TMAH wet etching<100>crystal orientation supporting layer silicon wafer 4 than there is better mechanical performance with dry etching.It is right
Bonding substrate in the present invention, profile pattern are not influenced by TMAH wet etching, only be initially bonded the device of substrate
The planarization of part layer silicon wafer 1 is related, it is possible to improve using the TMAH corrosive liquid of higher concentration, using more high corrosion temperature
Corrosion rate reduces the TMAH etching process time.The dilution of corrosive liquid in corrosion process is considered simultaneously and is being corroded
The Pyramid being likely to form in journey causes to be difficult to continue to corrode, and confirms through test of many times, arrives in corrosive liquid concentration 5wt%
25wt%, when corrosion temperature is 80 DEG C to 95 DEG C, especially corrosive liquid concentration 20wt% can guarantee when temperature is 90 DEG C
Etching process shortens the etching process time on the basis of completing.
Third, forming N in 1 back side elder generation ion implanting of device layer silicon wafer+The conjunction of the laggard line unit in area 3 is that the embodiment of the present invention is ultra-thin
The critical process of detector manufacture.It is not necessarily to litho pattern at the device layer back side, can directly be carried out in entire silicon chip surface after oxidation
Ion implanting reduces lithography step, eliminates and injects after supporting layer silicon wafer aperture to N+The limitation of 3 area of area, certain
N is eliminated in degree+Adulterate the leakage current and breakdown risk of area edge.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (10)
1. a kind of silicon PIN radiation detector characterized by comprising
Device layer silicon wafer (1) and supporting layer silicon wafer (4), are connected by way of bonding between the two, are formed between the two
One silicon dioxide layer (2)；
N+Area (3), be formed in the device layer silicon wafer (1) for bonding surface；
P+Area (6) is formed in surface opposite with the surface for being bonded on the device layer silicon wafer (1), the P+Area (6)
On be covered with thin metal layer (8), thin metal layer (8) edge be equipped with field plate (7)；
Second silicon dioxide layer (5) is formed on the device layer silicon wafer (1) except the P+The surface of area (6) outside；
The corresponding N of the supporting layer silicon wafer (4)+The position in area (3) is formed with the cavity structure (10) of inner narrow outer width, the branch
Support layer silicon wafer (4) and cavity structure (10) surface is covered with thick metal layers (11).
2. silicon PIN radiation detector according to claim 1, which is characterized in that the device layer silicon wafer (1) is<111>
The N-type silicon of crystal orientation, resistivity are greater than 1000 ohmcms, and thickness is less than or equal to 100 microns；The supporting layer silicon wafer (4)
For the N-type silicon of<100>crystal orientation, resistivity is less than 10 ohmcms, with a thickness of 300 microns~600 microns.
3. silicon PIN radiation detector according to claim 1, which is characterized in that the thin metal layer (8) and the device
The contact area of layer silicon wafer (1) is less than the P+The area in area (6)；The N+Area's (3) area and the device layer silicon wafer (1) are used
Area equation in the surface of bonding.
4. silicon PIN radiation detector according to claim 1, which is characterized in that the thin metal layer (8) with a thickness of
800 angstroms~to 1200 angstroms；The thickness of the thick metal layers (11) is in 0.8 micron to 1.4 micron ranges.
5. silicon PIN radiation detector according to claim 1, which is characterized in that the cross section of the cavity structure (10)
Product is octagon or circle, the surface opposite with the surface for being bonded and the cavity knot on the supporting layer silicon wafer (4)
Acute angle folded by the side wall of structure (10) is 54.74 °.
6. a kind of preparation method of silicon PIN radiation detector characterized by comprising
S1 forms N on the surface in one silicon dioxide layer (2) of (1) one surface growth regulation of device layer silicon wafer, and by ion implanting+
Area (3)；
S2 connects the device layer silicon wafer (1) with supporting layer silicon wafer (4), first silica by way of being bonded
Layer (2) is between the two；
S3, the surface growth regulation two opposite with the surface for being bonded on the device layer silicon wafer (1) and supporting layer silicon wafer (4)
Silicon dioxide layer (5)；
S4, the photoetching front detection window figure on second silicon dioxide layer (5) of the device layer silicon wafer (1), and
P is formed on device layer silicon wafer (1) surface by ion implanting form at the front detection window figure+Area (6)；
S5, the photoetching Metal And Silicon contact window figure on second silicon dioxide layer (5) of the device layer silicon wafer (1), goes
Except second silicon dioxide layer (5) in the Metal And Silicon contact window figure；
S6, in the P+Corresponding device layer silicon wafer (1) surface in area (6) forms the thin metal layer with field plate structure (7)
(8)；
S7, the surface cvd nitride opposite with the surface for being bonded on the device layer silicon wafer (1) and supporting layer silicon wafer (4)
Silicon layer (9)；
S8, the photoetching back side detection window figure on the silicon nitride layer (9) on the supporting layer silicon wafer (4), described in removal
The silicon nitride layer (9) and second silicon dioxide layer (5) in the detection window figure of the back side, the exposure supporting layer silicon wafer
(4)；
S9 removes the supporting layer silicon wafer (4) in the back side detection window figure, the cavity structure of narrow outer width in formation
(10), exposure first silicon dioxide layer (2)；
S10 removes the silicon nitride layer (9) on the device layer silicon wafer (1), the second titanium dioxide on the supporting layer silicon wafer (4)
The first silicon dioxide layer (2) of silicon layer (5) and silicon nitride layer (9) and the cavity structure (10)；
S11, sputtering is thick in the supporting layer silicon wafer (4) surface and the cavity structure (10) opposite with for bonding surface
Metal layer (11)；
S12 carries out alloy treatment, and metal and silicon is made to form Ohmic contact.
7. the preparation method of silicon PIN radiation detector according to claim 6, which is characterized in that the device layer silicon wafer
It (1) is the N-type silicon of<111>crystal orientation, resistivity is greater than 1000 ohmcms, and thickness is less than 100 microns；The supporting layer silicon
Piece (4) is the N-type silicon of<100>crystal orientation, and resistivity is less than 10 ohmcms, with a thickness of 300 microns~600 microns.
8. the preparation method of silicon PIN radiation detector according to claim 6, which is characterized in that second titanium dioxide
Silicon layer (5) with a thickness of 800 angstroms~1200 angstroms；The silicon nitride layer (9) with a thickness of 800 angstroms~2000 angstroms.
9. the preparation method of silicon PIN radiation detector according to claim 6, which is characterized in that it is injected by phosphonium ion,
Form N+Area (3), is injected by boron ion, forms P+Area (6).
10. the preparation method of silicon PIN radiation detector according to claim 6, which is characterized in that in aforesaid operations S9
In, the supporting layer silicon wafer (4) in the back side detection window, narrow outer width in formation are corroded using tetramethylammonium hydroxide
Cavity structure (10), the concentration of the tetramethylammonium hydroxide corrosive liquid are 10wt% to 25wt%, and corrosion temperature is 80 DEG C and arrives
95℃。
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| CN101286536A (en) * | 2008-05-06 | 2008-10-15 | 北京大学 | Ultrathin silicon based particle detector and preparing method thereof |
| CN102496632A (en) * | 2011-12-29 | 2012-06-13 | 北京大学 | Ultra-thin silicon PIN high energy particle detector based on bonding substrate and manufacturing method thereof |
| CN103515467A (en) * | 2012-06-26 | 2014-01-15 | 北京大学 | Delta E-E nuclear radiation detector based on substrate bonding and preparation method thereof |
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| CN102496632A (en) * | 2011-12-29 | 2012-06-13 | 北京大学 | Ultra-thin silicon PIN high energy particle detector based on bonding substrate and manufacturing method thereof |
| CN103515467A (en) * | 2012-06-26 | 2014-01-15 | 北京大学 | Delta E-E nuclear radiation detector based on substrate bonding and preparation method thereof |
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| CN113871509A (en) * | 2021-09-16 | 2021-12-31 | 北京大学 | Double-groove type narrow-edge high-voltage-resistant silicon PIN radiation detector and preparation thereof |
| CN113871509B (en) * | 2021-09-16 | 2024-03-15 | 北京大学 | Double-groove type narrow-edge high-voltage-resistant silicon PIN radiation detector and preparation thereof |
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