CN109727933A - A kind of method for packaging semiconductor and semiconductor packing device - Google Patents
A kind of method for packaging semiconductor and semiconductor packing device Download PDFInfo
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- CN109727933A CN109727933A CN201811583338.9A CN201811583338A CN109727933A CN 109727933 A CN109727933 A CN 109727933A CN 201811583338 A CN201811583338 A CN 201811583338A CN 109727933 A CN109727933 A CN 109727933A
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- base board
- ground pad
- board unit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
This application discloses a kind of method for packaging semiconductor and semiconductor packing devices, the method for packaging semiconductor includes: offer base board unit, the base board unit includes the first surface and second surface being disposed opposite to each other and the first side adjacent with the first surface and the second surface, the first surface is provided with ground pad, and the second side of the ground pad is exposed from the first side；The second surface is provided with chip and plastic packaging layer, and the plastic packaging layer covers the chip；The second side in the outer surface of the plastic packaging layer, the first side of the base board unit and the ground pad forms electro-magnetic screen layer.By the above-mentioned means, the application can reduce cost of manufacture and improve the contact area of electro-magnetic screen layer and earth-return circuit.
Description
Technical field
This application involves technical field of semiconductors, more particularly to a kind of method for packaging semiconductor and semiconductor packages device
Part.
Background technique
As the signal frequencies that the arithmetic speed of electronic component is getting faster or information is transmitted are higher and higher, semiconductor
Chip in packaging is easy mutually to generate electromagnetic interference with other internal or external electronic components, such as crosstalk, transmission damage
Consumption, signal reflection etc., this meeting so that the operational effectiveness of chip is cut down, so in semiconductor packing device to chip into
The protection of row electromagnetic interference is particularly important.
It is existing to chip carry out electromagnetic interference shielding mode include: be pre-formed inside substrate ground plane and with
The ground path of ground plane connection, ground path extend to the side of upper surface of base plate；It fixes, and is formed by chip and substrate
After plastic packaging layer, electro-magnetic screen layer is formed in plastic packaging layer outer surface, and the electro-magnetic screen layer is connected to the ground path, it will be electric
Magnetic wave or electrostatic guide to ground plane are discharged, and are influenced with protecting chip not by electromagnetic interference.
Present inventor has found that substrate needs additional to be grounded in the above method in chronic study procedure
Road, cost of manufacture are higher；And the face area of ground path is smaller, the contact with electro-magnetic screen layer is point-like contacts, is easy
It causes electro-magnetic screen layer and ground path poor contact and electromagnetic shielding is caused to fail.
Summary of the invention
The application, can mainly solving the technical problems that provide a kind of method for packaging semiconductor and semiconductor packing device
It reduces cost of manufacture and improves the contact area of electro-magnetic screen layer and earth-return circuit.
In order to solve the above technical problems, the technical solution that the application uses is: a kind of method for packaging semiconductor is provided,
The method for packaging semiconductor includes: offer base board unit, and the base board unit includes the first surface being disposed opposite to each other and second
Surface and the first side adjacent with the first surface and the second surface, the first surface are provided with ground connection weldering
The second side of disk, the ground pad is exposed from the first side；The second surface is provided with chip and plastic packaging layer,
And the plastic packaging layer covers the chip；The outer surface of the plastic packaging layer, the first side of the base board unit and
The second side of the ground pad forms electro-magnetic screen layer.
Wherein, the offer base board unit includes: offer substrate, define on the substrate multiple base board units with
And the Cutting Road between multiple base board units, the base board unit include the first surface being disposed opposite to each other and institute
Second surface is stated, the first surface is provided with ground pad；It is set respectively in the second surface of multiple base board units
The chip is set, and the chip is electrically connected with the base board unit；In the second surface of multiple base board units
The plastic packaging layer is formed, and the plastic packaging layer covers the chip；The substrate is cut along the Cutting Road, so that the base
The first side of plate unit is exposed, and the second side of the ground pad is exposed from the first side.
Wherein, the substrate that provides includes: to etch multiple ground connection in the first surface of the base board unit
Pad；Continue to etch the ground pad, to form notch, the ground pad in the second side of the ground pad
Including the third surface and fourth surface adjacent with the second side, relatively described 4th surface in the third surface is close to institute
Second surface is stated, the notch extends from the 4th surface to the third surface.
Wherein, described to continue to etch the ground pad, to form notch in the second side of the ground pad
Include: to continue to etch the ground pad, at least one stage portion is formed with the second side in the ground pad.
Wherein, described in the outer surface of the plastic packaging layer, the first side of the base board unit and the ground connection
The second side of pad forms electro-magnetic screen layer, comprising: using any described in spray coating method, galvanoplastic, sputtering method
The outer surface of plastic packaging layer, the first side of the base board unit, the second side of the ground pad, the ground connection
The electro-magnetic screen layer is formed in the notch of pad.
Wherein, described in the outer surface of the plastic packaging layer, the first side of the base board unit and the ground connection
The second side of pad is formed before electro-magnetic screen layer, method for packaging semiconductor provided herein further include: removal
And clean the outer surface of the plastic packaging layer, the first side of the base board unit, described second side of the ground pad
The medium in face, so that the outer surface, the first side, the second side are smooth.
In order to solve the above technical problems, another technical solution that the application uses is: providing a kind of semiconductor packages device
Part, the semiconductor packing device include: base board unit, the first surface and second surface including being disposed opposite to each other and with institute
First surface and the adjacent first side of the second surface are stated, the first surface is provided with ground pad, the ground connection weldering
Disk includes the second side exposed from the first side；Chip, positioned at the second surface of the base board unit, and with institute
State base board unit electrical connection；Plastic packaging layer covers the second surface and the chip of the base board unit；Electromagnetic shielding
Layer covers described the of the outer surface of the plastic packaging layer, the first side of the base board unit and the ground pad
Two side faces.
Wherein, the second side of the ground pad includes notch, and the ground pad includes and described second side
Face adjacent third surface and the 4th surface, relatively described 4th surface in the third surface are described close to the second surface
Notch extends from the 4th surface to the third surface, and the electro-magnetic screen layer extends into the notch.
Wherein, the notch forms at least one stage portion in the second side.
Wherein, the material of the electro-magnetic screen layer is metal, the metal include aluminium, copper, chromium, gold, silver, nickel, in tin extremely
Few one kind.
The beneficial effect of the application is: being in contrast to the prior art, method for packaging semiconductor provided herein
Middle base board unit includes the first surface and second surface being disposed opposite to each other and adjacent with first surface and the second surface
First side, first surface are provided with ground pad, and the second side of ground pad is exposed from first side；Electro-magnetic screen layer
It is connect with the second side of ground pad, electromagnetic wave or electrostatic is guided, chip is protected not influenced by electromagnetic interference；This Shen
Ground path, simple process please be not necessarily formed in provided method for packaging semiconductor, cost of manufacture and time reduce；And it connects
The area for the second side that ground pad exposes is greater than the face area of traditional ground path, electro-magnetic screen layer and ground pad it
Between binding force enhancing, effectively reduce electro-magnetic screen layer caused because of poor contact electromagnetic shielding fail probability.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the flow diagram of one embodiment of the application method for packaging semiconductor；
Fig. 2 is the flow diagram of mono- embodiment of step S101 in Fig. 1；
Fig. 3 is the structural schematic diagram of mono- embodiment of step S201- step S204 in Fig. 2；
Fig. 4 is the schematic top plan view of one embodiment of substrate in Fig. 3 a；
Fig. 5 is the structural schematic diagram of another embodiment of step S202 in Fig. 2；
Fig. 6 is the structural schematic diagram of one embodiment of the application semiconductor packing device；
Fig. 7 is the structural schematic diagram of another embodiment of the application semiconductor packing device；
Fig. 8 is the structural schematic diagram of another embodiment of the application semiconductor packing device.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
Referring to Fig. 1, Fig. 1 is the flow diagram of one embodiment of the application method for packaging semiconductor, the semiconductor package
Dress method includes:
S101: providing base board unit, and base board unit includes first surface and second surface being disposed opposite to each other and with first
Surface and the adjacent first side of second surface, first surface are provided with ground pad, and the second side of ground pad is from first
Expose in side；Second surface is provided with chip and plastic packaging layer, and plastic packaging layer covers chip.
Specifically, in an application scenarios, Fig. 2-Fig. 3 is please referred to, Fig. 2 is mono- embodiment of step S101 in Fig. 1
Flow diagram, Fig. 3 are the structural schematic diagram of mono- embodiment of step S201- step S204 in Fig. 2, and above-mentioned steps S101 is specific
Include:
S201: providing substrate 10, defines multiple base board units 100 on the substrate 10 and is located at multiple base board units 100
Between Cutting Road 102, base board unit 100 includes the first surface 104 and second surface 106 that are disposed opposite to each other, first surface 104
It is provided with ground pad 108.
Specifically, as illustrated in figures 3 a and 4, Fig. 4 is the schematic top plan view of one embodiment of substrate in Fig. 3 a, in this implementation
In example, substrate 10 can be Background Grid array packages LGA substrate etc..Base board unit 100 includes four sides, and every side can be set one and connect
Ground pad 108 (as shown in Figure 4), projection of the ground pad 108 on the first surface 104 of substrate 10 can be rectangular, rectangular
Shape or other arbitrary shapes, for connecting with earth-return circuit, earth-return circuit can be located inside substrate 10 ground pad 108,
It may be alternatively located at outside substrate 10；Certainly, in other embodiments, the set-up mode of ground pad 108 can also on base board unit 100
It may also comprise other pads, the application is not construed as limiting this and other than ground pad 108 for other.
In general, its first surface 104 is provided with metal layer when the purchase of substrate 10 comes, need to be etched to be formed
Ground pad 108, providing substrate 10 in one embodiment, in above-mentioned steps S201 includes: multiple substrates in substrate 10
The first surface 104 of unit 100 etches multiple ground pads 108.It is etched, and is etching for example, can use exposure mask
Formed ground pad 108 while also it is etchable go out other pads and bottom circuit etc..
In another embodiment, it to further strengthen the binding force between electro-magnetic screen layer and ground pad 108, asks
Refering to Fig. 3 b, in above-mentioned steps S201 after forming ground pad 108 further include: continue to etch ground pad 108, to connect
The second side 1080 of ground pad 108 forms notch 1082, and in the present embodiment, the second side 1080 of ground pad 108 is
The neighbouring side with Cutting Road 102.For example, can use another exposure mask for ground pad 108 close to the part of Cutting Road 102
It etches away, and then forms notch 1082 in the second side of ground pad 108 1080.Wherein, ground pad 108 includes and second
Side 1080 adjacent third surface 1084 and the 4th surface 1086,1084 opposite fourth surface 1086 of third surface is close to second
Surface 106, notch 1082 extend from the 4th surface 1086 to third surface 1084.The formation of above-mentioned notch 1082 is in addition to that can mention
Outside binding force between high later period electro-magnetic screen layer and ground pad 108, generation when can also reduce later period cutting Cutting Road 102
The risk of burr.
In an application scenarios, as shown in Figure 3b, notch 1082 can be stage portion, above-mentioned to continue to etch ground pad
108, it include: to continue to etch ground pad 108 to form notch 1082 in the second side 1080 of ground pad 108, to connect
The second side 1080 of ground pad 108 forms at least one stage portion, at least one stage portion is from third surface 1084 to the 4th
Surface 1086 extends.Certainly, in other application scenarios, the shape of notch 1082 can also be other, for example, trapezoidal etc..
S202: being respectively set chip 12 in the second surface 106 of multiple base board units 100, and by chip 12 and substrate list
Member 100 is electrically connected.
Specifically, as shown in Figure 3c, chip 12 includes front 120 and the back side 122, and chip front side 120 is provided with pad (figure
Do not show).When chip 12 is connect using the form of formal dress with base board unit 100, above-mentioned steps S202 is specifically included: by chip 12
The back side 122 be placed in the second surface 106 of base board unit 100, and be subjected to displacement to reduce chip 12 with base board unit 100
Probability, the glue film of double-sided adhesive class can be also set between the back side of chip 12 122 and base board unit 100, with preliminary fixed core
The position of piece 12 and base board unit 100；Chip 12 and corresponding base board unit 100 are electrically connected using conducting wire 14.Chip 12 can
Base board unit 100 is transmitted a signal to by conducting wire 14, or, chip 12 receives the letter that base board unit 100 transmits by conducting wire 14
Number.Wherein, the material of conducting wire 14 can close for gold, aluminium, copper and copper-iron series, copper-nickel-silicon system, copper-chromium system, copper-ni-sn system
Any one or more of composition of gold only needs the conducting wire 14 to have conducting function and preferable mechanical strength, resistance to stress pine
Relaxation characteristic.
Certainly, in other embodiments, as shown in figure 5, the structure that Fig. 5 is another embodiment of step S202 in Fig. 2 is shown
It is intended to.When the form that upside-down mounting can also be used in chip 12a is connect with base board unit 100a, before above-mentioned steps S202, the application
Provided method further include: metal salient point/metal pillar is formed in the pad (not shown) of the positive 120a of chip 12a
124a, metal salient point/metal pillar 124a and the corresponding position of base board unit 100a are electrically connected.Chip 12a can pass through gold
Belong to salient point/metal pillar 124a and transmit a signal to base board unit 100a, or, chip 12a passes through metal salient point/metal pillar
124a receives the signal of base board unit 100a transmission.
S203: plastic packaging layer 16 is formed in the second surface 106 of multiple base board units 100, and plastic packaging layer 16 covers chip 12.
Specifically, as shown in Figure 3d, the material of plastic packaging layer 16 can be insulating materials, such as epoxy resin etc. forms modeling
The method of sealing 16 can be to be any in the prior art, and this will not be detailed here.
S204: along 102 cutting substrate 10 of Cutting Road, so that the first side 101 of base board unit 100 is exposed, ground connection weldering
The second side 1080 of disk 108 is exposed from first side 101.
Specifically, as shown in Figure 3 e, it can repeatedly be cut once or along Cutting Road 102 using cutter, so that
The second side 1080 for obtaining ground pad 108 is exposed.In the present embodiment, the Edge Distance ground pad 108 of Cutting Road 102
Second side 1080 may be there are also a distance, if only cutting off 102 part of Cutting Road, second side 1080 can not be exposed；
Therefore, secondary cut can be carried out at this time, so that second side 1080 is exposed；Alternatively, can use wider than Cutting Road 102
Cutter are cut, so that primary cutting can be such that second side 1080 exposes.
Certainly, in other embodiments, the mode for realizing above-mentioned steps S101 can also be other, and the application does not limit this
It is fixed.For example, single base board unit 100 first can be cut into substrate 10, subsequent place then is carried out to single base board unit 100 again
Reason.
S102: the of the outer surface of plastic packaging layer 16, the first side 101 of base board unit 100 and ground pad 108
Two side faces 1080 form electro-magnetic screen layer 18.
Specifically, as shown in fig. 6, Fig. 6 is the structural schematic diagram of one embodiment of the application semiconductor packing device.Upper
Before stating step S102, method for packaging semiconductor provided herein further include: remove and clean plastic packaging layer 16 outer surface,
The medium of the first side 101 of base board unit 100, the second side 1080 of ground pad 108, so that outer surface, the first side
Face 101, second side 1080 are smooth.For example, can use the modes such as laser or plasma removes extra medium, so as to
With enhance the outer surface of electro-magnetic screen layer 18 and plastic packaging layer 16, the first side 101 of base board unit 100, ground pad 108
The binding force of two side faces 1080.
In the present embodiment, the material of electro-magnetic screen layer 18 can be metal, for example, aluminium, copper, gold, silver, nickel, tin, solder
At least one of, the mode for forming above-mentioned electro-magnetic screen layer 18 can be spray coating method, galvanoplastic, any in sputtering method.
In one embodiment, as shown in fig. 7, Fig. 7 is the knot of another embodiment of the application semiconductor packing device
Structure schematic diagram.When the second side 1080b of ground pad 108b forms jagged (not indicating), above-mentioned steps S102 is specifically wrapped
It includes: utilizing the outer surface in plastic packaging layer 16b any in spray coating method, galvanoplastic, sputtering method, the first side of base board unit 100b
The interior formation electro-magnetic screen layer of notch (not indicating) of 101b, the second side 1080b of ground pad 108b, ground pad 108b
18b。
Semiconductor packing device provided herein is described further from configuration aspects below.Referring to figure
6, semiconductor packing device provided herein includes:
Base board unit 100, including the first surface 104 and second surface 106 that are disposed opposite to each other and with first surface 104
The first side 101 adjacent with second surface 106, first surface 104 are provided with ground pad 108, ground pad 108 include from
The second side 1080 that first side 101 is exposed.
Chip 12 is electrically connected positioned at the second surface 106 of base board unit 100, and with base board unit 100.In the present embodiment
In, as shown in fig. 6, chip 12 includes that front 120 and the back side 122, the pad (not shown) in the front 120 of chip 12 pass through conducting wire
14 are electrically connected with base board unit 100.
Plastic packaging layer 16 covers the second surface 106 and chip 12 of base board unit 100.The material of plastic packaging layer 16 can be
Insulating materials, for example, epoxy resin etc..
Electro-magnetic screen layer 18 covers the outer surface of plastic packaging layer 16, the first side 101 of base board unit 100 and ground connection weldering
The second side 1080 of disk 108.In the present embodiment, the material of electro-magnetic screen layer 18 be metal, metal include aluminium, copper, chromium,
At least one of gold, silver, nickel, tin.In addition, the surface that ground pad 108 is not electromagnetically shielded by the grounding wire the covering of layer 18 can in the present embodiment
To be electrically connected with external circuit.
In the present embodiment, the second side 1080 of ground pad 108 include notch 1082, ground pad 108 include with
Second side 1080 adjacent third surface 1084 and the 4th surface 1086,1084 opposite fourth surface 1086 of third surface are close
Second surface 106, notch 1082 extend from the 4th surface 1086 to third surface 1084.Notch 1082 can be in second side
1080 form at least one stage portion.In the present embodiment, electro-magnetic screen layer 18 can be covered only to the second of ground pad 108
Side 1080.
In another embodiment, as shown in fig. 7, electro-magnetic screen layer 18b also may be further extended (does not indicate) into notch
It is interior.The electro-magnetic screen layer 18b extended into notch is equivalent to hook portion, can not only increase electro-magnetic screen layer 18b and ground pad
The contact area of 108b can also reduce the probability for making electro-magnetic screen layer 18b and ground pad 108b fall off because of applied external force.
In yet another embodiment, referring to Fig. 8, Fig. 8 is the knot of another embodiment of the application semiconductor packing device
The difference of structure schematic diagram, the semiconductor packing device and above-described embodiment is that chip 12a and base board unit 100a use upside-down mounting
Mode be electrically connected.Specifically, the positive 120a of chip 12a is provided with metal salient point/metal pillar 124a, chip 12a's
Metal salient point/metal pillar 124a is electrically connected with base board unit 100a.
To sum up, being in contrast to the prior art, base board unit in method for packaging semiconductor provided herein
Including the first surface and second surface and the first side adjacent with first surface and second surface being disposed opposite to each other, first
Surface is provided with ground pad, and the second side of ground pad is exposed from first side；Electro-magnetic screen layer and ground pad
Second side connection, electromagnetic wave or electrostatic are guided, influenced with protecting chip not by electromagnetic interference；Provided herein
Ground path, simple process are not necessarily formed in method for packaging semiconductor, cost of manufacture and time reduce；And ground pad exposes
Second side area be greater than traditional ground path face area, the binding force between electro-magnetic screen layer and ground pad
Enhancing effectively reduces the probability that electro-magnetic screen layer causes electromagnetic shielding to fail because of poor contact.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of method for packaging semiconductor, which is characterized in that the method for packaging semiconductor includes:
There is provided base board unit, the base board unit includes first surface and second surface being disposed opposite to each other and with described first
Surface and the adjacent first side of the second surface, the first surface are provided with ground pad, and the of the ground pad
Two side faces expose from the first side；The second surface is provided with chip and plastic packaging layer, and the plastic packaging layer covers institute
State chip；
Described the of the outer surface of the plastic packaging layer, the first side of the base board unit and the ground pad
Two side faces form electro-magnetic screen layer.
2. method for packaging semiconductor according to claim 1, which is characterized in that the offer base board unit includes:
Substrate is provided, defines multiple base board units and cutting between multiple base board units on the substrate
It cuts, the base board unit includes the first surface and the second surface being disposed opposite to each other, and the first surface is provided with
Ground pad；
The chip is respectively set in the second surface of multiple base board units, and by the chip and the substrate list
Member electrical connection；
The plastic packaging layer is formed in the second surface of multiple base board units, and the plastic packaging layer covers the chip；
The substrate is cut along the Cutting Road, so that the first side of the base board unit is exposed, the ground connection weldering
The second side of disk is exposed from the first side.
3. method for packaging semiconductor according to claim 2, which is characterized in that the offer substrate includes:
Multiple ground pads are etched in the first surface of the base board unit；
Continue to etch the ground pad, to form notch, the ground pad in the second side of the ground pad
Including the third surface and fourth surface adjacent with the second side, relatively described 4th surface in the third surface is close to institute
Second surface is stated, the notch extends from the 4th surface to the third surface.
4. method for packaging semiconductor according to claim 3, which is characterized in that it is described to continue to etch the ground pad,
Include: to form notch in the second side of the ground pad
Continue to etch the ground pad, at least one stage portion is formed with the second side in the ground pad.
5. method for packaging semiconductor according to claim 3 or 4, which is characterized in that the appearance in the plastic packaging layer
The second side in face, the first side of the base board unit and the ground pad forms electro-magnetic screen layer, packet
It includes:
Using the outer surface in the plastic packaging layer any in spray coating method, galvanoplastic, sputtering method, the base board unit described
One side, the second side of the ground pad, the ground pad the notch in form the electro-magnetic screen layer.
6. method for packaging semiconductor according to claim 1, which is characterized in that the outer surface in the plastic packaging layer,
The first side of the base board unit and the second side of the ground pad are formed before electro-magnetic screen layer,
Method for packaging semiconductor provided herein further include:
Remove and clean the outer surface of the plastic packaging layer, the first side of the base board unit, the ground pad institute
The medium of second side is stated, so that the outer surface, the first side, the second side are smooth.
7. a kind of semiconductor packing device, which is characterized in that the semiconductor packing device includes:
Base board unit, including the first surface and second surface that are disposed opposite to each other and with the first surface and second table
The adjacent first side in face, the first surface are provided with ground pad, and the ground pad includes revealing from the first side
Second side out；
Chip is electrically connected positioned at the second surface of the base board unit, and with the base board unit；
Plastic packaging layer covers the second surface and the chip of the base board unit；
Electro-magnetic screen layer covers the outer surface of the plastic packaging layer, the first side of the base board unit and the ground connection
The second side of pad.
8. semiconductor packing device according to claim 7, which is characterized in that
The second side of the ground pad includes notch, and the ground pad includes adjacent with the second side
Three surfaces and the 4th surface, relatively described 4th surface in the third surface is close to the second surface, and the notch is described in
4th surface extends to the third surface, and the electro-magnetic screen layer extends into the notch.
9. semiconductor packing device according to claim 8, which is characterized in that
The notch forms at least one stage portion in the second side.
10. semiconductor packing device according to claim 7, which is characterized in that
The material of the electro-magnetic screen layer is metal, and the metal includes at least one of aluminium, copper, chromium, gold, silver, nickel, tin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN109727933B (en) | 2021-07-13 |
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