CN109727877A - A kind of method for packaging semiconductor and semiconductor packing device - Google Patents
A kind of method for packaging semiconductor and semiconductor packing device Download PDFInfo
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- CN109727877A CN109727877A CN201811565049.6A CN201811565049A CN109727877A CN 109727877 A CN109727877 A CN 109727877A CN 201811565049 A CN201811565049 A CN 201811565049A CN 109727877 A CN109727877 A CN 109727877A
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- opening
- insulating layer
- chip
- connecting part
- conducting connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
This application discloses a kind of method for packaging semiconductor and semiconductor packing device, the method for packaging semiconductor includes: to form the first insulating layer in substrate/frame first surface, and form the first opening on the first insulating layer；Conducting connecting part is formed in first opening；Second insulating layer is formed far from the side of the substrate/frame in first insulating layer, and the second opening is formed in the position that the second insulating layer corresponds to first opening, and the height of the conducting connecting part is less than the sum of the depth of first opening with second opening；The metalwork of the front setting of chip is placed in second opening, and the front of the chip is bonded with the second insulating layer, the metalwork is electrically connected with the conducting connecting part.By the above-mentioned means, the application can keep chip surface exposed without grinding chip or in chip surface setting adhesive tape.
Description
Technical field
This application involves technical field of semiconductors, more particularly to a kind of method for packaging semiconductor and semiconductor packages device
Part.
Background technique
Semiconductor packages refers to the process of the packaging body that chip, substrate/frame and plastic packaging material are formed to different shapes.It is sealing
During dress, it is necessary first to fix chip and substrate/frame first surface, then cover substrate/frame using plastic packaging material
First surface and package chip.Under normal conditions, chip needs to expose from plastic packaging material far from substrate/frame side, and
In order to realize chip exposed, the first way of use is before plastic packaging material covering, in advance in chip far from substrate/frame
Adhesive tape is arranged in side, and the later period realizes chip exposed by removal adhesive tape；The second way of use is ground after plastic packaging material molding
Mill chip is far from substrate/frame side mode to realize chip exposed.
Present inventor has found that above-mentioned first way is easy to cause plastic packaging material to spill over core in chronic study procedure
Piece surface, the above-mentioned second way are easy to cause overgrinding, and the thickness of chip is ground to excessively thin.
Summary of the invention
The application, can mainly solving the technical problems that provide a kind of method for packaging semiconductor and semiconductor packing device
Without grinding chip or adhesive tape is set in chip surface and keeps chip surface exposed.
In order to solve the above technical problems, the technical solution that the application uses is: a kind of method for packaging semiconductor is provided,
The method for packaging semiconductor includes: to form the first insulating layer in substrate/frame first surface, and in first insulating layer
It is upper to form the first opening；Conducting connecting part is formed in first opening；In first insulating layer far from the substrate/frame
The side of frame forms second insulating layer, and forms the second opening in the position that the second insulating layer corresponds to first opening,
And the height of the conducting connecting part is less than the sum of the depth of first opening with second opening；The front of chip is set
The metalwork set is placed in second opening, and the front of the chip is bonded with the second insulating layer, the metalwork
It is electrically connected with the conducting connecting part.
Wherein, described to form conducting connecting part in first opening, comprising: to be opened using electroplating technology described first
The conducting connecting part is formed in mouthful, and the height of the conducting connecting part is more than or equal to the depth of first opening.
Wherein, the method for packaging semiconductor further include: reflow treatment is carried out to the conducting connecting part, so that described
Conducting connecting part is fixed with the substrate/frame, and the conducting connecting part forms arc table far from the substrate/frame side
Face.
Wherein, the first surface in the substrate/frame forms the first insulating layer, and in first insulation
The first opening is formed on layer, comprising: form photoresist layer in the first surface of the substrate/frame；Using light shield to institute
State photoresist layer be exposed be developed to it is described first opening.
Wherein, described to form second insulating layer far from the side of the substrate/frame in first insulating layer, and in institute
State the second opening of position formation that second insulating layer corresponds to first opening, comprising: in first insulating layer far from described
Substrate/frame side forms anti-solder ink layer；The anti-solder ink layer is corroded, in correspondence first opening
Position forms second opening.
Wherein, the metalwork of the front setting by chip is placed in second opening, comprising: by the chip
The metalwork is placed in second opening, and the front of the chip is contacted with the second insulating layer, and the metal
There is the first spacing, first spacing is more than or equal to 0 between part and the conducting connecting part；Alternatively, by the institute of the chip
It states metalwork to be placed in second opening, the metalwork is contacted with the conducting connecting part, and the front of the chip
There is the second spacing with the second insulating layer, second spacing is more than or equal to 0.
Wherein, after the metalwork of the front setting by chip is placed in second opening, the method is also wrapped
It includes: briquetting is set at the back side of the chip, reflow treatment is carried out to the chip and the substrate/frame, described first absolutely
Deformation occurs under the action of the briquetting and temperature for edge layer and/or the second insulating layer, so that the chip is described
It is positive to be bonded with the second insulating layer, and the metalwork is electrically connected with the conducting connecting part.
In order to solve the above technical problems, another technical solution that the application uses is: providing a kind of semiconductor packages device
Part, the semiconductor packing device include: substrate/frame；First insulating layer, positioned at the first surface of the substrate/frame, and
First insulating layer is provided with multiple first openings；Second insulating layer is located at first insulating layer far from the substrate/frame
Frame side, and the second insulating layer corresponds to the position that described first is open and is provided with the second opening；Conducting connecting part is located at institute
It states in the first opening, and the height of the conducting connecting part is less than the sum of the depth of first opening with second opening；
Chip, including front and back, front and the second insulating layer of the chip bond, and the front of the chip is provided with gold
Belong to part, the metalwork is electrically connected with the conducting connecting part.
Wherein, the height of the conducting connecting part is more than or equal to the depth of first opening.
Wherein, first insulating layer is photoresist layer；Or, the second insulating layer is anti-solder ink layer.
The beneficial effect of the application is: being in contrast to the prior art, method for packaging semiconductor provided herein
It include: to form the first insulating layer and second insulating layer of stacking in substrate/frame first surface, the first insulating layer is provided with the
The position of one opening, corresponding first opening of second insulating layer is provided with the second opening, and conducting connecting part is formed in the first opening,
And it is non-bulging in the second opening, the metalwork of chip front side setting is placed in the second opening, and the front of chip and the second insulation
Layer bonding, metalwork are electrically connected with conducting connecting part.The first insulating layer and second insulating layer are equivalent to plastic packaging layer in the application,
It is formed in front of chip and the fixation of substrate/frame first surface, so as to realize is not necessarily to that adhesive tape is arranged at the back side of chip
Or grinding chip the back side and the purpose that exposes chip, method for packaging semiconductor provided herein is more simple, easy
Row.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the flow diagram of one embodiment of the application method for packaging semiconductor；
Fig. 2 is the structural schematic diagram of the corresponding embodiment of step S101- step S104 in Fig. 1；
Fig. 3 is the flow diagram of mono- embodiment of step S101 in Fig. 1；
Fig. 4 is the structural schematic diagram of the corresponding embodiment of step S201- step S202 in Fig. 3；
Fig. 5 is the flow diagram of mono- embodiment of step S103 in Fig. 1；
Fig. 6 is the structural schematic diagram of the corresponding embodiment of step S301- step S302 in Fig. 5；
Fig. 7 is the structural schematic diagram of the corresponding another embodiment of step S104 in Fig. 1；
Fig. 8 is the structural schematic diagram of the corresponding another embodiment of step S104 in Fig. 1；
Fig. 9 is the structural schematic diagram of one embodiment of the application semiconductor packing device.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
Fig. 1-Fig. 2 is please referred to, Fig. 1 is the flow diagram of one embodiment of the application method for packaging semiconductor, and Fig. 2 is figure
The structural schematic diagram of the corresponding embodiment of step S101- step S104, the method for packaging semiconductor include: in 1
S101: the first insulating layer 12, and the shape on the first insulating layer 12 are formed in the first surface 100 of substrate/frame 10
At the first opening 120.
Specifically, Fig. 2 a is please referred to, substrate/frame 10 can be any kind in the prior art, for example, printed circuit board
(PCB), organic substrate, inorganic substrate, glass substrate, flexible base board, copper-iron series frame, copper-nickel-silicon system frame etc..In this reality
It applies in example, the first surface 100 of substrate/frame 10 is additionally provided with multiple pins 102, and multiple pins 102 are used for and other yuan of device
Part electrical connection.
In one embodiment, the first insulating layer 12 is photoresist layer, please refers to Fig. 3-Fig. 4, and Fig. 3 is step in Fig. 1
The flow diagram of mono- embodiment of S101, Fig. 4 are the structure of the corresponding embodiment of step S201- step S202 in Fig. 3
Schematic diagram.Above-mentioned steps S101 is specifically included:
S201: photoresist layer is formed in the first surface 100 of substrate/frame 10.
Specifically, as shown in fig. 4 a, the mode that can use printing forms light in the first surface 100 of substrate/frame 10
Photoresist layer, the device utilized include web plate 14 and scraper 16；In the present embodiment, photoresist is formed in the way of printing
Layer, efficiency are higher.Certainly, in other embodiments, the mode that other coatings can also be used forms photoresist layer.
S202: photoresist layer is exposed using light shield 18 and is developed to the first opening 120.
Specifically, in one embodiment as shown in Figure 4 b, first light shield 18 can be placed on photoresist layer 12, light
Cover 18 also referred to as photomask blank etc. is previously provided with multiple third openings, is got rid of by exposure development on the light shield 18
Third is open corresponding photoresist layer or other photoresist layers for being covered by light shield 18 in addition to third opening.For example, working as photoetching
When the material of glue-line is positive photoresist (for example, o- nitrine quinones photoresist etc.), exposed development, third is open corresponding
Positive photoresist is removed, and the positive photoresist that other are covered by light shield 18 retains；When the material of photoresist layer is negativity light
When photoresist (for example, poly- cinnamate derivative photoresist etc.), exposed development, the corresponding negative photoresist of third opening retains, and
Other negative photoresists covered by light shield 18 remove.
S102: conducting connecting part 11 is formed in the first opening 120.
Specifically, as shown in Figure 2 b, it can use electroplating technology and form conducting connecting part 11 in the first opening 120, and
The height of conducting connecting part 11 is more than or equal to the depth of the first opening 120, and conducting connecting part 11 can be copper and tin silver alloy etc..Separately
Outside, in the present embodiment, before forming conducting connecting part 11, also one layer of metal layer can be sputtered in the first opening 120, so that
It obtains when subsequent plating forms conducting connecting part 11 and is easier.
In addition, in the present embodiment, to make the connection of conducting connecting part 11 and substrate/frame 10 more closely, this Shen
Please provided by method for packaging semiconductor further include: to conducting connecting part 11 carry out reflow treatment so that conducting connecting part 11
It is fixed with substrate/frame 10, and conducting connecting part 11 forms curved surfaces (as shown in Figure 2 b) far from 10 side of substrate/frame.
S103: second insulating layer 13 is formed far from the side of substrate/frame 10 in the first insulating layer 12, and in the second insulation
The position of corresponding first opening 120 of layer 13 forms the second opening 130, and the height d1 of conducting connecting part 11 is less than the first opening
120 and second opening 130 the sum of depth d2.
Specifically, as shown in Figure 2 c.In one embodiment, above-mentioned second insulating layer 13 can be and the first insulating layer
12 identical photoresist layers, the mode formed is similar with the first insulating layer 12, for example, can be first with the mode of printing the
Photoresist layer is formed on one insulating layer 12；Then photoresist layer is exposed using light shield and is developed to the second opening 130.
Specifically similar with above-mentioned steps S201-S202, details are not described herein.
In another embodiment, above-mentioned second insulating layer 13 is anti-solder ink layer, anti-solder ink layer material
It can be green urushoil ink etc., anti-solder ink layer quality is softer, is easier compressive deformation compared with photoresist when heated.Please refer to Fig. 5
And Fig. 6, Fig. 5 are the flow diagram of mono- embodiment of step S103 in Fig. 1, Fig. 6 is S302 pairs of step of step S301- in Fig. 5
The structural schematic diagram for the embodiment answered, above-mentioned steps S103 are specifically included:
S301: anti-solder ink layer is formed far from the side of substrate/frame 10 in the first insulating layer 12.
Specifically, as shown in Figure 6 a, can use the mode of printing the first insulating layer 12 far from substrate/frame 10 one
Side forms anti-solder ink layer, and the device utilized includes web plate 14 and scraper 16；Certainly, in other embodiments, can also adopt
Anti-solder ink layer is formed with other coating methods.
S302: corroding anti-solder ink layer, forms the second opening 130 with the position in corresponding first opening 120.Tool
Body, as shown in Figure 6 b, one layer of glue film 15 can be pasted on anti-solder ink layer, and corresponding first opening 120 on the glue film 15
Position exposure have the 4th opening 150；Then corroded using corrosive liquid in the position of corresponding 4th opening 150, with corrosion
Fall the 4th 150 corresponding anti-solder ink layers of opening；Finally the glue film 15 is removed.
S104: the metalwork 172 that the front 170 of chip 17 is arranged is placed in the second opening 130, and the front of chip 17
170 bond with second insulating layer 13, and metalwork 172 is electrically connected with conducting connecting part 11.
Specifically, as shown in Figure 2 d, before step S104, method provided herein further include: in chip 17
Front 170 be provided with the position setting metalwork 172 of pad (not shown), metalwork 172 can be metal salient point, and metal is convex
The material of point can be gold, tin etc., and thickness is less than 30um, is greater than 10um, for example, it is with a thickness of 25um, 20um, 15um etc..
When the metalwork 172 that the front 170 of chip 17 is arranged is placed in the second opening 130, as shown in Figure 2 d, the front of chip 17
170 contact with second insulating layer 13, and metalwork 172 is contacted with conducting connecting part 11, metalwork 172 and conducting connecting part 11 it
Between the first spacing be 0, i.e., the sum of the height d3 of the metalwork 172 of chip 17 and the height d1 of conducting connecting part 11 are equal at this time
The sum of the depth of first opening 120 and the second opening 130 d2.
As shown in Figure 2 e, the front 170 and second insulating layer 13 to make chip 17 bond, and guarantee the front of chip 17
There is no gap between 170 and second insulating layer 13, the metalwork 172 that the front 170 of chip 17 is arranged is placed in the second opening 130
After interior, method provided herein further include: briquetting 19 is set at the back side of chip 17 174, to chip 17 and substrate/frame
Frame 10 carries out reflow treatment, and deformation occurs under the action of briquetting 19 and temperature for the first insulating layer 12 and/or second insulating layer 13,
So that the front 170 of chip 17 and second insulating layer 13 bond, and metalwork 172 is electrically connected with conducting connecting part 11.In addition,
In the present embodiment, before briquetting 19 is set, chip 17 and 10 entirety of substrate/frame can also be preheated, by core
Piece 17 and substrate/frame 10 are tentatively fixed.
In another embodiment, as shown in fig. 7, Fig. 7 is the structure of the corresponding another embodiment of step S104 in Fig. 1
Schematic diagram；The metalwork 172a of chip 17a is placed in the second opening (not indicating), the positive 170a of chip 17a and second
Insulating layer 13a contact, and there is the first spacing between metalwork 172a and conducting connecting part 11a, the first spacing is greater than 0.To make
It obtains metalwork 172a to contact with conducting connecting part 11a, briquetting, the first insulating layer 12a can also be introduced as shown in above-described embodiment
With second insulating layer 13a under the action of briquetting and temperature, compressive deformation occurs, chip 17a is moved towards substrate 10a, in turn
So that the metalwork 172a of chip 17a is electrically connected with conducting connecting part 11a.
In yet another embodiment, as shown in figure 8, Fig. 8 is the structure of the corresponding another embodiment of step S104 in Fig. 1
Schematic diagram；The metalwork 172b of chip 17b is placed in the second opening (not indicating), metalwork 172b and conducting connecting part
11b contact, and the positive 170b and second insulating layer 13b of chip 17b has the second spacing, the second spacing is greater than 0.To make core
There is no gap between the positive 170b and second insulating layer 13b of piece 17b, briquetting can also be introduced as shown in above-described embodiment, the
One insulating layer 12b, second insulating layer 13b, conducting connecting part 11b compressive deformation under the action of temperature and pressure, so that core
Piece 17b is towards substrate/frame 10b movement, so that the positive 170b of chip 17b is contacted with second insulating layer 13b.
Referring to Fig. 9, Fig. 9 is the structural schematic diagram of one embodiment of the application semiconductor packing device, the application is mentioned
The semiconductor packing device 1 of confession includes:
Substrate/frame 10；In the present embodiment, substrate/frame 10 can be any kind in the prior art, for example, print
Printed circuit board (PCB), organic substrate, inorganic substrate, glass substrate, flexible base board, copper-iron series frame, copper-nickel-silicon system frame
Deng.In addition, in the present embodiment, the first surface 100 of substrate/frame 10 is additionally provided with multiple pins 102, multiple pins 102
For being electrically connected with other components.
First insulating layer 12, positioned at the first surface 100 of substrate/frame 10, and the first insulating layer 12 is provided with multiple
One opening (not indicating)；In the present embodiment, the first insulating layer 12 is photoresist layer, and the material of photoresist layer can be positivity light
Photoresist, or negative photoresist, the application are not construed as limiting this.
Second insulating layer 13 is located at the first insulating layer 12 far from 10 side of substrate/frame, and second insulating layer 13 corresponding the
The position of one opening is provided with the second opening (not indicating)；In the present embodiment, second insulating layer 13 can be photoresist layer, light
The material of photoresist layer can be positive photoresist, or negative photoresist；Certainly, second insulating layer 13 may be anti-welding
The material of ink layer, anti-solder ink layer can be green urushoil ink etc..
Conducting connecting part 11 is located in the first opening, and the height d1 of conducting connecting part 11 is less than the first opening and second
The sum of depth of opening d2；The material of conducting connecting part 11 can be copper and tin silver alloy etc..
Chip 17, including front 170 and the back side 174, the front 170 of chip 17 and second insulating layer 13 bond, chip 17
Front 170 be provided with metalwork 172, metalwork 172 is electrically connected with conducting connecting part 11.Metalwork 172 can be convex for metal
The material of point, metal salient point can be gold, tin etc..
To sum up, being in contrast to the prior art, method for packaging semiconductor provided herein includes: in base
Plate/frame first surface forms the first insulating layer of stacking and second insulating layer, the first insulating layer are provided with the first opening, the
The position of corresponding first opening of two insulating layers is provided with the second opening, and conducting connecting part is formed in the first opening, and non-bulging
It is placed in the second opening in the metalwork of the second opening, chip front side setting, and the front of chip is bonded with second insulating layer, gold
Belong to part to be electrically connected with conducting connecting part.The first insulating layer and second insulating layer are equivalent to plastic packaging layer in the application, are formed in core
Before piece and substrate/frame first surface are fixed, so as to realize it is not necessarily to that adhesive tape or grinding is arranged at the back side of chip
The back side of chip and the purpose for exposing chip, method for packaging semiconductor provided herein is more simple, easy.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of method for packaging semiconductor, which is characterized in that the method for packaging semiconductor includes:
The first insulating layer is formed in substrate/frame first surface, and forms the first opening on the first insulating layer；
Conducting connecting part is formed in first opening；
Second insulating layer is formed far from the side of the substrate/frame in first insulating layer, and in the second insulating layer
The position of corresponding first opening forms the second opening, and the height of the conducting connecting part is less than first opening and institute
State the sum of the depth of the second opening；
The metalwork of the front setting of chip is placed in second opening, and the front of the chip and second insulation
Layer bonding, the metalwork are electrically connected with the conducting connecting part.
2. method for packaging semiconductor according to claim 1, which is characterized in that described formed in first opening is led
Electrical connector, comprising:
The conducting connecting part is formed in first opening using electroplating technology, and the height of the conducting connecting part is greater than
Equal to the depth of first opening.
3. method for packaging semiconductor according to claim 2, which is characterized in that the method for packaging semiconductor further include:
Reflow treatment is carried out to the conducting connecting part, so that the conducting connecting part is fixed with the substrate/frame, and institute
It states conducting connecting part and forms curved surfaces far from the substrate/frame side.
4. method for packaging semiconductor according to claim 1, which is characterized in that described described in the substrate/frame
First surface forms the first insulating layer, and forms the first opening on the first insulating layer, comprising:
Photoresist layer is formed in the first surface of the substrate/frame；
The photoresist layer is exposed using light shield and is developed to first opening.
5. method for packaging semiconductor according to claim 1, which is characterized in that it is described in first insulating layer far from institute
It states substrate/frame side and forms second insulating layer, and formed in the position that the second insulating layer corresponds to first opening
Second opening, comprising:
Anti-solder ink layer is formed far from the side of the substrate/frame in first insulating layer；
The anti-solder ink layer is corroded, second opening is formed with the position in correspondence first opening.
6. method for packaging semiconductor according to claim 1, which is characterized in that the metal of the front setting by chip
Part is placed in second opening, comprising:
The metalwork of the chip is placed in second opening, front and the second insulating layer of the chip
Contact, and there is the first spacing between the metalwork and the conducting connecting part, first spacing is more than or equal to 0；Alternatively,
The metalwork of the chip is placed in second opening, the metalwork connects with the conducting connecting part
Touching, and the front of the chip has the second spacing with the second insulating layer, second spacing is more than or equal to 0.
7. method for packaging semiconductor according to claim 6, which is characterized in that the metal of the front setting by chip
After part is placed in second opening, the method also includes:
Briquetting is set at the back side of the chip, reflow treatment is carried out to the chip and the substrate/frame, described first absolutely
Deformation occurs under the action of the briquetting and temperature for edge layer and/or the second insulating layer, so that the chip is described
It is positive to be bonded with the second insulating layer, and the metalwork is electrically connected with the conducting connecting part.
8. a kind of semiconductor packing device, which is characterized in that the semiconductor packing device includes:
Substrate/frame；
First insulating layer, positioned at the first surface of the substrate/frame, and first insulating layer is provided with multiple first and opens
Mouthful；
Second insulating layer is located at first insulating layer far from the substrate/frame side, and the second insulating layer corresponds to institute
The position for stating the first opening is provided with the second opening；
Conducting connecting part is located in first opening, and the height of the conducting connecting part is less than first opening and institute
State the sum of the depth of the second opening；
Chip, including front and back, front and the second insulating layer of the chip bond, the front setting of the chip
There is metalwork, the metalwork is electrically connected with the conducting connecting part.
9. semiconductor packing device according to claim 8, which is characterized in that the height of the conducting connecting part be greater than etc.
In the depth of first opening.
10. semiconductor packing device according to claim 8, which is characterized in that
First insulating layer is photoresist layer；Or, the second insulating layer is anti-solder ink layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565049.6A CN109727877A (en) | 2018-12-20 | 2018-12-20 | A kind of method for packaging semiconductor and semiconductor packing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565049.6A CN109727877A (en) | 2018-12-20 | 2018-12-20 | A kind of method for packaging semiconductor and semiconductor packing device |
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| CN109727877A true CN109727877A (en) | 2019-05-07 |
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| CN201811565049.6A Pending CN109727877A (en) | 2018-12-20 | 2018-12-20 | A kind of method for packaging semiconductor and semiconductor packing device |
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| CN103972197A (en) * | 2013-01-24 | 2014-08-06 | 富士通半导体股份有限公司 | Semiconductor device, method for fabricating the same, lead and method for producing the same |
| CN108198794A (en) * | 2017-12-29 | 2018-06-22 | 通富微电子股份有限公司 | A kind of chip packing-body and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499589A (en) * | 2002-11-04 | 2004-05-26 | 矽统科技股份有限公司 | Procedure of encapsulating composite crystal and device |
| CN102136434A (en) * | 2010-01-27 | 2011-07-27 | 马维尔国际贸易有限公司 | Method of stacking flip-chip on wire-bonded chip |
| CN103972197A (en) * | 2013-01-24 | 2014-08-06 | 富士通半导体股份有限公司 | Semiconductor device, method for fabricating the same, lead and method for producing the same |
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Application publication date: 20190507 |