CN108198794A - A kind of chip packing-body and preparation method thereof - Google Patents
A kind of chip packing-body and preparation method thereof Download PDFInfo
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- CN108198794A CN108198794A CN201711499149.9A CN201711499149A CN108198794A CN 108198794 A CN108198794 A CN 108198794A CN 201711499149 A CN201711499149 A CN 201711499149A CN 108198794 A CN108198794 A CN 108198794A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 28
- 229910000679 solder Inorganic materials 0.000 claims abstract description 13
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 8
- 239000000843 powder Substances 0.000 claims description 71
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000006071 cream Substances 0.000 claims description 7
- 238000007639 printing Methods 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 6
- 238000004381 surface treatment Methods 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 230000004927 fusion Effects 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 238000004382 potting Methods 0.000 claims description 3
- 239000000155 melt Substances 0.000 claims 1
- 238000012536 packaging technology Methods 0.000 abstract description 13
- 238000005538 encapsulation Methods 0.000 abstract description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 40
- 238000010586 diagram Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000004224 protection Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- -1 wherein Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
This application discloses a kind of chip packing-bodies and preparation method thereof, are related to chip encapsulation technology field.The method includes：Chip and substrate are provided, the first weld part is provided on chip, the second weld part is provided on substrate, wherein, pre-set fluxing agent on the first weld part or the second weld part；By flip-chip on substrate, wherein, the first weld part carries out solder interconnections with being connected on the second weld part, forms chip packing-body by the above-mentioned means, the application can improve packaging technology efficiency, improve equipment capacity, reduce packaging cost.
Description
Technical field
This application involves chip encapsulation technology field, more particularly to a kind of chip packing-body and preparation method thereof.
Background technology
With the increase of integrated circuit integrated level, the encapsulation technology of chip is also more and more diversified, because of flip-chip skill
Art has the interconnection length shortened in encapsulation, and then can better adapt to highly integrated growth requirement, extensively should at present
For chip package field.Referring to Fig. 1, Fig. 1 is the cross-sectional view of package substrate in the prior art, in flip-chip
In technique, as shown in Figure 1a, the substrate 11 of early application has planted tin ball 111 in advance in welding disking area, after pasting chip 10 by
Reflux makes tin ball 111 weld together after being melted with the metal salient point 101 on chip 10.As shown in Figure 1 b, base common at present
Plate 12 is all exposed in the pad 121 of 10 pasting area of chip, by the metal salient point 101 on pad 121 and chip 10 into
Row reflow soldering.
Present inventor is had found in current flip chip mounting process, chip attachment arrives in long-term R＆D process
It before on substrate, is required for the metal salient point on chip dipping scaling powder, the metal of scaling powder is moistened with using camera identification
Salient point is mounted after being identified by substrate surface.But this technique there is also some problems, such as dip metal after scaling powder
Salient point identification alarm is more, influences equipment capacity；In order to control the amount of scaling powder, customized corresponding jig is needed；Scaling powder exists
Service life on board needs management and control etc., it is therefore desirable to develop new flip chip mounting process to solve the problems, such as these.
Invention content
The application can be had ready conditions and be carried mainly solving the technical problems that provide a kind of chip packing-body and preparation method thereof
High packaging technology efficiency improves equipment capacity, reduces packaging cost.
In order to solve the above technical problems, the technical solution that the application uses is：A kind of potted element, the envelope are provided
Element surface setting weld part is filled, the weld part includes fusible scaling powder.
Wherein, the potted element is package substrate, and scaling powder top surface is less than surface where package substrate.
Wherein, enclosure wall is equipped with around weld part, enclosure wall top surface is higher than scaling powder top surface, and scaling powder top surface is less than package substrate
The structure on place surface.
Wherein, weld part includes the pad between scaling powder and package substrate, and weld part is not provided with pad protection
Layer.
Wherein, the thickness of scaling powder layer is 0.2~0.4 μm.
In order to solve the above technical problems, another technical solution that the application uses is：A kind of system of potted element is provided
Preparation Method, the method includes providing matrix；Weld part is set, and weld part includes fusible scaling powder in matrix surface.
Wherein, potted element is package substrate, and weld part includes pad, and weld part, and weld part are set in matrix surface
Include including fusible scaling powder：Substrate carrier is provided；Overlay film, exposure, development, etching making formation weldering are carried out on support plate
Disk；Pad is surface-treated, to form fusible scaling powder layer on pad, and scaling powder layer top surface is less than package substrate
Place surface.
Wherein, pad is surface-treated, is included with forming fusible scaling powder layer on pad：Pass through the side of printing
Solid weld-aiding cream brush is formed scaling powder layer by formula in corresponding substrate pads.
Wherein, around weld part be equipped with enclosure wall, on support plate carry out overlay film, exposure, development, etching make formed pad it
After further include：Enclosure wall is set around pad, and enclosure wall top surface, higher than scaling powder layer top surface, scaling powder layer top surface is less than encapsulation base
The structure on surface where plate.
The material of enclosure wall is resin material, enclosure wall is set to include around pad：By overlay film, exposure, development, plated film,
Or the mode of printing around pad to form enclosure wall.
In order to solve the above technical problems, another technical solution that the application uses is：A kind of chip packing-body is provided
Preparation method, the method includes：Chip and substrate are provided, the first weld part is provided on chip, second is provided on substrate
Weld part, wherein, pre-set fluxing agent on the first weld part or the second weld part；By flip-chip on substrate, wherein,
First weld part carries out solder interconnections with being connected on the second weld part, forms chip packing-body.
Wherein, the first weld part is metal salient point, and the second weld part is pad, by flip-chip in specifically being wrapped on substrate
It includes：Substrate is loaded into, and substrate is identified；Absorption chip, and the metal salient point on chip is identified；By flip-chip
In completion attachment on substrate, wherein, metal salient point is connected with pad.
Wherein, fluxing agent layer is pre-set on the second weld part, wherein, in the preparation process of substrate, by
Two weld parts carry out surface treatment and form scaling powder layer.
Wherein, it forms scaling powder layer by carrying out surface treatment to the second weld part and includes：It will be solid by way of printing
Body weld-aiding cream brush forms the scaling powder layer on second weld part.
Wherein, enclosure wall is equipped with around second weld part, the enclosure wall top surface is higher than the scaling powder layer top surface, described
Scaling powder layer top surface is less than the structure on surface where the package substrate.
Wherein, it is described by flip-chip on the substrate, and carry out solder interconnections and include：By way of reflow soldering
Solder interconnections are carried out to the chip and substrate.
Wherein, in solder reflow process, scaling powder layer fusing and the first weld part described in catalysed promoted with it is described
Fusion weld between second weld part.
Wherein, it is described by flip-chip on the substrate, and carry out solder interconnections and include：During welding is formed
Pressure is applied to the chip, to press the chip and substrate.
Wherein, it is described by flip-chip on the substrate, and after solder interconnections include：It is filled out using capillary bottom
Fill the gap potting resin glue of technology or molded underfill technology between chip and substrate.
In order to solve the above technical problems, another technical solution that the application uses is：A kind of chip packing-body, institute are provided
Chip packing-body is stated to be made by the preparation method of said chip packaging body.
The advantageous effect of the application is：The situation of the prior art is different from, the application provides a kind of system of chip packing-body
Preparation Method is previously provided with fusible scaling powder on the weld part of potted element used in the preparation method, using the encapsulation first
When part carries out chip package, packaging technology can be shortened, packaging technology efficiency is improved, improve equipment capacity, reduce packaging cost.
Description of the drawings
Fig. 1 a are a kind of cross-sectional views of package substrate in the prior art；
Fig. 1 b are a kind of cross-sectional views of package substrate in the prior art
Fig. 2 is the cross-sectional view of the application potted element first embodiment；
Fig. 3 is the cross-sectional view of the application potted element second embodiment；
Fig. 4 is the flow diagram of the preparation method first embodiment of the application potted element；
Fig. 5 is the process flow diagram of the preparation method second embodiment of the application potted element；
Fig. 6 is the flow diagram of the preparation method first embodiment of the application chip packing-body；
Fig. 7 is the chip attachment flow diagram of the preparation method second embodiment of the application chip packing-body；
Fig. 8 is the process flow diagram of the preparation method second embodiment of the application chip packing-body；
Fig. 9 is the structure diagram of the application chip packing-body first embodiment.
Specific embodiment
Purpose, technical solution and effect to make the application is clearer, clear and definite, and develop simultaneously embodiment pair referring to the drawings
The application is further described.
The application provides a kind of potted element, which may at least apply in chip package process, the encapsulation
Element surface is provided with weld part, and weld part includes fusible scaling powder.By advance on the weld part of the potted element
Fusible scaling powder is set, when the potted element is used to carry out chip package, packaging technology can be shortened, improve packaging technology
Efficiency improves equipment capacity, reduces packaging cost.The potted element can be chip, package substrate etc..In an embodiment
In, when potted element is chip, the weld part on chip is metal salient point, and scaling powder can be arranged on the top of metal salient point
End or the front end of cladding metal salient point.When potted element is package substrate, weld part can be the soldered ball or naked on advance plant
The pad of dew, scaling powder coat soldered ball or are covered in above pad.
Optionally, referring to Fig. 2, Fig. 2 is the cross-sectional view of the application potted element first embodiment.At this
In embodiment, potted element is package substrate 20, and weld part is exposed pad 201, and scaling powder is covered in the upper of pad 201
It is rectangular that and 202 top surface of scaling powder layer be less than surface where package substrate into scaling powder layer 202, the thickness of scaling powder layer for 0.2~
0.4μm。
Optionally, referring to Fig. 3, Fig. 3 is the cross-sectional view of the application potted element second embodiment.At this
In embodiment, potted element is package substrate 30, and weld part is exposed pad 301, and scaling powder is covered in the top of pad
Form scaling powder layer 302.Enclosure wall 303 is equipped with around pad 301,303 top surface of enclosure wall is higher than 302 top surface of scaling powder layer, scaling powder
302 top surface of layer are less than the structure on surface where package substrate.By setting enclosure wall, can enclose multiple empty with certain receiving
Between groove, and scaling powder layer is in bottom portion of groove, becomes liquid when in reflow soldering, scaling powder can melt, this groove
The scaling powder of buffering liquid can be accommodated, is unlikely to spill on peripheral substrate, can prevent scaling powder fusing from overflowing and pollute
And waste；On the other hand, by setting enclosure wall, pad can be located in multiple grids, when carrying out chip package attachment,
Pad is found by grid location, placement accuracy and efficiency can be improved.
To prepare above-mentioned potted element, the application also provides a kind of preparation method of potted element.Referring to Fig. 4, Fig. 4 is
The flow diagram of the preparation method first embodiment of the application potted element.As shown in figure 5, in this embodiment, envelope
The preparation method of dress element includes the following steps：
S401：Matrix is provided.
Specifically, corresponding matrix is provided according to the type of potted element.
S402：Weld part is set, and weld part includes fusible scaling powder in matrix surface.
Specifically, according to the type of potted element and corresponding manufacture craft, adaptability sets weld part and scaling powder.
Optionally, Fig. 2, Fig. 3 and Fig. 5 are please referred to, Fig. 5 is the second embodiment party of preparation method of the application potted element
The process flow diagram of formula.In this embodiment, potted element is package substrate, and weld part is exposed pad, helps weldering
The top that agent is covered in pad forms scaling powder layer.As shown in figure 5, the preparation method of package substrate includes：
Substrate carrier is provided, support plate is generally selected DTF support plates, made by techniques such as overlay film, exposure, development, etchings
Substrate 501 is obtained after base plate line and pad connecting pole；On substrate 501 after copper plate 502, one layer is covered in layers of copper 502
Negative photoresist film 503；And it in one piece of MASK 504 of covering on negative photoresist film 503 and is exposed；Layers of copper is carried out after development
Etching removes extra negative photoresist film 503 and obtains pad 505 again；It, can be according to final institute after etching obtains pad 505
Type of substrate is needed, adapts to selection subsequent technique.
In one embodiment, for above-mentioned package substrate 20 is made, subsequent technique is：In the place in addition to pad 505
Coat soldermask layer；Pad 505 is surface-treated, is formed solid weld-aiding cream brush on pad 505 by way of printing
Scaling powder layer 202, scaling powder, 202 thickness is 0.2~0.4 μm.The preparation process of the substrate is prepared relative to existing substrate
Technique, the process that OSP (having machine aided to weld protective film) is coated in process of surface treatment will have machine aided weldering protection materials to be replaced with water
The weld-aiding cream of dissolubility, obtained coating are scaling powder layer 202；Therefore, the substrate that prepared by this method, there is no protections on pad
Layer.By changing existing protective layer into scaling powder layer, can either play the role of protecting pad, additionally it is possible to be subsequent Welder
Skill saves process, meanwhile, it will not also increase the preparation section of substrate, improve total production efficiency.
In one embodiment, for above-mentioned package substrate 30 is made, after etching obtains pad 505, it is also necessary to prepare enclosure wall
506, the material of wherein enclosure wall 506 is close with substrate material, can select suitable organic material.It can be by way of printing
Organic material brush is formed into enclosure wall 506 around pad 505；It can also be made by way of overlay film, exposure, development, plated film
It is standby to form enclosure wall 506.Scaling powder layer 302 is prepared followed by processes such as coating soldermask layer, surface treatments, specific process please join
Foregoing description is read, details are not described herein, makes 303 top surface of gained enclosure wall higher than 302 top surface of scaling powder layer, 302 top surface of scaling powder layer
Less than the structure on 30 place surface of package substrate.
When carrying out chip package using above-mentioned potted element, packaging technology can be shortened, packaging technology efficiency is improved, carry
High equipment capacity reduces packaging cost.On this basis, the application also provides a kind of preparation method of chip packing-body, please join
Fig. 6 is read, Fig. 6 is the flow diagram of the preparation method first embodiment of the application chip packing-body, as shown in fig. 6, at this
In embodiment, the preparation method of potted element includes the following steps：
S601：Chip and substrate are provided, the first weld part is provided on chip, the second weld part is provided on substrate,
In pre-set fluxing agent on the first weld part or the second weld part.
Specifically, the chip and substrate can be above-mentioned potted elements, and concrete structure and preparation method please refer to above-mentioned
The description of related potted element embodiment, details are not described herein.The chip and substrate can be by customizing by chip, substrate manufacturer
It provides or chip package manufacturer voluntarily prepares according to above-mentioned preparation method.
S602：By flip-chip on substrate, wherein the first weld part and the second weld part are connected, and welded
Interconnection forms chip packing-body.
Specifically, the first weld part on chip can be metal salient point, and the second weld part on substrate can be pad.
In one embodiment, substrate can be the special substrate for adapting to certain chip, and pad is consistent with the quantity of metal salient point,
And it is correspondingly arranged；In other embodiments, substrate can also be for the universal type basal plate in chip package preparation process,
And on substrate multiple chips can be assembled simultaneously (these chips can be set in side-by-side fashion, can also be set in a stacked fashion
Put), to carry out fast packing to multiple chips simultaneously.Therefore the number of pads on substrate can be more than the metal salient point on chip
Quantity, as long as can ensure that the metal salient point on chip has the corresponding matching connection of pad.
In this embodiment, because being previously provided with fusible scaling powder on the weld part of chip or substrate, therefore,
It in subsequent packaging technology, will no longer be required to dip scaling powder immediately, shorten packaging technology, improve packaging technology efficiency.Specifically
Ground, please refers to Fig. 7 and Fig. 8, and Fig. 7 is the chip attachment stream of the preparation method second embodiment of the application chip packing-body
Journey schematic diagram, Fig. 8 is the process flow diagram of the preparation method second embodiment of the application chip packing-body, in the implementation
In mode, chip and the detailed process that substrate mounts are included：
S701：Substrate 81 is loaded into, and substrate 81 is identified.
Wherein, fluxing agent layer 812 is pre-set on the pad 811 of substrate 81, so, it, can be direct after substrate is loaded into
Identification does not need to re-coating scaling powder.
S702：Absorption chip 82, and the metal salient point 821 on chip 82 is identified.
It wherein, can be direct after absorption chip because having pre-set fluxing agent 812 on corresponding substrate 81
Metal salient point 821 is identified, and no longer needs to dip scaling powder immediately, shortens attachment process, while also improves identification effect
Rate.
S703：By 82 upside-down mounting of chip in completion attachment on substrate 81, wherein, metal salient point 821 connects with the cooperation of pad 811
It connects.
Then, the chip mounted and substrate are subjected to reflow soldering, during being heated at reflux, scaling powder layer 812
Weld-aiding cream is melted by high temperature from Solid State Transformation into liquid so that the tin cap portion on 821 top of metal salient point on chip 82 is complete
Full infiltration is in weld-aiding cream, fusion weld between pad 811 on catalytic metal salient point 821 and substrate 81, then is transformed into from liquid
Gaseous state vapors away.Finally, product enters the 821 top tin cap curing of cooling zone metal salient point, is welded on pad 811 on substrate 81
Together.
Optionally, on substrate 81, enclosure wall 813 is also set up between pad 811,813 top surface of enclosure wall is pushed up higher than scaling powder layer 812
Face, 812 top surface of scaling powder layer is less than the structure on surface where package substrate.By setting enclosure wall, pad can be located in more
In a grid, when carrying out chip package attachment, pad is found by grid location, placement accuracy and efficiency can be improved；Separately
On the one hand, by setting enclosure wall, multiple grooves with certain accommodation space can be enclosed, and scaling powder layer is in groove-bottom
Portion becomes liquid when in reflow soldering, scaling powder can melt, this groove can accommodate the scaling powder of buffering liquid, be unlikely to
It spills on peripheral substrate, can prevent scaling powder fusing from overflowing and pollute and waste.
It is alternatively possible to apply pressure to chip 82 during welding is formed, to press chip 82 and substrate 81, carry
The stability of height welding.
Optionally, after the completion of welding, using capillary underfill technology or molded underfill technology to chip and base
Gap potting resin glue between plate, underfill be a kind of low-viscosity, low-temperature setting Capillary Flow bottom under filler
(Underfill), flowing velocity is fast, and long working life overhauls excellent performance.It can be with dispersed chip surface by using underfill
The stress that bears and then the reliability for improving entire product.
Chip packing-body can be efficiently prepared using above-mentioned preparation method, referring to Fig. 9, Fig. 9 is the application chip envelope
Fill the structure diagram of body first embodiment.The application also provides a kind of chip packing-body 90, which is making
It is made during standby using above-mentioned preparation method, specific preparation process please refers to the description of the above embodiment, herein no longer
It repeats.
Above scheme, the application provide a kind of potted element, are previously provided on the weld part of the potted element fusible
Scaling powder when the potted element is used to carry out chip package, can shorten packaging technology, improve packaging technology efficiency, improve
Equipment capacity reduces packaging cost.
The foregoing is merely presently filed embodiments, not thereby limit the scope of the claims of the application, every to utilize this
It is relevant to be directly or indirectly used in other for the equivalent structure or equivalent flow shift that application specification and accompanying drawing content are made
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of preparation method of chip packing-body, which is characterized in that the method includes：
Chip and substrate are provided, the first weld part is provided on the chip, the second weld part is provided on the substrate, wherein
Fusible scaling powder is previously provided on first weld part or second weld part；
By the flip-chip on the substrate, wherein first weld part is connected with second weld part, and
Solder interconnections are carried out, form chip packing-body.
2. the preparation method of chip packing-body according to claim 1, which is characterized in that first weld part is metal
Salient point, second weld part is pad, described to specifically include flip-chip on the substrate：
The substrate is loaded into, and the substrate is identified；
The chip is drawn, and the metal salient point on the chip is identified；
By the flip-chip in completion attachment on the substrate, wherein, the metal salient point is connected with the pad.
3. the preparation method of chip packing-body according to claim 1, which is characterized in that on second weld part in advance
Fluxing agent layer is set, wherein, in the preparation process of the substrate, by carrying out surface treatment shape to second weld part
Into the scaling powder layer.
4. the preparation method of chip packing-body according to claim 3, which is characterized in that described by being welded to described second
Socket part carries out surface treatment and forms the scaling powder layer and include：
Solid weld-aiding cream brush is formed into the scaling powder layer on second weld part by way of printing.
5. the preparation method of chip packing-body according to claim 1, which is characterized in that set around second weld part
There is enclosure wall, the enclosure wall top surface is higher than the scaling powder layer top surface, and the scaling powder layer top surface is less than where the package substrate
The structure on surface.
6. the preparation method of chip packing-body according to claim 1, which is characterized in that it is described by flip-chip in described
On substrate, and carry out solder interconnections and include：
Solder interconnections are carried out to the chip and substrate by way of reflow soldering.
7. the preparation method of chip packing-body according to claim 6, which is characterized in that
In solder reflow process, the scaling powder layer melts simultaneously the first weld part described in catalysed promoted and second weld part
Between fusion weld.
8. the preparation method of chip packing-body according to claim 6, which is characterized in that it is described by flip-chip in described
On substrate, and carry out solder interconnections and include：
Pressure is applied to the chip during welding is formed, to press the chip and substrate.
9. the preparation method of chip packing-body according to claim 1, which is characterized in that it is described by flip-chip in described
On substrate, and after solder interconnections include：
Utilize the gap potting resin glue of capillary underfill technology or molded underfill technology between chip and substrate.
10. a kind of chip packing-body, which is characterized in that the chip packing-body passes through such as claim 1~9 any one of them
The preparation method of chip packing-body is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711499149.9A CN108198794A (en) | 2017-12-29 | 2017-12-29 | A kind of chip packing-body and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711499149.9A CN108198794A (en) | 2017-12-29 | 2017-12-29 | A kind of chip packing-body and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108198794A true CN108198794A (en) | 2018-06-22 |
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ID=62587833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711499149.9A Pending CN108198794A (en) | 2017-12-29 | 2017-12-29 | A kind of chip packing-body and preparation method thereof |
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| CN (1) | CN108198794A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712912A (en) * | 2018-12-06 | 2019-05-03 | 通富微电子股份有限公司 | A kind of flip-chip device and method |
| CN109727877A (en) * | 2018-12-20 | 2019-05-07 | 通富微电子股份有限公司 | A kind of method for packaging semiconductor and semiconductor packing device |
| CN114045137A (en) * | 2022-01-12 | 2022-02-15 | 武汉市三选科技有限公司 | Panel driving circuit bottom filling adhesive, preparation method thereof and chip packaging structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040169275A1 (en) * | 2003-02-27 | 2004-09-02 | Motorola, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
| CN202169445U (en) * | 2011-07-15 | 2012-03-21 | 广州先艺电子科技有限公司 | Preformed soldering lug pre-coated with soldering flux coating |
| KR20120095662A (en) * | 2011-02-21 | 2012-08-29 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
| CN107346742A (en) * | 2016-05-05 | 2017-11-14 | 中芯国际集成电路制造（天津）有限公司 | The preparation method of wafer bumps |
-
2017
- 2017-12-29 CN CN201711499149.9A patent/CN108198794A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040169275A1 (en) * | 2003-02-27 | 2004-09-02 | Motorola, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
| KR20120095662A (en) * | 2011-02-21 | 2012-08-29 | 엘지이노텍 주식회사 | The printed circuit board and the method for manufacturing the same |
| CN202169445U (en) * | 2011-07-15 | 2012-03-21 | 广州先艺电子科技有限公司 | Preformed soldering lug pre-coated with soldering flux coating |
| CN107346742A (en) * | 2016-05-05 | 2017-11-14 | 中芯国际集成电路制造（天津）有限公司 | The preparation method of wafer bumps |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712912A (en) * | 2018-12-06 | 2019-05-03 | 通富微电子股份有限公司 | A kind of flip-chip device and method |
| CN109727877A (en) * | 2018-12-20 | 2019-05-07 | 通富微电子股份有限公司 | A kind of method for packaging semiconductor and semiconductor packing device |
| CN114045137A (en) * | 2022-01-12 | 2022-02-15 | 武汉市三选科技有限公司 | Panel driving circuit bottom filling adhesive, preparation method thereof and chip packaging structure |
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Application publication date: 20180622 |
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