CN109725673B - Fully-integrated multi-output stacked low-dropout linear voltage regulator - Google Patents

Abstract

The invention discloses a fully-integrated multi-output stacked low dropout regulator, which comprises a main LDO and an auxiliary LDO_kK is 1,2 … n; main LDO passes through on-chip electric capacity C₀And Load₀And auxiliary LDO_kOn-chip capacitor C on circuit_kAnd Load_kThe series connection forms a stacked structure, the main LDO is used for providing current required by a load, and the auxiliary LDO_kFor stabilizing VOUT_kVoltage, generated from VDD when load current is not uniform_kFlow through MP_kTo VOUT_kI of (A)_sourceCurrent or from VOUT_kFlows through MN_kI to GND_sinkThe current is applied. The stacked structure can flexibly adjust the output voltage value and the output voltage quantity according to the load requirement, and meets the more flexible load requirement; auxiliary LDO_kThe three working modes can quickly adjust the voltage and current fluctuation caused by mismatching between loads, and improve the dynamic performance of a power supply system; the fully integrated structure is beneficial to system integration and cost reduction; all output terminals have good PSR characteristics, especially output terminals close to GND, and are suitable for modules sensitive to power supplies.

Description

Fully-integrated multi-output stacked low-dropout linear voltage regulator

Technical Field

The invention belongs to the technical field of design of semiconductor integrated circuits and low-power-consumption integrated circuits, and particularly relates to a fully-integrated multi-output stacked low-dropout linear regulator which is applied to the fields of high-performance power systems and consumer electronics.

Background

LDOs are one of the widely used voltage converters in power management systems, and are especially important in battery-powered portable devices (e.g., cell phones, tablets, and wearable devices). The LDO has low noise and fast response characteristics, and is very suitable for high-performance and supply voltage-sensitive analog/mixed signal modules. When the input and output voltages of the LDO have large difference due to the structure and the working principle of the LDO, the system efficiency is low. Especially, in the current application environment, the technology of the integrated circuit is continuously upgraded, the required power supply voltage, namely the output voltage of the LDO, is continuously reduced, and the input voltage of the LDO cannot be synchronously reduced due to the constraint of the technology and the performance, so that the efficiency of the LDO is rapidly reduced, and energy waste is caused. For the situation, the stacked structure formed by stacking the loads can improve the power supply voltage required by the system, and at the moment, the system efficiency can be improved if a new LDO structure is adopted for supplying power. For a stacked system, the existing research adopts a structure based on a switched capacitor to realize multi-layer stacked power supply, and a larger on-chip or off-chip capacitor and a switched clock are needed to realize functions.

To sum up, the existing technology adopts a switched capacitor to realize multi-output and stacked power supply, and the implementation mode has the following problems:

1. on-chip capacitance leads to increased chip area and off-chip capacitance increases system cost;

2. the clock control causes the complexity of the system to rise, and the power supply rejection ratio (PSR) of the switch capacitor structure is poor and is not suitable for a sensitive circuit.

Disclosure of Invention

The present invention provides a fully integrated multi-output stacked low dropout regulator, which stacks a plurality of LDOs to realize multi-output, in order to overcome the above-mentioned shortcomings in the prior art. Because each LDO can independently control the output voltage, the voltage between the laminated layers is variable, the application range is expanded, meanwhile, the system efficiency is improved, the full integration is realized, and the good PSR characteristic is obtained.

The invention adopts the following technical scheme:

a fully integrated multi-output stacked low dropout regulator comprises a main LDO and an auxiliary LDO_kK is 1,2 … n; main LDO passes through on-chip electric capacity C₀And Load₀And auxiliary LDO_kOn-chip capacitor C on circuit_kAnd Load_kThe series connection forms a stacked structure, the main LDO is used for providing current required by a load, and the auxiliary LDO_kFor stabilizing VOUT_kVoltage, generated from VDD when load current is not uniform_kFlow through MP_kTo VOUT_kI of (A)_sourceCurrent or from VOUT_kFlows through MN_kI to GND_sinkThe current is applied.

Specifically, the main LDO includes an error amplifier EA₀Adjusting tube MP₀Feedback resistance R_F1、R_F2On-chip capacitor C₀And Load₀Error amplifier EA₀Is connected with the reverse input end VREF₀The non-inverting input terminal is respectively connected with the feedback resistor R_F1、R_F2Connected, error amplifier EA₀Power supply end connection adjusting tube MP₀Source electrode of (1), error amplifier EA₀The output end of the adjusting tube MP₀Grid of (1), adjusting tube MP₀Is divided into three pathsA capacitor C on a contact piece₀Second routing Load₀And the third path is through a feedback resistor R_F1Then divided into two paths, one path is through a feedback resistor R_F2Grounded, and connected to error amplifier EA₀The non-inverting input terminal of (1).

In particular, the auxiliary LDO_kComprising an error amplifier EA_kPMOS adjusting tube MP_kNMOS tuning tube MN_kBias voltage VB_kOn-chip capacitor C_kAnd Load_kError amplifier EA_kIs connected with the reverse input end VREF_kThe same phase input end is respectively connected with a PMOS adjusting tube MP_kDrain electrode, NMOS regulating tube MN_kDrain electrode, on-chip capacitor C_kAnd Load_kConnected, error amplifier EA_kPower supply end connected with PMOS adjusting tube MP_kSource electrode of (1), error amplifier EA_kThe output of the voltage divider is divided into two paths, one path is biased by a bias voltage VB_kMP connected with PMOS adjusting tube_kThe other path of the grid is connected with an NMOS adjusting tube MN_kThe gate of (MN), the NMOS regulating tube_kIs grounded.

In particular, the on-chip capacitor C_k-1And Load_k-1Is connected to VOUT_k-1And VOUT_kK 1,2 … n, on-chip capacitance C_nAnd Load_nIs connected to VOUT_nAnd GND.

Specifically, the power supply end VDD of the main LDO is connected to an external power supply port, and the auxiliary LDO_kPower supply terminal VDD of circuit_kThe method comprises the following three connection modes: VDD_kIs connected with VDD; VDD_kAre respectively connected with VOUT_k-1Link, k ═ 1,2 … n; VDD_kAre respectively connected with VOUT_m-1And m is 1,2 … k.

Specifically, the output voltage VOUT_kAnd VOUT_k-1The difference of (a) is the same or different, k is 1,2 … n.

In particular, the auxiliary LDO_kThe method comprises a Source mode, a Sink mode and a Neutral mode; when Load is loaded_kRequired current I_kLoad greater than Load_k-1Required current I_k-1Time-assisted LDO_kWorking in a Source mode; when the load isLoad_kRequired current I_kLoad less than Load_k-1Required current I_k-1Time-assisted LDO_kWorking in a Sink mode; when Load is loaded_kRequired current I_kLoad equal to_k-1Required current I_k-1Time-assisted LDO_kOperating in Neutral mode.

Furthermore, in Source mode, the MP of the adjusting tube_kOpen, MN_kIs turned off to generate a current I_source-kFrom VDD_kFlow through MP_kTo VOUT_kIs a Load_kProviding additional current to generate current satisfying the relation I_source-k＝I_k-I_k-1。

Further, in Sink mode, the MN is adjusted_kOpen, MP_kIs turned off to generate a current I_sink-kFrom VOUT_kFlows through MN_kTo GND, the flow is extracted to Load_kExcess current, generated current satisfying the relation of I_sink-k＝I_k-1-I_k。

Furthermore, in Neutral mode, the MN is adjusted_kAnd MP_kIn subthreshold region, assist LDO_kDoes not generate extra current I_source-kOr I_sink-k。

Compared with the prior art, the invention has at least the following beneficial effects:

according to the fully-integrated multi-output stacked low dropout regulator, a plurality of low dropout regulators (LDOs) form a stacked structure, the system efficiency is improved while fully-integrated multi-output is realized, the output voltage value and the output voltage quantity can be flexibly adjusted according to the load requirement, and the more flexible stacked load requirement can be met; voltage and current fluctuation caused by mismatching of loads can be quickly adjusted, and the dynamic performance of a power supply system is improved; a fully integrated structure is realized, system integration is facilitated, and cost is reduced; the circuit has good PSR characteristics, particularly the output end close to GND, and is suitable for a module sensitive to a power supply.

Further, the main LDO is used for generating VOUT₀Voltage, simultaneously for stacked load liftingSupplying current.

Further, the auxiliary LDO_kFor generating VOUT_kVoltage, stable VOUT when stacked loads are unbalanced_kProviding additional current I while applying voltage_source-kOr I_sink-k。

Further, an on-chip capacitor C_k-1To improve the output dynamic characteristics and power supply rejection ratio. Load_k-1The stacked structure improves the efficiency of the design and forms diversified power supply forms.

Further, a power supply end VDD of the main LDO is connected to an external power supply port. Auxiliary LDO_k( k 1,2 … n) power supply terminal VDD_kConnected to VDD, minimum MP can be achieved_kAnd MN_kSize design and optimal dynamic response characteristics; VDD_kAre respectively connected with VOUT_k-1Connection, optimal PSR characteristics can be achieved; VDD_kAnd VOUT_m-1(m-1, 2 … k) to realize MP_kAnd MN_kArea, dynamic response characteristics, and PSR characteristics.

Further, VOUT_k(k is 1,2 … n) and VOUT_k-1(k ═ 1,2 … n), i.e. the voltage difference between two adjacent outputs, i.e. the Load_k( k 0,1,2 … n) voltage difference Δ V across the terminals_kThe values of (k ═ 0,1,2 … n) may be the same or different, so as to achieve diversified load requirements and corresponding output voltage configurations of the stacked low dropout linear regulator.

Further, current I_source-kOr I_sink-kTo ensure VOUT_kAnd (5) stabilizing the voltage.

Furthermore, the Source mode can realize that additional current I is generated when the stacked loads are mismatched_source-kTo ensure VOUT_kAnd (5) stabilizing the voltage.

Furthermore, the Sink mode can realize that additional current I is generated when the stacked loads are mismatched_sink-kTo ensure VOUT_kAnd (5) stabilizing the voltage.

Furthermore, when the Neutral mode can realize stacked load matching, the Neutral mode does not need to be usedGenerating extra current while ensuring VOUT_kAnd (5) stabilizing the voltage.

In summary, the stacked structure of the invention can flexibly adjust the output voltage value and the output voltage quantity according to the load requirement, and can meet the more flexible load requirement; auxiliary LDO_kThe three working modes can quickly adjust the voltage and current fluctuation caused by mismatching between loads, and improve the dynamic performance of a power supply system; the fully integrated structure is beneficial to system integration and cost reduction; all output terminals have good PSR characteristics, especially output terminals close to GND, and are suitable for modules sensitive to power supplies.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

FIG. 1 is a diagram of a fully integrated multi-output stacked low dropout linear regulator according to the present invention;

FIG. 2 shows an auxiliary LDO of the present invention_kThe three working mode diagrams of (1);

FIG. 3 shows a dual output VOUT with the design of the present invention₁0.8V transient oscillogram;

FIG. 4 shows a dual output VOUT with the design of the present invention₁1.6V transient oscillogram;

FIG. 5 shows a dual output VOUT with the design of the present invention₁2.4V transient oscillogram;

FIG. 6 shows a dual output VOUT with the design of the present invention₁PSR characteristic diagrams in three modes.

Detailed Description

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The invention provides a fully-integrated multi-output stacked low dropout regulator (LDO), which is formed by a plurality of LDOs into a stacked structure, so that the system efficiency is improved while the fully-integrated multi-output is realized.

Referring to fig. 1, a fully integrated multi-output stacked low dropout regulator according to the present invention includes a main LDO and a plurality of auxiliary LDOs₁～LDO_nSeveral auxiliary LDOs₁～LDO_nThe LDO is connected with the main LDO in series through the corresponding on-chip capacitor and the load respectively, and the on-chip capacitor and the load are connected in parallel.

The main LDO comprises an error amplifier EA₀Adjusting tube MP₀Feedback resistance R_F1、R_F2On-chip capacitor C₀And a Load to be driven₀Error amplifier EA₀Is connected with the reverse input end VREF₀The non-inverting input terminal is respectively connected with the feedback resistor R_F1、R_F2Connected, error amplifier EA₀Power supply end connection adjusting tube MP₀Source electrode of (1), error amplifier EA₀The output end of the adjusting tube MP₀Grid of (1), adjusting tube MP₀The drain electrode of the capacitor is divided into three paths, one path is connected with an on-chip capacitor C₀Second routing Load₀And the third path is through a feedback resistor R_F1Then divided into two paths, one path is through a feedback resistor R_F2Grounded, and connected to error amplifier EA₀The non-inverting input terminal of (1).

Auxiliary LDO_kThe circuit ( k 1,2 … n) includes an error amplifier EA_kPMOS adjusting tube MP_k(k is 1,2 … n), NMOS tuning transistor MN_k( k 1,2 … n), bias voltage VB_k( k 1,2 … n), on-chip capacitance C_k( k 1,2 … n) and a Load to be driven_k( k 1,2 … n), error amplifier EA_kIs connected with the reverse input end VREF₁The same phase input end is respectively connected with a PMOS adjusting tube MP_kDrain electrode, NMOS regulating tube MN_kDrain electrode, on-chip capacitor C_k-1On-chip capacitor C_kLoad, Load₀And Load_kConnection, error proofingAmplifier EA_kPower supply end connected with PMOS adjusting tube MP_kSource electrode of (1), error amplifier EA_kThe output of the voltage divider is divided into two paths, one path is biased by a bias voltage VB_kMP connected with PMOS adjusting tube_kThe other path of the grid is connected with an NMOS adjusting tube MN_kThe gate of (MN), the NMOS regulating tube_kIs grounded.

On-chip capacitor C_k-1And Load_k-1Is connected to VOUT_k-1And VOUT_kOn-chip capacitor C_nAnd Load_nIs connected to VOUT_nAnd GND.

Main LDO provides Load₀～Load_nRequired current, auxiliary LDO_kStabilize VOUT_kVoltage dependent, slave VDD generated when load currents are not uniform_kFlow through MP_kTo VOUT_kI of (A)_sourceCurrent or from VOUT_kFlows through MN_kI to GND_sinkThe current is applied.

According to different requirements, the stacked LDO is arranged as follows:

the number of the auxiliary LDOs varies according to the number of the output voltages, so that the stacked low dropout linear regulator of the present invention may comprise a main LDO and an auxiliary LDO, or a main LDO and a plurality of auxiliary LDOs.

The power supply end VDD of the main LDO is connected to an external power supply port, and the auxiliary LDO_kPower supply terminal VDD of circuit ( k 1,2 … n)_kThe connection mode has the following options:

a.VDD_kconnected with VDD to realize minimum MP_kAnd MN_kSize design and optimal dynamic response characteristics;

b.VDD_kare respectively connected with VOUT_k-1Connecting to realize optimal PSR characteristics;

c.VDD_kand VOUT_m-1(m-1, 2 … k) to achieve MP_kAnd MN_kArea, dynamic response characteristics, and PSR characteristics.

Reference voltage VREF of main LDO₀And auxiliary LDO_kReference voltage VREF in ( k 1,2 … n)_k(k-1, 2 … n) can be designed separately to achieveRequired VOUT_k(k＝0,1,2…n)。VOUT_k(k is 1,2 … n) and VOUT_k-1A difference between (k ═ 1,2 … n), that is, a voltage difference between two adjacent outputs, that is, a voltage difference Δ V across load k (k ═ 0,1,2 … n)_kThe values (k-0 … n) may be the same or different to realize diversified output voltage configurations of the stacked low dropout linear regulator.

On-chip capacitor C_kThe volume values (k ═ 0,1,2 … n) may be the same or different. The design can be carried out according to the requirements of load, stability, dynamic characteristics and PSR characteristics.

Please refer to fig. 2, the auxiliary LDO_kThe circuit (k ═ 1,2 … n) has three operating modes, Source mode, Sink mode, and Neutral mode.

For the auxiliary LDOk, when the Load is loaded_kRequired current I_kLoad greater than Load_k-1Required current I_k-1Time-assisted LDO_kWorking in Source mode, adjusting tube MP_kOpen, MN_kIs turned off to generate a current I_source-kFrom VDD_kFlow through MP_kTo VOUT_kIs a Load_kProviding additional current;

when Load is loaded_kRequired current I_kLoad less than Load_k-1Required current I_k-1Time-assisted LDO_kWorking in Sink mode, adjusting the tube MN_kOpen, MP_kIs turned off to generate a current I_sink-kFrom VOUT_kFlows through MN_kTo GND, the flow is extracted to Load_kExcess current flow;

when Load is loaded_kRequired current I_kLoad equal to_k-1Required current I_k-1Time-assisted LDO_kWorking in Neutral mode, the adjusting pipe MN is_kAnd MP_kIn subthreshold region, assist LDO_kDoes not generate extra current I_source-kOr I_sink-k。

MP in main LDO₀Is required to satisfy the Load_k(k-0, 1,2 … n). Auxiliary LDO_k(k is 1,2 … n) middle MP_k(k-1, 2 … n) and MN_k( k 1,2 … n) according to Load_k(k-1, 2 … n) mismatch case design, which produces I_source-kAnd I_sink-kThe maximum mismatch condition needs to be satisfied. I.e. in Source mode, I_source-k≥I_k-I_k-1(ii) a In Sink mode, I_sink-k≥I_k-1-I_k。

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention has been applied to the design of a high-efficiency fully-integrated stacked two-output low dropout linear regulator. In the design, n is 1 and comprises a main LDO and an auxiliary LDO₁. Its supply voltage VDD is 3.3V, auxiliary LDO₁Power supply terminal VDD of₁Is connected with VOUT₀To realize VOUT₁Optimal PSR characteristics.

VOUT₀＝3.2V，VOUT₁Can be varied over a wide range to meet different stacked load requirements. The maximum load current is 50mA, and the LDO is assisted₁The maximum current of the Source and Sink modes is 10 mA.

Please refer to fig. 3, 4 and 5, which are VOUT respectively₁When the voltage is 0.8V, 1.6V and 2.4V, transient waveforms of load jump occur at two output ends. When the load current jumps between 45mA and 55mA, both outputs can be quickly stabilized. Auxiliary LDO₁Switching among three modes in the jumping process to quickly adjust VOUT₁Voltage and current.

FIG. 6 is VOUT₁PSR characteristics of the ports due to VDD in this design₁And VOUT₀Connected, exhibits low frequency PSR characteristics almost twice that of conventional LDOs. The LDO of the design has the efficiency of 3.2V/3.3V ≈ 97% when the LDO does not consider other losses, and the problem of low efficiency caused by large input and output differential pressure of the traditional LDO structure is solved.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (4)

1. A fully integrated multi-output stacked low dropout regulator comprises a main LDO and an auxiliary LDO_kK is 1,2 … n; main LDO passes through on-chip electric capacity C₀And Load₀And auxiliary LDO_kOn-chip capacitor C on circuit_kAnd Load_kThe series connection forms a stacked structure, the main LDO is used for providing current required by a load, and the auxiliary LDO_kFor stabilizing VOUT_kVoltage, generated from VDD when load current is not uniform_kFlow through MP_kTo VOUT_kI of (A)_sourceCurrent or from VOUT_kFlows through MN_kI to GND_sinkCurrent flow;

the main LDO comprises an error amplifier EA₀Adjusting tube MP₀Feedback resistance R_F1、R_F2On-chip capacitor C₀And Load₀Error amplifier EA₀Is connected with the reverse input end VREF₀The non-inverting input terminal is respectively connected with the feedback resistor R_F1、R_F2Connected, error amplifier EA₀Power supply end connection adjusting tube MP₀Source electrode of (1), error amplifier EA₀The output end of the adjusting tube MP₀Grid of (1), adjusting tube MP₀The drain electrode of the capacitor is divided into three paths, one path is connected with an on-chip capacitor C₀Second connected to the loadLoad₀And the third path is through a feedback resistor R_F1Then divided into two paths, one path is through a feedback resistor R_F2Grounded, and connected to error amplifier EA₀The non-inverting input terminal of (1);

auxiliary LDO_kComprising an error amplifier EA_kPMOS adjusting tube MP_kNMOS tuning tube MN_kBias voltage VB_kOn-chip capacitor C_kAnd Load_kError amplifier EA_kIs connected with the reverse input end VREF_kThe same phase input end is respectively connected with a PMOS adjusting tube MP_kDrain electrode, NMOS regulating tube MN_kDrain electrode, on-chip capacitor C_kAnd Load_kConnected, error amplifier EA_kPower supply end connected with PMOS adjusting tube MP_kSource electrode of (1), error amplifier EA_kThe output of the voltage divider is divided into two paths, one path is biased by a bias voltage VB_kMP connected with PMOS adjusting tube_kThe other path of the grid is connected with an NMOS adjusting tube MN_kThe gate of (MN), the NMOS regulating tube_kThe source of (2) is grounded;

auxiliary LDO_kThe method comprises a Source mode, a Sink mode and a Neutral mode; when Load is loaded_kRequired current I_kLoad greater than Load_k-1Required current I_k-1Time-assisted LDO_kWorking in a Source mode; when Load is loaded_kRequired current I_kLoad less than Load_k-1Required current I_k-1Time-assisted LDO_kWorking in a Sink mode; when Load is loaded_kRequired current I_kLoad equal to_k-1Required current I_k-1Time-assisted LDO_kOperating in Neutral mode; under Source mode, adjusting tube MP_kOpen, MN_kIs turned off to generate a current I_source-kFrom VDD_kFlow through MP_kTo VOUT_kIs a Load_kProviding additional current to generate current satisfying the relation I_source-k＝I_k-I_k-1(ii) a Under Sink mode, adjusting the pipe MN_kOpen, MP_kIs turned off to generate a current I_sink-kFrom VOUT_kFlows through MN_kTo GND, the flow is extracted to Load_kExcess current, generating current to satisfyThe relationship is I_sink-k＝I_k-1-I_k(ii) a Adjusting the tube MN in Neutral mode_kAnd MP_kIn subthreshold region, assist LDO_kDoes not generate extra current I_source-kOr I_sink-k。

2. The fully integrated multiple output stacked low dropout regulator according to claim 1, wherein an on-chip capacitor C_k-1And Load_k-1Is connected to VOUT_k-1And VOUT_kK 1,2 … n, on-chip capacitance C_nAnd Load_nIs connected to VOUT_nAnd GND.

3. The fully integrated multi-output stacked low dropout regulator according to claim 1, wherein a power supply terminal VDD of the main LDO is connected to an external power supply port, and the auxiliary LDO is connected to an external power supply port_kPower supply terminal VDD of circuit_kThe method comprises the following three connection modes: VDD_kIs connected with VDD; VDD_kAre respectively connected with VOUT_k-1Link, k ═ 1,2 … n; VDD_kAre respectively connected with VOUT_m-1And m is 1,2 … k.

4. The fully integrated multiple output stacked low dropout regulator according to claim 1, wherein an output voltage VOUT is_kAnd VOUT_k-1The difference of (a) is the same or different, k is 1,2 … n.

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