CN109712946B

CN109712946B - Semiconductor package

Info

Publication number: CN109712946B
Application number: CN201910004316.0A
Authority: CN
Inventors: 颜瀚琦; 刘盈男; 李维钧; 林政男
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2013-03-29
Filing date: 2013-03-29
Publication date: 2021-01-19
Anticipated expiration: 2033-03-29
Also published as: CN106024730A; CN103151327A; CN103151327B; CN109712946A; CN106024730B

Abstract

A semiconductor package includes a substrate, a semiconductor chip, a first signal contact, a third signal transmission column, a signal pad, a plurality of ground pads, and a package body. The substrate comprises at least one through hole penetrating through the substrate and the second grounding layer arranged in the substrate and connected with the inner side wall of the through hole. The semiconductor chip is arranged on the substrate. The first signal contact is arranged on the substrate and electrically connected with the semiconductor chip. The third signal transmission column penetrates through the through hole and extends to the first signal contact. The signal connecting pad is formed on the end face of the third signal transmission column. The plurality of grounding connecting pads surround the signal connecting pads and are electrically connected with the second grounding layer. The package body is used for wrapping the semiconductor chip and has an upper surface.

Description

Semiconductor package

The present application is a divisional application of an invention patent application having an application number of "201310109829.0" and entitled "semiconductor package and method for manufacturing the same", which is filed on 29/03/2013 by the applicant. This divisional application is a divisional application of an invention patent application having an application number of "201610347969.5" and an invention name of "semiconductor package and manufacturing method thereof".

Technical Field

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a signal recess.

Background

Semiconductor devices have become more complex due to the demands for increased process speed and size reduction. As the process speed increases and the benefit of small size increases significantly, problems also arise with the characteristics of the semiconductor package. In particular, a higher clock speed (clock speed) leads to more frequent transitions between signal levels (signal levels), and thus to a reduction in the signal strength at high frequencies or short wavelengths. Therefore, how to improve the problem of the high frequency signal strength reduction is one of the important efforts in the industry.

Disclosure of Invention

The invention relates to a semiconductor package which can reduce signal loss.

According to the present invention, a semiconductor package is provided. The semiconductor package comprises a substrate, a semiconductor chip, a first signal contact, a third signal transmission column, a signal pad, a plurality of ground pads and a package body. The substrate comprises at least one through hole penetrating through the substrate and a second grounding layer arranged in the substrate and connected with the inner side wall of the through hole. The semiconductor chip is arranged on the substrate. The first signal contact is arranged on the substrate and electrically connected with the semiconductor chip. The third signal transmission column penetrates through the through hole and extends to the first signal contact. The signal connecting pad is formed on the end face of the third signal transmission column. The plurality of grounding connecting pads surround the signal connecting pads and are electrically connected with the second grounding layer. The packaging body is used for packaging the semiconductor chip and is provided with an upper surface.

In order to make the aforementioned and other objects of the present invention more comprehensible, embodiments accompanied with figures are described in detail as follows:

drawings

Fig. 1A is a cross-sectional view of a semiconductor package according to an embodiment of the invention.

FIG. 1B is a top view of FIG. 1A.

Fig. 2 is a top view of a semiconductor package according to another embodiment of the invention.

Fig. 3 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 4 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 5A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

FIG. 5B is a top view of FIG. 5A.

Fig. 6A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 6B illustrates a top view of fig. 6A.

Fig. 7A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 7B illustrates a bottom view of fig. 7A.

Fig. 8A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 8B illustrates a bottom view of fig. 8A.

Fig. 9 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 10 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the invention.

Fig. 11 is a cross-sectional view of a stacked semiconductor package according to another embodiment of the invention.

Fig. 12A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 12B is a bottom view of the signal transmission element of fig. 12A.

Fig. 13 is a bottom view of a signal transmission element according to another embodiment of the invention.

Fig. 14 is a bottom view of a signal transmission element according to another embodiment of the invention.

Fig. 15 is a bottom view of a signal transmission element according to another embodiment of the invention.

Fig. 16 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 17 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 18A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 18B is a top view of a semiconductor package according to another embodiment of the invention.

Fig. 19A is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 19B illustrates a top view of fig. 19A.

Fig. 20 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 21 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.

Fig. 22A to 22G are process diagrams illustrating the semiconductor package of fig. 5A.

Fig. 23A to 23O are process diagrams illustrating the manufacturing of the semiconductor package of fig. 12A.

Fig. 24A to 24I are process diagrams illustrating the manufacturing of the semiconductor package of fig. 20.

Fig. 25A to 25C are diagrams illustrating a manufacturing process of the semiconductor package of fig. 21.

Description of the main element symbols:

100. 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1200, 1300, 1400, 1500, 1600, 1700: semiconductor package

110. 710, 810, 1210: substrate

110b, 111b, 1210 b: lower surface

110s, 140s, 1250 s: outer side surface

110u, 111u, 1210u, 1250u, 1260u, 140u, 150 u: upper surface of

111: base material

111h, 141h, 150h, 710h, 1210 h: through hole

112: the first composite layer

1121: line layer

1122: dielectric layer

1123: conductive hole

1124: grounding pad

113: second composite layer

1132. 5722: grounding pad

120: a first signal contact

121. 1131, 5721: signal connecting pad

1211: grounding point

1212: first conductive layer

1213: second conductive layer

1250: shielding layer

1250h, 1260 h: opening holes

1260: dielectric layer

1270: antenna layer

1271: feed-in part

1280. 1380: signal transmission element

1281: grounding pole

130: semiconductor chip

131: bonding wire

130 u: active surface

140: package body

140 r: signal groove

140r 1: inner side wall

150: dielectric layer

160. 360: a first ground layer

161: inner side part

162: upper part

163: bottom part

364: outer side part

570: first signal transmission column

571: first pad layer

572: second pad layer

573: part of the material

620: second signal contact

670: second signal transmission column

714: third signal transmission column

715: second ground plane

814: fourth signal transmission column

P1, P2: cutting path

Detailed Description

Referring to fig. 1A, a cross-sectional view of a semiconductor package according to an embodiment of the invention is shown. The semiconductor package 100 includes a substrate 110, a first signal contact 120, a semiconductor chip 130, a package body 140, a dielectric layer 150, and a first ground layer 160. Although not shown, the semiconductor package 100 further includes at least one passive device, such as a resistor, a capacitor, or an inductor.

The substrate 110 includes a substrate 111, a first composite layer 112 and a second composite layer 113, wherein the first composite layer 112 and the second composite layer 113 are respectively formed on an upper surface 111u and a lower surface 111b of the substrate 111. The substrate 111 is, for example, a BT substrate, a glass substrate, a dielectric substrate, or other suitable substrate. The first composite layer 112 includes at least one circuit layer 1121, at least one dielectric layer 1122 and at least one conductive via (conductive via)1123, wherein the dielectric layer 1122 electrically isolates two adjacent circuit layers 1121, and the two adjacent circuit layers 1121 can be electrically connected through the corresponding conductive via 1123. The structure of the second composite layer 113 may be similar to that of the first composite layer 112, and thus, the description thereof is omitted.

The first signal contact 120 is formed on the upper surface 110u of the substrate 110, which may be a portion of the circuit layer 1121. The first signal contact 120 can be electrically connected to the semiconductor chip 130 through the circuit layer 1121 and the conductive via 1123, such that a signal can be transmitted between the first signal contact 120 and the semiconductor chip 130. In addition, the semiconductor package 100 further includes a signal pad 121 formed on the first signal contact 120. The signal pad 121 and the first ground layer 160 can be formed in the same process with the same material at one time. In another example, the signal pad 121 may be omitted.

The semiconductor chip 130 is, for example, a wireless signal transceiver chip such as a Radio Frequency (RF) chip or other kinds of chips. The semiconductor chip 130 is disposed on the upper surface 110u of the substrate 110 with the active surface 130u facing upward, and is electrically connected to the first composite layer 112 through at least one bonding wire 131. The semiconductor chip 130 can be electrically connected to the first signal contact 120 through the bonding wire 131 and the circuit layer 1121 of the substrate 110. In another example, the semiconductor chip 130 is, for example, a flip chip (flip chip), which is disposed on the upper surface 110u of the substrate 110 with the active surface 130u facing downward and electrically connected to the first composite layer 112 through at least one solder ball.

The package 140 is formed on the upper surface 110u of the substrate 110 and covers the semiconductor chip 130. The package 140 has an upper surface 140u and at least one signal groove 140r, and the signal groove 140r extends from the upper surface 140u of the package 140 to the first signal contact 120 and the upper surface 110u of the substrate 110 to expose the first signal contact 120.

The encapsulant 140 may include phenolic-based resin (Novolac-based resin), epoxy-based resin (epoxy-based resin), silicone-based resin (silicone-based resin), or other suitable coating agent. The package 140 may also include a suitable filler, such as powdered silicon dioxide. The package body 140 may be formed by several packaging techniques, such as compression molding (compression molding), injection molding (injection molding) or transfer molding (transfer molding).

Due to the removal of the package material, the signal transmitted in the signal recess 140r is not interfered by the package 140. The dielectric layer 150 is selectively formed in the signal recess 140r, thereby improving the transmission of signals in the signal recess 140 r. For example, the dielectric layer 150 is a waveguide medium that may fill at least a portion of the signal recess 140 r. Preferably, but not limited to, the dielectric layer 150 may be made of a low loss material. After entering the dielectric layer 150, the external signal is propagated in the dielectric layer 150 and then transmitted to the semiconductor chip 130 through the first signal contact 120; alternatively, the signal from the semiconductor chip 130 is transmitted to the dielectric layer 150, then is propagated in the dielectric layer 150, and then is radiated from the dielectric layer 150 to the outside. Further, even if the physical or mechanical conductive traces are omitted, the signal can still be conducted within the dielectric layer 150 between the first signal contact 120 and the upper surface 150u of the dielectric layer 150 through the waveguide property of the dielectric layer 150.

The first ground layer 160 includes an inner side portion 161 formed on the inner side wall 140r1 of the signal groove 140 r. The inner portion 161 may confine the signal within the signal groove 140r, reduce signal loss or maintain signal strength. In addition, since the inner portion 161 can shield external electromagnetic interference, the signal transmitted in the signal groove 140r is not easily affected. In addition, in this embodiment, the inner portion 161 is a closed annular ground layer, which is formed to surround the inner sidewall 140r1 of the signal groove 140r in a closed manner; in another example, the inner portion 161 may be an open circular ground plane.

The first ground layer 160 further includes an upper portion 162 formed on the upper surface 140u of the package body 140 and extending between the signal groove 140r and the outer side surface 140s of the package body 140. In this embodiment, the first ground layer 160 extends to the outer side surface 140s of the package body 140 and is aligned with, e.g., coplanar with, the outer side surface 140s of the package body 140; but may be misaligned. In one example, the upper portion 162 may cover the entire upper surface 140u of the package body 140 to completely overlap the semiconductor chip 130, thereby improving the emi protection. In another example, the upper portion 162 of the first ground layer 160 may be omitted.

The first ground layer 160 further includes a bottom portion 163 formed on the circuit layer 1121 of the substrate 110. The bottom portion 163 is electrically connected to an external ground (not shown) through the circuit layer 1121, the conductive hole 1123, the conductive hole 1111 of the substrate 111 and the second composite layer 113, so as to ground the first ground layer 160. In another example, the bottom portion 163 may be omitted from the first ground layer 160.

Referring to fig. 1B, a top view of fig. 1A is shown. The cross-section of the signal groove 140r is, for example, circular, but this is not intended to limit the present invention, and in another example, the cross-section of the signal groove 140r is oval or polygonal, wherein the polygonal is, for example, triangular, rectangular or other polygonal.

Referring to fig. 2, a top view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 200 includes a substrate 110 (not shown), a first signal contact 120, a semiconductor chip 130 (not shown), a package body 140, a dielectric layer 150 (not shown), and a first ground layer 160.

In this embodiment, the cross-sectional shape of the signal recess 140r of the package 140 is rectangular, but may be polygonal with other geometric shapes, such as pentagonal, hexagonal, etc. The cross-sectional shape of the signal groove 140r is not particularly limited by the embodiments of the present invention.

Referring to fig. 3, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 300 includes a substrate 110, a first signal contact 120, a semiconductor chip 130, a package body 140, a dielectric layer 150, and a first ground layer 360.

The first ground layer 360 includes an inner portion 161, an upper portion 162, a bottom portion 163, and an outer portion 364, wherein the outer portion 364 is formed on the outer side 140s of the package 140 and the outer side 110s of the substrate 110 and extends between the upper surface 140u of the package 140 and the lower surface 110b of the substrate 110. In this example, the outer portion 364 extends from the upper surface 140u of the package body 140 to the lower surface 110b of the substrate 110. The outer portion 364 covers the circuit layer 1121 on the outer side surface 110s of the substrate 110 to electrically connect to an external ground terminal through the circuit layer 1121, so as to ground the first ground layer 360.

Referring to fig. 4, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 400 includes a substrate 110, a first signal contact 120, a semiconductor chip 130, a package body 140, a dielectric layer 150, and a first ground layer 160.

In this example, the first signal contact 120 is formed on the active surface 130u of the semiconductor chip 130. The signal recess 140r of the package body 140 extends from the upper surface 140u of the package body 140 to the first signal contact 120 formed on the semiconductor chip 130 to expose the first signal contact 120. The dielectric layer 150 fills at least a portion of the signal recess 140r, and a signal can propagate within the dielectric layer 150.

Referring to fig. 5A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 500 includes a substrate 110, a first signal contact 120, a semiconductor chip 130, a package body 140, a dielectric layer 150, a first ground layer 160, and a first signal transmission pillar 570.

In this example, the dielectric layer 150 may be epoxy (epoxy) or a material similar to the package body 140, which may fill the groove space between the first signal transmission post 570 and the first ground layer 160. The inner side portion 161 of the first ground layer 160 surrounds the first signal transmission post 570 and is disposed coaxially with the first signal transmission post 570 (CVS); but may also be arranged off-axis. In this example, the inner portion 161 of the first ground layer 160 and the first signal transmission pillar 570 are located in the same lateral structure layer, so that a vertical space is not occupied, that is, the first signal transmission pillar 570 does not increase the height of the semiconductor package 100.

The first signal transmitting pillars 570 are, for example, Through Molding Vias (TMV), which extend from the upper surface 150u of the dielectric layer 150 to the signal pads 121 and are electrically connected to the semiconductor chip 130 Through the signal pads 121, the first signal contacts 120, the conductive vias 1123 and the circuit layer 1121. In another example, the signal pad 121 can be omitted, such that the first signal transmitting pillar 570 extends directly from the upper surface 150u of the dielectric layer 150 to the first signal contact 120. By designing the outer diameter of the first signal transmission post 570, the inner diameter of the inner portion 161 of the first ground layer 160, and the dielectric constant of the dielectric layer 150, an impedance match of about 50 ohms can be obtained, and the waveguide electromagnetic mode exceeds the desired operating frequency to avoid mode conversion; in another example, the waveguide electromagnetic mode can exceed 70GHz (the desired operating frequency) and can be less than 70GHz, such as between 40GHz and 69GHz, if properly designed.

Referring to fig. 5B, a top view of fig. 5A is shown. In this embodiment, the cross-sectional shape of the first signal transmission post 570 is circular, but may also be oval or polygonal, such as triangular, rectangular or other polygonal shapes.

Referring to fig. 6A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 600 includes a substrate 110, a first signal contact 120, a second signal contact 620, a semiconductor chip 130, a package body 140, a dielectric layer 150, a first ground layer 160, a first signal transmission pillar 570, and a second signal transmission pillar 670. The semiconductor package 600 of this embodiment is different from the semiconductor package 100 in that two signal transmission pillars, such as the first signal transmission pillar 570 and the second signal transmission pillar 670, are formed in one signal groove 140 r.

The first signal contact 120 and the second signal contact 620 are formed on the upper surface 110u of the substrate 110, which may be a portion of the circuit layer 1121 of the substrate 110. The material and structure of the second signal contact 620 may be similar to those of the first signal contact 120, and thus, the description thereof is omitted.

The dielectric layer 150 fills the groove space between the first signal transmitting post 570, the second signal transmitting post 670 and the first ground layer 160.

The second signal transmission pillars 670 are, for example, through-mold vias, which extend from the upper surface 150u of the dielectric layer 150 to the signal pads 121 and the upper surface 110u of the substrate 110, and are electrically connected to the semiconductor chip 130 through the signal pads 121, the second signal contacts 620, the conductive vias 1123 and the circuit layer 1121. In another example, the signal pad 121 can be omitted, such that the second signal transmitting pillar 670 extends directly from the upper surface 150u of the dielectric layer 150 to the second signal contact 620. The semiconductor chip 130 can control the phase difference of the signals transmitted to the first signal transmitting post 570 and the second signal transmitting post 670 by 180 degrees. In addition, the material and structure of the second signal transmitting pillar 670 may be similar to those of the first signal transmitting pillar 570, and thus the description thereof is omitted.

Referring to fig. 6B, a top view of fig. 6A is shown. In this embodiment, the cross-sectional shape of the second signal transmission post 670 is circular, but may also be oval or polygonal, such as triangular, rectangular or other polygonal shapes. In addition, the cross-sectional shape of the signal recess 140r of the package 140 is elliptical, but may also be circular or polygonal, wherein the polygonal is triangular, rectangular or other polygonal.

Referring to fig. 7A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 700 includes a substrate 710, a first signal contact 120, a semiconductor chip 130, and a package body 140.

The substrate 710 includes a substrate 111, a first composite layer 112 and a second composite layer 113, a third signal transmission pillar 714 and a second ground layer 715, and has at least one through hole 710 h. The through hole 710h penetrates the entire thickness of the substrate 710. The third signal transmission pillar 714 penetrates through the through hole 710h and extends to the first signal contact 120, so that the semiconductor chip 130 can be electrically connected to an external circuit (not shown) through the first signal contact 120 and the third signal transmission pillar 714.

The second grounding layer 715 is formed on the inner sidewall of the through hole 710h, the upper surface 111u and the lower surface 111b of the substrate 111, and is electrically connected to an external ground (not shown) through the conductive hole 1123, so that the second grounding layer 715 is grounded. The technical effect of the second ground layer 715 is similar to that of the first ground layer 160, and thus, the description thereof is omitted.

Referring to fig. 7B, a bottom view of fig. 7A is shown. The second composite layer 113 includes at least one signal pad 1131 and a plurality of ground pads 1132, the signal pad 1131 is formed on an end surface of the third signal transmission pillar 714, and the ground pads 1132 surround the signal pad 1131 separately. In addition, the cross-sectional shape of the through hole 710h is circular, but may also be oval or polygonal, such as triangular, rectangular or other polygonal shapes.

Referring to fig. 8A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 800 includes a substrate 810, a first signal contact 120, a semiconductor chip 130, and a package body 140.

The substrate 810 includes a substrate 111, a first composite layer 112 and a second composite layer 113, at least one third signal transmission pillar 714, a second ground layer 715 and at least one fourth signal transmission pillar 814, and has at least one through hole 710 h. The through hole 710h penetrates the entire thickness of the substrate 710. The fourth signal transmitting pillar 814 passes through the through hole 710h and extends to the first signal contact 120, so that the semiconductor chip 130 can be electrically connected to an external circuit (not shown) through the first signal contact 120 and the fourth signal transmitting pillar 814.

The second ground layer 715 is formed on the inner sidewall of the through hole 710h, surrounding the third signal transmitting pillar 714 and the fourth signal transmitting pillar 814.

Referring to fig. 8B, a bottom view of fig. 8A is shown. The second composite layer 113 (fig. 8A) includes a plurality of signal pads 1131 and a plurality of ground pads 1132, the two signal pads 1131 are respectively formed on the end surface of the third signal transmission pillar 714 and the end surface of the fourth signal transmission pillar 814, and the ground pads 1132 separately surround the signal pads 1131. In addition, the cross-sectional shape of the through hole 710h is oval, but may also be circular or polygonal, such as triangular, rectangular or other polygonal shapes.

Referring to fig. 9, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 900 includes a substrate 710, a first signal contact 120, a semiconductor chip 130, a package body 140, a dielectric layer 150, a first ground layer 160, and a first signal transmission pillar 570.

The first signal transmitting pillar 570 is electrically connected to the third signal transmitting pillar 714, so that signals can be transmitted among the semiconductor chip 130, the first signal transmitting pillar 570 and the third signal transmitting pillar 714. In this example, the first signal transmitting post 570 is butted against the third signal transmitting post 714, that is, the first signal transmitting post 570 and the third signal transmitting post 714 are arranged in a straight line direction, so that the signal transmission path is shortest. In another example, the first signal transmitting post 570 and the third signal transmitting post 714 may be arranged in a left-right staggered manner and electrically connected to each other through the first composite layer 112.

Referring to fig. 10, a cross-sectional view of a stacked semiconductor package according to another embodiment of the invention is shown. The stacked semiconductor package 1000 includes two semiconductor packages 100 butted in a manner that the signal grooves 140r are opposite to each other, so that signals between the two semiconductor packages 100 can be transmitted through the two opposite signal grooves 140 r. Although not shown, a solder is included between the two semiconductor packages 100 to solder the two semiconductor packages 100.

Referring to fig. 11, a cross-sectional view of a stacked semiconductor package according to another embodiment of the invention is shown. The stacked semiconductor package 1100 includes the semiconductor packages 500 and 900, wherein the first signal transmission post 570 of the semiconductor package 500 is connected to the third signal transmission post 714 of the semiconductor package 900, so that signals between the two

semiconductor packages

500 and 900 can be transmitted through the first signal transmission post 570 and the third signal transmission post 714. In this example, the first signal transmission post 570 and the third signal transmission post 714 of the semiconductor package 900 and the first signal transmission post 570 of the semiconductor package 500 are arranged in a straight line direction so that the signal transmission path is the shortest.

Although the stacked semiconductor packages of the above embodiments are illustrated by stacking the semiconductor packages 100, 500, and 900, in another example, at least two of the semiconductor packages 100 to 900 may be stacked on each other; alternatively, a plurality of identical semiconductor packages may be stacked on top of each other.

Referring to fig. 12A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1200 includes a substrate 1210, a first signal contact 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, a dielectric layer 1260, an antenna layer 1270, a feed-in (feed point)1271, and at least one signal transmission element 1280.

The substrate 1210 is a multi-layer structure, for example, and includes at least one circuit layer 1121 and at least one conductive via 1123. In another example, the substrate 1210 may have a single layer structure. The substrate 1210 further includes at least one grounding point 1211 formed on the upper surface 1210u of the substrate 1210 and electrically connected to an external ground (not shown) through the circuit layer 1121 and the conductive hole 1123; in another example, the ground 1211 may extend between the upper surface 1210u and the lower surface 1210b of the substrate 1210.

The first signal contact 120 is formed on the substrate 1210 and electrically connected to the semiconductor chip 130 through the circuit layer 1121 and the conductive via 1123 of the substrate 1210. The semiconductor chip 130 is disposed on the substrate 1210 and electrically connected to the substrate 1210 through the bonding wire 131.

The shielding layer 1250 is formed on the outer surface 140s and the upper surface 140u of the package body 140, and is electrically connected to the grounding point 1211 of the substrate 1210, so that the shielding layer 1250 is grounded.

The shielding layer 1250 is made of aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel or a combination thereof, and can be made by using a Chemical Vapor Deposition (CVD), electroless plating (electroless plating), electroplating, printing (printing), spraying (sputtering), sputtering or vacuum Deposition (vacuum Deposition).

The dielectric layer 1260 is formed of low-loss low-k material, such as Teflon (Teflon), Polytetrafluoroethylene (PTEE), and Polystyrene (Polystyrene), for example. The dielectric layer 1260 covers the upper surface 1250u of the shielding layer 1250 and has at least one opening 1260 h. An antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260. The feeding element 1271 is connected to the antenna layer 1270 and the first signal transmitting pillar 570 through the opening 1260h, such that the antenna layer 1270 is electrically connected to the semiconductor chip 130 through the feeding element 1271, the first signal transmitting pillar 570, the first signal contact 120, the circuit layer 1121, the conductive via 1123 and the bonding wire 131.

The signal transmission element 1280 is electrically connected to the first signal contact 120, and is electrically connected to the semiconductor chip 130 through the first signal contact 120, the conductive via 1123, the circuit layer 1121, and the bonding wire 131.

The signal transmission element 1280 includes at least one first signal transmission post 570, at least one ground post 1281, a dielectric layer 150, a first pad layer 571 and a second pad layer 572, and the signal transmission element 1280 is, for example, a surface mount device or an Interposer (Interposer). The first signal transmitting post 570 and the ground post 1281 penetrate the entire dielectric layer 150, and the first signal transmitting post 570 is electrically connected to the first signal contact 120 and electrically connected to the semiconductor chip 130 through the first signal contact 120.

Referring to fig. 12B, a bottom view of the signal transmitting device in fig. 12A is shown. The ground posts 1281 surround the first signal transmitting post 570 separately from each other to provide emi protection for the first signal transmitting post 570. In this embodiment, the plurality of ground pins 1281 are arranged in a circle around the first signal transmitting pin 570, but this is not intended to limit the present invention. In addition, the second pad layer 572 includes signal pads 5721 and ground pads 5722, wherein the signal pads 5721 are formed on the end surface of the first signal transmission pillars 570, and the ground pads 5722 are formed in a closed loop shape on the end surface of each ground pillar 1281, so as to electrically connect all the ground pillars 1281 at the same time. In another example, the ground pad 5722 may comprise a plurality of separate sub-pad layers, each formed on an end surface of a corresponding ground pillar 1281.

Referring to fig. 13, a bottom view of a signal transmission element according to another embodiment of the invention is shown. In this example, the signal transmitting element 1280 includes a plurality of ground posts 1281 and a first signal transmitting post 570, wherein the plurality of ground posts 1281 are arranged in a rectangular shape surrounding the first signal transmitting post 570.

Referring to fig. 14, a bottom view of a signal transmission element according to another embodiment of the invention is shown. In this example, the signal transmitting member 1280 includes a single ground post 1281 and a first signal transmitting post 570, wherein the ground post 1281 is a closed circular ring-shaped post that closely surrounds the first signal transmitting post 570.

Referring to fig. 15, a bottom view of a signal transmission element according to another embodiment of the invention is shown. In this example, the signal transmitting element 1280 includes a single ground post 1281 and a first signal transmitting post 570, wherein the ground post 1281 is a closed rectangular ring-shaped post that closely surrounds the first signal transmitting post 570.

Referring to fig. 16, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1300 includes a substrate 1210, a first signal contact 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, a dielectric layer 1260, an antenna layer 1270, and a signal transmission element 1380.

Compared to the semiconductor package 1200, the signal transmitting device 1380 of the semiconductor package 1300 of the present embodiment omits the first signal transmitting stud 570, and the semiconductor package 1200 omits the feeding element 1271. The dielectric layer 150 of the signal transmitting element 1280 may be formed of a waveguide material to help improve signal transmission. The shielding layer 1250 has an opening 1250h that is directly over the dielectric layer 150 of the signal transmitting element 1380. The signal of the semiconductor chip 130 can be transmitted into the dielectric layer 150 through the first signal contact 120, and is propagated to the opening 1250h in the dielectric layer 150, and then the shielding layer 1250 and the antenna layer 1270 induce the signal by the electromagnetic induction principle, and the signal is radiated to the outside by the antenna layer 1270. Further, even if the physical or mechanical conductive trace is omitted, the signal transmission between the antenna layer 1270 and the first signal contact 120 can be achieved by electromagnetic induction. In addition, the opening 1250h is vertically aligned with the first signal contact 120 to make the signal transmission path shorter or shortest.

Referring to fig. 17, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1400 includes a substrate 1210, a first signal contact 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, and at least one signal transmission element 1380.

In contrast to the semiconductor package 1300, the semiconductor package 1400 of the present embodiment omits the dielectric layer 1260 and the antenna layer 1270. The signal of the semiconductor chip 130 can be transmitted into the dielectric layer 150 through the first signal contact 120, and then propagated to the opening 1250h in the dielectric layer 150 and radiated to the outside.

Referring to fig. 18A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1500 includes a substrate 1210, at least two first signal contacts 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, and at least two signal transmission elements 1380.

In contrast to the semiconductor package 1400, the semiconductor package 1500 of the present embodiment includes a plurality of signal transmission elements 1380, each of which is disposed on a corresponding first signal contact 120.

Referring to fig. 18B, a top view of a semiconductor package according to another embodiment of the invention is shown. The signal transmission elements 1380 are arranged in two rows and located at two opposite sides of the semiconductor chip 130. By increasing the number of signal transmission elements 1380, the signal strength of the semiconductor package 1500 may be increased.

Referring to fig. 19A, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1600 includes a substrate 1210, at least one first signal contact 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, and at least one signal transmission element 1380.

The substrate 1210 includes a circuit layer 1121' electrically connected to the semiconductor chip 130 for transmitting signals of the semiconductor chip 130. For the input signal, the external signal is transmitted into the dielectric layer 150 of the signal transmission element 1380 through the opening 1250h of the shielding layer 1250, and is transmitted to the circuit layer 1121 'of the substrate 1210 through wave conduction between the plurality of ground posts 1281 of the signal transmission element 1380, and the circuit layer 1121' induces the signal through electromagnetic induction, and then transmits the signal to the semiconductor chip 130. For the output signal, the signal of the semiconductor chip 130 is transmitted to the circuit layer 1121', enters the dielectric layer 150, and is laterally conducted between the ground studs 1281 in the direction of the opening 1250h, and then is radiated through the opening 1250h of the shielding layer 1250.

Referring to fig. 19B, a top view of fig. 19A is shown. The grounding posts 1281 of the signal transmission element 1380 are arranged in n-shape, and the circuit layer 1121' of the substrate 1210 extends between two opposite rows of the n-shape to receive signals from the dielectric layer 150 (fig. 19A) or transmit signals of the semiconductor chip 130 to the dielectric layer 150. In addition, the substrate 1210 includes at least one grounding pad 1124, and a single grounding pad 1124 may be electrically connected to all grounding studs 1281 of a single signal transmission element 1380, but the embodiment of the present invention is not limited to the shape of the grounding pad 1124 as long as all grounding studs 1281 of a single signal transmission element 1380 can be electrically connected at one time. In addition, the grounding pad 1124 has a n-shaped opening facing the circuit layer 1121 ', and the circuit layer 1121' overlaps with the n-shaped opening.

Referring to fig. 20, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1700 includes a substrate 1210, a first signal contact 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, a dielectric layer 1260, an antenna layer 1270, and at least one ground stud 1281.

In contrast to the semiconductor package 1300 (fig. 16), the ground post 1281 of the present embodiment is not formed in the signal transmission element 1280, but is integrated into the semiconductor package 1400, and in detail, the ground post 1281 directly extends from the upper surface 140u of the package body 140 to the ground pad 1124 of the substrate 1210. The grounding pad 1124 is electrically connected to a ground terminal, such that the shielding layer 1250 is grounded via the grounding pin 1281 and the grounding pad 1124. In addition, the circuit layer 1121' of the substrate 1210 can be electrically connected to the semiconductor chip 130 through the conductive via 1123.

The shielding layer 1250 has at least one opening 1250h located between the ground posts 1281, such that a signal received by the antenna layer 1270 can enter between the first signal transmission posts 570 from the opening 1250h, or a signal output from the semiconductor chip 130 can radiate out from the opening 1250h after being conducted between the ground posts 1281. In this embodiment, the package 140 is, for example, a waveguide material, which fills the space between the ground posts 1281, so that signals can be propagated between the ground posts 1281.

The dielectric layer 1260 covers the upper surface 1250u and the outer surface 1250s of the shielding layer 1250, i.e., the dielectric layer 1260 covers the entire shielding layer 1250 to completely protect the shielding layer 1250. The antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260 and disposed corresponding to the opening 1250h of the shielding layer 1250 such that a transmission path of a signal between the antenna layer 1270 and the opening 1250h is short or shortest.

Referring to fig. 21, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 1800 includes a substrate 1210, a first signal contact 120, a semiconductor chip 130, a package body 140, a shielding layer 1250, a dielectric layer 1260, an antenna layer 1270 and a plurality of first signal transmission pillars 570.

Compared to the semiconductor package 1700 (fig. 20), the dielectric layer 1260 of this example covers the upper surface 1250u of the shielding layer 1250, but does not cover the outer side surface of the shielding layer 1250.

Referring to fig. 22A to 22G, a process diagram of manufacturing the semiconductor package of fig. 5A is shown.

As shown in fig. 22A, at least one semiconductor chip 130 is disposed on the substrate 110 by, for example, Surface Mount Technology (SMT), and the semiconductor chip 130 and the substrate 110 are electrically connected by at least one bonding wire 131.

The substrate 110 includes a substrate 111, a first composite layer 112 and a second composite layer 113, wherein the first composite layer 112 and the second composite layer 113 are respectively formed on an upper surface 111u and a lower surface 111b of the substrate 111. The substrate 111 is, for example, a BT substrate, a glass substrate, a dielectric substrate, or other suitable substrate. The first composite layer 112 includes at least one circuit layer 1121, at least one dielectric layer 1122 and at least one conductive via (conductive via)1123, wherein the dielectric layer 1122 isolates two adjacent circuit layers 1121, and the two adjacent circuit layers 1121 can be electrically connected through the corresponding conductive via 1123. The structure of the second composite layer 113 may be similar to that of the first composite layer 112, and thus, the description thereof is omitted. In addition, the first signal contact 120 is formed on the upper surface 110u of the substrate 110, which may be a part of the circuit layer 1121.

As shown in fig. 22A, a package body 140 is formed to cover the semiconductor chip 130 and the bonding wires 131 by, for example, compression molding, injection molding or transfer molding.

As shown in fig. 22B, at least one signal recess 140r is formed in the package body 140 by, for example, laser drilling, jet (tapping) drilling or mechanical drilling, wherein the signal recess 140r extends from the upper surface 140u of the package body 140 to the first signal contact 120 to expose the first signal contact 120.

As shown in fig. 22C, the first ground layer 160 and the signal pads 121 are formed by, for example, a material forming technique. The first ground layer 160 includes an inner portion 161, an upper portion 162 and a bottom portion 163, wherein the inner portion 161 is formed on the inner sidewall 140r1 of the signal groove 140r, the upper portion 162 is formed on the upper surface 140u of the package body 140, and the bottom portion 163 is formed on the circuit layer 1121 of the substrate 110. The signal pad 121 is formed on the first signal contact 120.

The material forming technique is, for example, chemical vapor deposition, electroless plating (electro plating), electrolytic plating (electro plating), printing, spin coating, spray coating, sputtering (sputtering), or vacuum deposition (vacuum deposition).

As shown in fig. 22D, a dielectric layer 150 is formed by glue filling to fill the signal recess 140r, in this example, the dielectric layer 150 may be an epoxy resin. Thus, the structure of the semiconductor package 100 of fig. 1A is formed. The following continues to describe a method of manufacturing the semiconductor package 500 of fig. 5A.

As shown in fig. 22E, at least one via 150h is formed through the corresponding dielectric layer 150 by, for example, a laser, a spray or a cutter, wherein the via 150h extends from the upper surface 150u of the dielectric layer 150 to the signal pad 121. In another example, if the signal pad 121 is omitted, the through hole 150h extends directly from the upper surface 150u of the dielectric layer 150 to the first signal contact 120.

As shown in fig. 22F, a first signal transmitting post 570 is formed within the via 150h, for example, using the material formation techniques described above, wherein a portion 573 of the first signal transmitting post 570 protrudes above the upper surface 150u of the dielectric layer 150.

Then, the upper portion 162 of the first ground layer 160 is patterned, for example, by a patterning technique, to obtain a predetermined pattern. In addition, the edges of portions of material 573 may be simultaneously modified during the patterning step to obtain the appropriate or desired dimensions. Examples of patterning techniques are photolithography, chemical etching, laser drilling, or mechanical drilling.

As shown in fig. 22G, at least one scribe line P1 is formed through the first ground layer 160, the package body 140 and the substrate 110 by, for example, a cutter or a laser, so as to form at least one semiconductor package 500 shown in fig. 5A.

The manufacturing methods of the semiconductor packages 200, 300, 400, and 600 are similar to the manufacturing method of the semiconductor package 500 of fig. 5A, and thus the description thereof is omitted.

In the manufacturing process of the semiconductor package 700, the substrate 710 may replace the substrate 110 shown in fig. 22A, and the formation steps of the signal recess 140r (fig. 22B), the first ground layer 160 (fig. 22C), the dielectric layer 150 (fig. 22D), the via hole 150h (fig. 22E) and the first signal transmission pillar 570 (fig. 22F) are omitted.

The manufacturing process of the semiconductor package 800 is similar to that of the semiconductor package 700, and thus is not described herein again.

In a manufacturing process of the semiconductor package 900, the substrate 710 may replace the substrate 110 of fig. 22A, so that the semiconductor package 900 may be formed.

Referring to fig. 23A to 23O, a process diagram of the semiconductor package of fig. 12A is shown.

As shown in fig. 23A, a substrate 1200 is provided, the substrate 1200 includes a substrate 111, a first conductive layer 1212 and a second conductive layer 1213, and the first conductive layer 1212 and the second conductive layer 1213 respectively cover the entire upper surface 111u and the entire lower surface 111b of the substrate 111. In this example, the substrate 111 may be an insulator.

As shown in fig. 23B, at least one through hole 1210h is formed through the entire substrate 1200, for example, by laser drilling, jet drilling, or mechanical drilling.

As shown in fig. 23C, a grounding post 1281 is formed on the inner sidewall of the via 1210h by, for example, electroplating, wherein the grounding post 1281 is connected to the first conductive layer 1212 and the second conductive layer 1213.

As shown in fig. 23D, a dielectric layer 150 is formed to fill the via 1210h, for example, by glue filling.

As shown in fig. 23E, at least one via 150h is formed through the entire dielectric layer 150, for example, by laser drilling, jet drilling, or mechanical drilling.

As shown in fig. 23F, by using the above-mentioned material forming techniques, a first signal transmitting pillar 570, a first pad layer 571 and a second pad layer 572 are formed, wherein the through hole 150h is filled with the first signal transmitting pillar 570, and the first pad layer 571 and the second pad layer 572 respectively cover the first conductive layer 1212 and the second conductive layer 1213 and are electrically connected to the first signal transmitting pillar 570.

As shown in fig. 23G, the first conductive layer 1212 and the second conductive layer 1213 are patterned by the above-mentioned patterning technique to electrically isolate the first signal transmitting stud 570 from the ground stud 1281. After patterning, the first conductive layer 1212 and the second conductive layer 1213 form a first pad layer 571 and a second pad layer 572, respectively, each of which includes at least one pad.

As shown in fig. 23H, at least one scribe line P1 is formed through the substrate 111, the first conductive layer 1212, and the second conductive layer 1213 by, for example, a knife or a laser, so as to form at least one signal transmission element 1280 shown in fig. 12A.

As shown in fig. 23I, a substrate 1210 is provided. The substrate 1210 is a multi-layer structure, for example, and includes at least one circuit layer 1121 and at least one conductive via 1123. In another example, the substrate 1210 may have a single layer structure. In addition, the substrate 1210 further includes at least one grounding point 1211 formed protruding from the upper surface 1210u of the substrate 1210; in another example, the ground 1211 may extend between the upper surface 1210u and the lower surface 1210b of the substrate 1210.

As shown in fig. 23I, at least one semiconductor chip 130 is disposed on the substrate 110 by, for example, a surface mount technology, and the semiconductor chip 130 is electrically connected to the substrate 1210 by at least one bonding wire 131.

As shown in fig. 23I, the signal transmission element 1280 of fig. 23H is disposed on the substrate 1210 by, for example, a surface mount technology, wherein the second pad layer 572 and the first signal transmission post 570 of the signal transmission element 1280 are electrically connected to the circuit layer 1121 (the circuit layer 1121 separated from the first signal contact 120) and the first signal contact 120, respectively. The second pad layer 572 is grounded through the wiring layer 1121.

As shown in fig. 23J, the package body 140 is formed by compression molding, injection molding or transfer molding, for example, to encapsulate the semiconductor chip 130, the bonding wires 131 and the signal transmission element 1280.

As shown in fig. 23K, the upper material of the package body 140 is removed by, for example, grinding, to form the upper surface 140u of the package body 140, wherein the first pad layer 571 of the signal transmission element 1280 is exposed from the upper surface 140u of the package body 140.

As shown in fig. 23L, at least one scribe line P1 is formed through the package body 140 by, for example, a knife or a laser until the grounding points 1211 of the substrate 1210 are exposed. Since the cutting path P1 does not completely cut the substrate 1210, this cutting method is called "half-cut". In another example, the scribe line P1 may be cut through the entire package 140 and the entire substrate 1210, and this cutting method is called "full-cut".

As shown in fig. 23M, the shielding layer 1250 is formed to cover the outer surface 140s and the upper surface 140u of the package body 140 by the above-mentioned material forming technique.

As shown in fig. 23N, a dielectric layer 1260 is formed overlying the upper surface 1250u of the shielding layer 1250, for example, by a coating technique.

As shown in fig. 23N, the antenna layer 1270 is formed on the top surface 1260u of the dielectric layer 1260 and the feeding element 1271 is formed in the opening 1260h of the dielectric layer 1260 by the above-mentioned material forming technique, such that the antenna layer 1270 is electrically connected to the first signal transmitting pillar 570 through the feeding element 1271.

As shown in fig. 23O, at least one scribe line P2 is formed through the substrate 1210 to form at least one semiconductor package 1200 as shown in fig. 12A.

In the manufacturing process of the semiconductor package 1300 (fig. 16), the formation steps of the through hole 150h (fig. 23E), the first signal transmission pillar 570 (fig. 23F), the opening 1260h and the feeding portion 1271 are omitted, and the remaining manufacturing steps are similar to the corresponding steps of manufacturing the semiconductor package 1200, and are not repeated herein.

In the manufacturing process of the semiconductor package 1400 (fig. 17), compared to the manufacturing process of the semiconductor package 1300, the steps of forming the dielectric layer 1260 and the antenna layer 1270 may be omitted, and the remaining manufacturing steps are similar to the corresponding steps of manufacturing the semiconductor package 1300, and thus are not repeated herein.

The manufacturing process of the

semiconductor packages

1500 and 1600 is similar to that of the semiconductor package 1400, and thus the description thereof is omitted.

Referring to fig. 24A to 24I, a process diagram of the semiconductor package of fig. 20 is shown.

As shown in fig. 24A, a substrate 1210 is provided, wherein the substrate 1210 has a multi-layer structure, and includes at least one circuit layer 1121, at least one conductive hole 1123, at least one grounding point 1211 and at least one grounding pad 1124.

As shown in fig. 24A, at least one semiconductor chip is disposed on a substrate 1210 by, for example, a surface mount technology.

As shown in fig. 24B, the package body 140 is formed to cover the semiconductor chip 130 and the ground pad 1124 by compression molding, injection molding or transfer molding, for example.

As shown in fig. 24C, at least one through hole 141h is formed to extend from the upper surface 140u of the package body 140 to the grounding pad 1124 by the above-mentioned patterning technique, for example, so as to expose the grounding pad 1124.

As shown in fig. 24D, at least one ground post 1281 is formed to fill the corresponding via 141h, such as by the material forming techniques described above, such that ground post 1281 is grounded via ground pad 1124.

As shown in fig. 24E, at least one scribe line P1 is formed, for example, by a tool or a laser, to extend from the upper surface 140u of the package body 140 to the ground 1211 and expose the ground 1211. Since the cutting path P1 does not cut through the entire structure, this cutting method is called "half-through cutting". In another example, the entire substrate 1210 may be cut by the full-through cutting method, i.e., the scribe line P1.

As shown in fig. 24F, a shielding layer 1250 is formed on the outer surface 140s and the upper surface 140u of the package body 140 by using the above-mentioned material forming technique, for example, wherein the shielding layer 1250 is electrically connected to the ground 1211. The shielding layer 1250 has at least one opening 1250h located between the ground posts 1281.

As shown in fig. 24G, a dielectric layer 1260 is formed to cover the upper surface 1250u and the outer surface 1250s of the shielding layer 1250 by, for example, a coating technique.

As shown in fig. 24H, an antenna layer 1270 is formed on the top surface 1260u of the dielectric layer 1260 by a material forming technique such as that described above, wherein the antenna layer 1270 is positioned opposite to the opening 1250H, such that the signal transmission distance between the antenna layer 1270 and the opening 1250H is minimized and the loss is minimized.

As shown in fig. 24I, at least one scribe line P2 is formed through the dielectric layer 1260 and the substrate 1210 by, for example, a knife or a laser, to form at least one semiconductor package 1700 as shown in fig. 20.

Referring to fig. 25A to 25C, a process of manufacturing the semiconductor package of fig. 21 is illustrated.

As shown in fig. 25A, dielectric layer 1260 is formed, for example, by a coating technique, to cover upper surface 1250u of shielding layer 1250, but to expose outer surface 1250s of shielding layer 1250.

As shown in fig. 25B, an antenna layer 1270 is formed on the top surface 1260u of the dielectric layer 1260 by a material forming technique such as that described above, wherein the antenna layer 1270 is positioned opposite to the opening 1250h, such that the signal transmission distance between the antenna layer 1270 and the opening 1250h is minimized and the loss is minimized.

As shown in fig. 25C, at least one scribe line P2 is formed through the substrate 1210 to form at least one semiconductor package 1800 as shown in fig. 21.

In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. A semiconductor package, comprising:

a substrate including at least one through hole penetrating through the substrate and a second grounding layer arranged in the substrate and formed on the inner side wall of the through hole;

a semiconductor chip disposed on the substrate;

a first signal contact point arranged on the substrate and electrically connected with the semiconductor chip;

a third signal transmission column passing through the through hole and extending to the first signal contact, wherein the third signal transmission column is electrically insulated from the second grounding layer;

a signal pad formed on the end surface of the third signal transmission column not contacting with the first signal contact;

a plurality of grounding pads surrounding the signal pads and electrically connected to the second grounding layer; and

a package body for encapsulating the semiconductor chip and having an upper surface.

2. The semiconductor package according to claim 1, further comprising:

a second signal contact; and

a fourth signal transmission post passing through the other through hole and extending to the second signal contact.

3. The semiconductor package according to claim 1, further comprising:

a package body, which wraps the semiconductor chip and has an upper surface and a signal groove, wherein the signal groove extends from the upper surface of the package body to the first signal contact;

a first ground plane formed on the inner side wall of the signal groove and the upper surface of the package body; and

a dielectric layer formed in the signal recess.