CN109712946A - Semiconductor package part - Google Patents
Semiconductor package part Download PDFInfo
- Publication number
- CN109712946A CN109712946A CN201910004316.0A CN201910004316A CN109712946A CN 109712946 A CN109712946 A CN 109712946A CN 201910004316 A CN201910004316 A CN 201910004316A CN 109712946 A CN109712946 A CN 109712946A
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- Prior art keywords
- signal
- substrate
- semiconductor package
- package part
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
A kind of semiconductor package part, including substrate, semiconductor chip, the first signal contact, third signal transmission column, signal bonding pad, several ground connection connection pads and packaging body.Substrate includes that an at least perforation is set in substrate through the substrate and the second ground plane and is connected to the inner sidewall of perforation.Semiconductor chip is set on substrate.First signal contact is set on substrate and is electrically connected semiconductor chip.Third signal transmission column is arranged in perforation and extends to the first signal contact.Signal bonding pad is formed in the end face of third signal transmission column.Several ground connection connection pads are around signal bonding pad and are electrically connected the second ground plane.Packaging body is to coat semiconductor chip and have upper surface.
Description
The application is that applicant submitted on 03 29th, 2013, application No. is " 201310109829.0 ", invention
The divisional application of the divisional application of the application for a patent for invention of entitled " semiconductor package assembly and a manufacturing method thereof ".The divisional application
It is for application No. is the patents of invention of " 201610347969.5 ", entitled " semiconductor package assembly and a manufacturing method thereof "
The divisional application of application.
Technical field
The invention relates to a kind of semiconductor package parts, and in particular to a kind of semiconductor with signal groove
Packaging part.
Background technique
By lifting process speed and result of scaling demand, semiconductor element becomes very complicated.When process speed
Promoted and small size benefit is evident increase when, the characteristic of semiconductor package body also goes wrong.It particularly relates to, higher work
Clock pulse (clock speed) leads to more frequent transition (transition) between signal level (signal level), because
And cause in high frequency or the signal strength weakening under shortwave.Therefore, how to improve the problem of high-frequency signal strength weakens as industry
Make great efforts one of emphasis in boundary.
Summary of the invention
The present invention can reduce loss of signal about a kind of semiconductor package part.
According to the present invention it is proposed that a kind of semiconductor package part.Semiconductor package part include a substrate, semiconductor chip,
One first signal contact, third signal transmission column, a signal bonding pad, several ground connection connection pads and a packaging body.Substrate includes
An at least perforation is set in the substrate through the substrate and one second ground plane and is connected to the inner sidewall of the perforation.Semiconductor core
Piece is set on the substrate.First signal contact is set on the substrate and is electrically connected the semiconductor chip.Third signal transmits column
It is arranged in the perforation and extends to first signal contact.Signal bonding pad is formed in the end face of third signal transmission column.It is several
Ground connection connection pad is around the signal bonding pad and is electrically connected second ground plane.Packaging body is to coat the semiconductor chip and have
One upper surface.
For above content of the invention can be clearer and more comprehensible, special embodiment below, and cooperate attached drawing, it elaborates
It is as follows:
Detailed description of the invention
Figure 1A is painted the cross-sectional view of the semiconductor package part of one embodiment of the invention.
Figure 1B is painted the top view of Figure 1A.
Fig. 2 is painted the top view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 B is painted the top view of Fig. 5 A.
Fig. 6 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 6 B is painted the top view of Fig. 6 A.
Fig. 7 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 7 B is painted the bottom view of Fig. 7 A.
Fig. 8 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 8 B is painted the bottom view of Fig. 8 A.
Fig. 9 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 10 is painted the cross-sectional view of the stacking type semiconductor package part according to another embodiment of the present invention.
Figure 11 is painted the cross-sectional view of the stacking type semiconductor package part according to another embodiment of the present invention.
Figure 12 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 12 B is painted the bottom view of signal transmission component in Figure 12 A.
Figure 13 is painted the bottom view of the signal transmission component according to another embodiment of the present invention.
Figure 14 is painted the bottom view of the signal transmission component according to another embodiment of the present invention.
Figure 15 is painted the bottom view of the signal transmission component according to another embodiment of the present invention.
Figure 16 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 17 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 18 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 18 B is painted the top view of the semiconductor package part according to another embodiment of the present invention.
Figure 19 A is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 19 B is painted the top view of Figure 19 A.
Figure 20 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 21 is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.
Figure 22 A to 22G is painted the process drawing of the semiconductor package part of Fig. 5 A.
Figure 23 A to 23O is painted the process drawing of the semiconductor package part of Figure 12 A.
Figure 24 A to 24I is painted the process drawing of the semiconductor package part of Figure 20.
Figure 25 A to 25C is painted the process drawing of the semiconductor package part of Figure 21.
Main element symbol description:
100、200、300、400、500、600、700、800、900、1000、1000、1200、1300、1400、1500、
1600,1700: semiconductor package part
110,710,810,1210: substrate
110b, 111b, 1210b: lower surface
110s, 140s, 1250s: lateral surface
110u, 111u, 1210u, 1250u, 1260u, 140u, 150u: upper surface
111: substrate
111h, 141h, 150h, 710h, 1210h: perforation
112: the first composite layers
1121: line layer
1122: dielectric layer
1123: conductive hole
1124: ground connection connection pad
113: the second composite layers
1132,5722: ground connection connection pad
120: the first signal contacts
121,1131,5721: signal bonding pad
1211: grounding point
1212: the first conductive layers
1213: the second conductive layers
1250: shielded layer
1250h, 1260h: aperture
1260: dielectric layer
1270: antenna stack
1271: feeding portion
1280,1380: signal transmission component
1281: earthing rod
130: semiconductor chip
131: bonding wire
130u: active surface
140: packaging body
140r: signal groove
140r1: inner sidewall
150: dielectric layer
160,360: the first ground plane
161: inside portion
162: top
163: bottom
364: outside portion
570: the first signals transmit column
571: the first cushion layers
572: the second cushion layers
573: some materials
620: second signal contact
670: second signal transmits column
714: third signal transmits column
715: the second ground planes
814: fourth signal transmits column
P1, P2: Cutting Road
Specific embodiment
Figure 1A is please referred to, the cross-sectional view of the semiconductor package part of one embodiment of the invention is painted.Semiconductor package part 100
Including substrate 110, the first signal contact 120, semiconductor chip 130, packaging body 140, dielectric layer 150 and the first ground plane 160.
Although figure is not painted, right semiconductor package part 100 further includes an at least passive device, such as resistance, inductively or capacitively.
Substrate 110 includes substrate 111, the first composite layer 112 and the second composite layer 113, wherein the first composite layer 112 and the
Two composite layers 113 are respectively formed on the upper surface 111u and lower surface 111b of substrate 111.Substrate 111 is, for example, BT substrate, glass
Glass substrate, dielectric substrate or other suitable substrates.First composite layer 112 includes at least a line layer 1121, at least a dielectric layer
1122 and at least one conductive hole (conductive via) 1123, dielectric layer 1122 electrically isolates adjacent two line layers
1121, and adjacent two line layers 1121 can be electrically connected by corresponding conductive hole 1123.The structure of second composite layer 113 can phase
It is similar to the first composite layer 112, holds this and repeats no more.
First signal contact 120 is formed in the upper surface 110u of substrate 110, can be a part of line layer 1121.
First signal contact 120 can be electrically connected at semiconductor chip 130 by line layer 1121 and conductive hole 1123, pass signal can
It is defeated between the first signal contact 120 and semiconductor chip 130.In addition, semiconductor package part 100 further includes signal bonding pad 121,
It is formed on the first signal contact 120.Signal bonding pad 121 and the first ground plane 160 can be in same techniques with same material
It is primary to be formed.In another example, signal bonding pad 121 can be also omitted.
Semiconductor chip 130 is, for example, the chip of wireless signal transceiving chip or other types, and wherein wireless signal is received and dispatched
Chip is, for example, less radio-frequency (Radio frequency, RF) chip.Semiconductor chip 130 is with the orientation upward active surface 130u
The first composite layer 112 is electrically connected on the upper surface 110u of substrate 110, and through an at least bonding wire 131.Semiconductor core
Piece 130 can be electrically connected at the first signal contact 120 by the line layer 1121 of bonding wire 131 and substrate 110.In another example, half
Conductor chip 130 be, for example, flip (flip chip), with active surface 130u downward orientation be set to substrate 110 upper surface
On 110u, and the first composite layer 112 is electrically connected at by an at least soldered ball.
Packaging body 140 is formed in the upper surface 110u of substrate 110 and coats semiconductor chip 130.Packaging body 140 has upper
Surface 140u and at least signal a groove 140r, signal groove 140r extend to the first letter from the upper surface 140u of packaging body 140
The upper surface 110u of number contact 120 and substrate 110 and expose the first signal contact 120.
Packaging body 140 may include phenolic group resin (Novolac-based resin), epoxy (epoxy-based
Resin), silicone (silicone-based resin) or other coverings appropriate.Packaging body 140 also may include appropriate
Filler, the e.g. silica of powdery.Packaging body 140, e.g. compression forming are formed using several encapsulation technologies
(compression molding), injection moulding (injection molding) or metaideophone form (transfer
molding)。
Due to the removal of package material, make the signal being transmitted in signal groove 140r will not be by packaging body 140
Interference.Dielectric layer 150 is selectively formed in signal groove 140r, uses promotion signal in the transmission in signal groove 140r
Property.For example, dielectric layer 150 is waveguide medium, at least part of signal groove 140r can be filled up.Preferably but non-exclusively,
Dielectric layer 150 can be made of low-loss material.Extraneous signal enters after dielectric layer 150 in carrying out wave conduction in dielectric layer 150,
Then semiconductor chip 130 is transmitted to by the first signal contact 120 again；Alternatively, the signal from semiconductor chip 130 passes
It transports to after dielectric layer 150 in carrying out wave conduction in dielectric layer 150, is then radiated to the external world from dielectric layer 150 again.Further
It says, even if omitting physical or mechanical conducting wire, by the guide properties of dielectric layer 150, signal still can be in dielectric layer
Conduction is between the first signal contact 120 and the upper surface 150u of dielectric layer 150 in 150.
First ground plane 160 includes inside portion 161, is formed on the inner sidewall 140r1 of signal groove 140r.Inside portion
161 can be limited to signal in signal groove 140r, reduce loss of signal or maintain signal strength.Further, since inside portion 161
Can covering outer electromagnetic interference, therefore the signal being transmitted in signal groove 140r is not easily susceptible to negative impact.In addition, this example
In, 161 1 closed ring ground plane of inside portion, the inner sidewall 140r1 for being closely surrounded on signal groove 140r is formed；It is so another
In an example, inside portion 161 can be an open annular ground plane.
First ground plane 160 further includes top 162, is formed in the upper surface 140u of packaging body 140, and extends signal
Between groove 140r and the lateral surface 140s of packaging body 140.In this example, the first ground plane 160 extends to the outside of packaging body 140
Face 140s and be aligned with the lateral surface 140s of packaging body 140, it is e.g. coplanar；So can also it be misaligned.In an example, top 162 is also
The entire upper surface 140u of packaging body 140 can be covered, to overlap completely with about 130 semiconductor chip, and promotes electromagnetic interference
The technical effect of protection.In another example, the first ground plane 160 can also omit top 162.
First ground plane 160 further includes bottom 163, is formed on the line layer 1121 of substrate 110.Bottom 163 passes through
Line layer 1121, conductive hole 1123, the conductive hole 1111 of substrate 111 and the second composite layer 113 are electrically connected at an outside ground connection
It holds (not being painted), is grounded the first ground plane 160.In another example, the first ground plane 160 can omit bottom 163.
Figure 1B is please referred to, the top view of Figure 1A is painted.The cross section of signal groove 140r is, for example, circle, this right non-use
To limit the embodiment of the present invention, in another example, the cross section ellipse or polygon of signal groove 140r, wherein polygonal is such as
It is triangle, rectangle or other polygons.
Referring to figure 2., it is painted the top view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 200 includes substrate 110 (not being painted), the first signal contact 120, semiconductor chip 130 (not being painted), packaging body 140, dielectric
150 (not being painted) of layer and the first ground plane 160.
In this example, it so also can be other geometric shapes that the cross section shape of the signal groove 140r of packaging body 140, which is rectangle,
Polygon, such as pentagon, hexagon.The embodiment of the present invention does not limit the cross section shape of signal groove 140r especially
System.
Referring to figure 3., it is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 300 includes substrate 110, the first signal contact 120, semiconductor chip 130, packaging body 140, dielectric layer 150 and the first ground connection
Layer 360.
First ground plane 360 includes inside portion 161, top 162, bottom 163 and outside portion 364, wherein 364 shape of outside portion
At on the lateral surface 140s of packaging body 140 and the lateral surface 110s of substrate 110, and extend the upper surface of packaging body 140
Between 140u and the lower surface 110b of substrate 110.In this example, outside portion 364 extends to base from the upper surface 140u of packaging body 140
The lower surface 110b of plate 110.Outside portion 364 covers the line layer 1121 of the lateral surface 110s of substrate 110, to pass through line layer
1121 are electrically connected at external ground terminal, are grounded the first ground plane 360.
Referring to figure 4., it is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages
Part 400 includes substrate 110, the first signal contact 120, semiconductor chip 130, packaging body 140, dielectric layer 150 and the first ground connection
Layer 160.
In this example, the first signal contact 120 is formed on the active surface 130u of semiconductor chip 130.The letter of packaging body 140
Number groove 140r extends to the first signal contact being formed on semiconductor chip 130 from the upper surface 140u of packaging body 140
120, to expose the first signal contact 120.Dielectric layer 150 fills up at least part of signal groove 140r, and signal can Yu Jie electricity
Wave conduction is carried out in layer 150.
A referring to figure 5. is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package
Piece installing 500 includes substrate 110, the first signal contact 120, semiconductor chip 130, packaging body 140, the ground connection of dielectric layer 150, first
Layer 160 and the first signal transmit column 570.
In this example, dielectric layer 150 can be epoxy resin (epoxy) or the material for being similar to packaging body 140, can fill up
First signal transmits the recess space between column 570 and the first ground plane 160.The inside portion 161 of first ground plane 160 is around the
One signal transmits column 570, and transmits 570 arranged coaxial of column (Coaxial Via Structure, CVS) with the first signal；So also
It can different axis configuration.In this example, the inside portion 161 of the first ground plane 160 and the first signal transmission column 570 are located at same transverse structure
It in layer, therefore will not occupy directly to space, that is to say, that the first signal transmission column 570 not will increase semiconductor package part 100
Height.
It is, for example, to mold through-hole (Through Molding Via, TMV) that first signal, which transmits column 570, from dielectric layer
150 upper surface 150u extends to signal bonding pad 121, and passes through signal bonding pad 121, the first signal contact 120, conductive hole 1123
And line layer 1121 is electrically connected semiconductor chip 130.In another example, signal bonding pad 121, such first signal transmission can be omitted
Column 570 extends directly to the first signal contact 120 from the upper surface 150u of dielectric layer 150.Column is transmitted by the first signal of design
The internal diameter of the inside portion 161 of 570 outer diameter, the first ground plane 160 and the dielectric coefficient of dielectric layer 150, can get about 50 ohm
Impedance matching and waveguiding electromagnetic mode be more than be intended to operating frequency to avoid mode conversion；In another example, as long as suitably setting
Meter, can make waveguiding electromagnetic mode can be more than 70GHz (be intended to operating frequency), so also be smaller than 70GHz, such as extremely between 40GHz
69GHz。
B referring to figure 5. is painted the top view of Fig. 5 A.In this example, the first signal transmits the cross section shape circle of column 570
Shape also can be so ellipse or polygon, wherein polygon shaped like triangle, rectangle or other polygons.
Fig. 6 A is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 600 includes substrate 110, the first signal contact 120, second signal contact 620, semiconductor chip 130, packaging body 140, is situated between
Electric layer 150, the first ground plane 160, the first signal transmission column 570 and second signal transmit column 670.The semiconductor package part of this example
600 are different from semiconductor package part 100, and binary signal transmission column, the e.g. first letter are formed in a signal groove 140r
Number transmission column 570 and second signal transmit column 670.
First signal contact 120 and second signal contact 620 are all formed on the upper surface 110u of substrate 110, can be
A part of the line layer 1121 of substrate 110.The material and structure of second signal contact 620 can be similar to the first signal contact
120, hold this and repeats no more.
Dielectric layer 150 fills up between the first signal transmission column 570, second signal transmission column 670 and the first ground plane 160
Recess space.
It is, for example, to mold through-hole that second signal, which transmits column 670, extends to signal from the upper surface 150u of dielectric layer 150 and connects
The upper surface 110u of pad 121 and substrate 110, and pass through signal bonding pad 121, second signal contact 620, conductive hole 1123 and route
Layer 1121 is electrically connected at semiconductor chip 130.In another example, signal bonding pad 121 can be omitted, such second signal transmits column
670 extend directly to second signal contact 620 from the upper surface 150u of dielectric layer 150.Semiconductor chip 130 is controllable to be transmitted to
First signal transmits column 570 and the signal phase of second signal transmission column 670 differs 180 degree.In addition, second signal transmits column
670 material and structure can be similar to the first signal transmission column 570, hold this and repeat no more.
Fig. 6 B is please referred to, the top view of Fig. 6 A is painted.In this example, second signal transmits the cross section shape circle of column 670
Shape also can be so ellipse or polygon, wherein polygon shaped like triangle, rectangle or other polygons.In addition, packaging body 140
Signal groove 140r cross section shape ellipse, also can be so round or polygon, wherein polygon shaped like triangle, rectangle
Or other polygons.
Fig. 7 A is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 700 includes substrate 710, the first signal contact 120, semiconductor chip 130 and packaging body 140.
Substrate 710 includes substrate 111, the first composite layer 112 and the second composite layer 113, third signal transmission column 714 and the
Two ground planes 715 and have an at least perforation 710h.Perforation 710h runs through the thickness of entire substrate 710.Third signal transmits column
714 are arranged in perforation 710h and extend to the first signal contact 120, make semiconductor chip 130 can be by the first signal contact 120
And third signal transmission column 714 is electrically connected at an external circuit (not being painted).
Second ground plane 715 is formed in the upper surface 111u and lower surface 111b of the inner sidewall of perforation 710h, substrate 111
On, and an outside ground terminal (not being painted) is electrically connected at by conductive hole 1123, it is grounded the second ground plane 715.Second connects
The technical effect on stratum 715 is similar to the first ground plane 160, holds this and repeats no more.
Fig. 7 B is please referred to, the bottom view of Fig. 7 A is painted.Second composite layer 113 includes an at least signal bonding pad 1131 and number
A ground connection connection pad 1132, signal bonding pad 1131 be formed in third signal transmission column 714 end face, and these ground connection connection pads 1132 that
This is discretely around signal bonding pad 1131.In addition, the cross section shape of perforation 710h is round, it so also can be oval or polygon
Shape, such as triangle, rectangle or other polygons.
Fig. 8 A is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 800 includes substrate 810, the first signal contact 120, semiconductor chip 130 and packaging body 140.
Substrate 810 includes substrate 111, the first composite layer 112 and the second composite layer 113, at least third signal transmission column
714, the second ground plane 715 and an at least fourth signal transmit column 814 and have an at least perforation 710h.Perforation 710h is through whole
The thickness of a substrate 710.Fourth signal transmission column 814 is arranged in perforation 710h and extends to the first signal contact 120, makes partly to lead
Body chip 130 can be electrically connected at an external circuit and (not drawn by the first signal contact 120 and fourth signal transmission column 814
Show).
Second ground plane 715 is formed in the inner sidewall of perforation 710h, and around third signal transmission column 714 and fourth signal
Transmit column 814.
Fig. 8 B is please referred to, the bottom view of Fig. 8 A is painted.Second composite layer 113 (Fig. 8 A) includes several signal bonding pads 1131
And several ground connection connection pads 1132, binary signal connection pad 1131 are respectively formed in end face and the fourth signal of third signal transmission column 714
The end face of column 814 is transmitted, and these ground connection connection pads 1132 surround signal bonding pad 1131 with being separated from each other.In addition, perforation 710h
Cross section shape ellipse also can be so round or polygon, such as triangle, rectangle or other polygons.
Fig. 9 is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor packages
Part 900 includes substrate 710, the first signal contact 120, semiconductor chip 130, packaging body 140, dielectric layer 150, the first ground plane
160 and first signal transmit column 570.
Substrate 710 includes substrate 111, the first composite layer 112 and the second composite layer 113, third signal transmission column 714 and the
Two ground planes 715 and have an at least perforation 710h.Perforation 710h runs through the thickness of entire substrate 710.Third signal transmits column
714 are arranged in perforation 710h and extend to the first signal contact 120, make semiconductor chip 130 can be by the first signal contact 120
And third signal transmission column 714 is electrically connected at an external circuit (not being painted).
First signal transmits column 570 and third signal transmission column 714 is electrically connected, and makes signal that can be transmitted in semiconductor chip
130, between the first signal transmission column 570 and third signal transmission column 714.In this example, the first signal transmits column 570 and third is believed
Number transmission column 714 docks, i.e. the first signal transmission column 570 and third signal transmit column 714 and linearly configure, and passes signal
Defeated path is most short.In another example, the first signal transmission column 570 can be controlled with third signal transmission column 714 and is in staggered configuration, and be passed through
First composite layer 112 is electrically connected.
Figure 10 is please referred to, the cross-sectional view of the stacking type semiconductor package part according to another embodiment of the present invention is painted.Heap
Stacked semiconductor package part 1000 includes two semiconductor package parts 100, with the docking of signal groove 140r relative mode, makes 2 half
Signal between conductor packaging part 100 can be transmitted by opposite binary signal groove 140r.Although figure is not painted, right two semiconductor
It include a solder between packaging part 100, with two semiconductor package part 100 of soldering.
Figure 11 is please referred to, the cross-sectional view of the stacking type semiconductor package part according to another embodiment of the present invention is painted.Heap
Stacked semiconductor package part 1100 includes semiconductor package part 500 and 900, and wherein semiconductor package part 500 is with its first signal
The third signal of transmission column 570 and semiconductor package part 900 transmits column 714 and docks, make two semiconductor package parts 500 and 900 it
Between signal can pass through the first signal and transmit column 570 and third signal and transmit column 714 and transmit.In this example, semiconductor package part 900
The first signal transmission column 570, third signal transmission column 714 and semiconductor package part 500 the first signal transmit column 570 along straight
The configuration of line direction, keeps signal transmission path most short.
Although the stacking type semiconductor package part of above-described embodiment with semiconductor package part 100,500 and 900 stack for
Example explanation, so in another example, at least the two of semiconductor package part 100 to 900 can also stack each other；Alternatively, several identical
Semiconductor package part can also stack each other.
Figure 12 A is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 1200 includes substrate 1210, the first signal contact 120, semiconductor chip 130, packaging body 140, shielded layer 1250, dielectric
Layer 1260, antenna stack 1270, feeding portion (feed point) 1271 and at least one signal transmission component 1280.
Substrate 1210 is, for example, multilayered structure comprising an at least line layer 1121 and at least a conductive hole 1123.It is another
In example, substrate 1210 can be single layer structure.Substrate 1210 further includes an at least grounding point 1211, is formed in substrate 1210
Upper surface 1210u, and an outside ground terminal (not being painted) is electrically connected by line layer 1121 and conductive hole 1123；Another example
In, grounding point 1211 may extend away between the upper surface 1210u and lower surface 1210b of substrate 1210.
First signal contact 120 is formed on substrate 1210, and passes through the line layer 1121 and conductive hole of substrate 1210
1123 are electrically connected at semiconductor chip 130.Semiconductor chip 130 is set on substrate 1210, and is electrically connected by bonding wire 131
In substrate 1210.
Shielded layer 1250 is formed in the lateral surface 140s and upper surface 140u of packaging body 140, and is electrically connected at substrate
1210 grounding point 1211 is grounded shielded layer 1250.
The materials of aluminum of shielded layer 1250, copper, chromium, tin, gold, silver, nickel, stainless steel or above-mentioned material combination made by,
It can be using e.g. chemical vapor deposition (Chemical Vapor Deposition, CVD), electroless plating (electroless
Plating), it is electroplated, prints (printing), spraying (spraying), sputter or vacuum deposition (vacuum deposition)
Etc. technologies be made.
Dielectric layer 1260 is, for example, to be formed with low-loss low dielectric constant materials, e.g. Teflon (Teflon), poly-
Tetrafluoroethene (PTEE) and polystyrene (Polystyrene).Dielectric layer 1260 covers the upper surface 1250u of shielded layer 1250,
And there is an at least aperture 1260h.Antenna stack 1270 is formed on the upper surface 1260u of dielectric layer 1260.Feeding portion 1271 is logical
Aperture 1260h connection antenna stack 1270 and the first signal transmission column 570 are crossed, antenna stack 1270 can be made to pass through feeding portion 1271, the
One signal transmission column 570, the first signal contact 120, line layer 1121, conductive hole 1123 and bonding wire 131 are electrically connected at and partly lead
Body chip 130.
Signal transmission component 1280 is electrically connected at the first signal contact 120, and passes through the first signal contact 120, conduction
Hole 1123, line layer 1121, bonding wire 131 are electrically connected at semiconductor chip 130.
Signal transmission component 1280 includes that at least one first signal transmits column 570, at least an earthing rod 1281, dielectric layer
150, the first cushion layer 571 and the second cushion layer 572, signal transmission component 1280 are, for example, an element pasted on surface or intermediary layer
(Interposer).First signal transmits column 570 and earthing rod 1281 runs through entire dielectric layer 150, and the first signal transmits column 570
It is docked with the first signal contact 120, to be electrically connected at semiconductor chip 130 by the first signal contact 120.
Figure 12 B is please referred to, the bottom view of signal transmission component in Figure 12 A is painted.Several earthing rods 1281 are separated from each other
Ground transmits column 570 around the first signal, to generate electromagnetic interference shielding effect to the first signal transmission column 570.It is several in this example
Earthing rod 1281 is arranged in circular rings and transmits column 570 around the first signal, and so this is non-to limit the embodiment of the present invention.In addition, the
Two cushion layers 572 include signal bonding pad 5721 and ground connection connection pad 5722, and wherein signal bonding pad 5721 is formed in the transmission of the first signal
The end face of column 570, and it is grounded the end face that connection pad 5722 is formed in each earthing rod 1281 in closed ring, to be electrically connected simultaneously
Whole earthing rods 1281.In another example, ground connection connection pad 5722 may include the sub- cushion layer of several separation, be each formed in pair
The end face for the earthing rod 1281 answered.
Figure 13 is please referred to, the bottom view of the signal transmission component according to another embodiment of the present invention is painted.In this example, letter
Number transfer element 1280 includes that several earthing rods 1281 and the first signal transmit column 570, wherein several earthing rods 1281 are arranged in
Straight-flanked ring transmits column 570 around the first signal.
Figure 14 is please referred to, the bottom view of the signal transmission component according to another embodiment of the present invention is painted.In this example, letter
Number transfer element 1280 includes that single earthing rod 1281 and the first signal transmit column 570, wherein 1,281 1 closed circle of earthing rod
Cyclic annular column closely transmits column 570 around the first signal.
Figure 15 is please referred to, the bottom view of the signal transmission component according to another embodiment of the present invention is painted.In this example, letter
Number transfer element 1280 includes that single earthing rod 1281 and the first signal transmit column 570, wherein 1,281 1 enclosing square of earthing rod
Cyclic annular column closely transmits column 570 around the first signal.
Figure 16 is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 1300 includes substrate 1210, the first signal contact 120, semiconductor chip 130, packaging body 140, shielded layer 1250, dielectric
Layer 1260, antenna stack 1270 and signal transmission component 1380.
Compared to semiconductor package part 1200, the signal transmission component 1380 of the semiconductor package part 1300 of this example omits the
One signal transmits column 570, and semiconductor package part 1200 omits feeding portion 1271.The dielectric layer 150 of signal transmission component 1280
It can be formed by waveguide material, facilitate promotion signal transporting.Shielded layer 1250 has aperture 1250h, is located at signal and transmits
Right above the dielectric layer 150 of element 1380.The signal of semiconductor chip 130 can be transmitted to dielectric by the first signal contact 120
In layer 150, and conduct in carrying out wave in dielectric layer 150 to aperture 1250h, then via electromagnetic induction principle, shielded layer 1250
And antenna stack 1270 induces signal, and by antenna stack 1270 by signal radiation to the external world.It further says, even if omitting physics
Property or mechanical conducting wire, between antenna stack 1270 and the first signal contact 120 signal transmitting can still pass through electromagnetism sense
Mode is answered to reach.In addition, aperture 1250h vertically the first signal contact of face 120, keep signal transmission path shorter or most
It is short.
Figure 17 is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 1400 includes substrate 1210, the first signal contact 120, semiconductor chip 130, packaging body 140, shielded layer 1250 and at least
One signal transmission component 1380.
Compared to semiconductor package part 1300, the semiconductor package part 1400 of this example omits dielectric layer 1260 and antenna stack
1270.The signal of semiconductor chip 130 can be transmitted in dielectric layer 150 by the first signal contact 120, and in dielectric layer 150
Interior progress wave is radiated to the external world after conducting to aperture 1250h.
Figure 18 A is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 1500 includes substrate 1210, at least 2 first signal contacts 120, semiconductor chip 130, packaging body 140, shielded layer 1250
And at least binary signal transfer element 1380.
Compared to semiconductor package part 1400, the semiconductor package part 1500 of this example includes multiple signal transmission components
1380, it is respectively set on corresponding first signal contact 120.
Figure 18 B is please referred to, the top view of the semiconductor package part according to another embodiment of the present invention is painted.Multiple signals
Transfer element 1380 lines up two column, is located at opposite two sides of semiconductor chip 130.Via increase signal transmission component 1380
Quantity, the signal strength of semiconductor package part 1500 can be promoted.
Figure 19 A is please referred to, the cross-sectional view of the semiconductor package part according to another embodiment of the present invention is painted.Semiconductor package
Piece installing 1600 includes substrate 1210, at least one first signal contact 120, semiconductor chip 130, packaging body 140, shielded layer 1250
An and at least signal transmission component 1380.
Substrate 1210 includes line layer 1121 ', semiconductor chip 130 is electrically connected at, with transferring semiconductor chip 130
Signal.For input signal, outer signals are transmitted to signal transmission component 1380 via the aperture 1250h of shielded layer 1250
Dielectric layer 150 in, and toward substrate 1210 line layer 1121 ' direction in several earthing rods of signal transmission component 1380
Wave conduction is carried out to transverse reciprocating between 1281, via electromagnetic induction, after 1121 ' inductive signal of line layer, then signal is transmitted
To semiconductor chip 130.For output signal, the signal of semiconductor chip 130 is transmitted to line layer 1121 ' and enters dielectric afterwards
In layer 150, and lateral wave conduction is carried out between these earthing rods 1281 toward the direction aperture 1250h, then pass through shielded layer again
1250 aperture 1250h is radiate.
Figure 19 B is please referred to, the top view of Figure 19 A is painted.Several earthing rods 1281 of signal transmission component 1380 arrange
At ㄇ font, the line layer 1121 ' of substrate 1210 is extended between opposite two rows of ㄇ font, to receive from dielectric layer
The signal of 150 (Figure 19 A) or the signal of transferring semiconductor chip 130 are to dielectric layer 150.In addition, substrate 1210 includes at least one
It is grounded connection pad 1124, single ground connection connection pad 1124 can be electrically connected all earthing rods 1281 of individual signals transfer element 1380,
As long as so can once be electrically connected all earthing rods 1281 of individual signals transfer element 1380, the embodiment of the present invention is simultaneously unlimited
Surely it is grounded the shape of connection pad 1124.In addition, ground connection connection pad 1124 forms a ㄇ font, it is open towards line layer 1121 ', and line
The opening of road floor 1121 ' and ㄇ font overlaps up and down.
Referring to figure 2. 0, it is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package
Piece installing 1700 includes substrate 1210, the first signal contact 120, semiconductor chip 130, packaging body 140, shielded layer 1250, dielectric
Layer 1260, antenna stack 1270 and an at least earthing rod 1281.
Compared to semiconductor package part 1300 (Figure 16), the earthing rod 1281 of this example is non-formation in signal transmission component 1280
In, but be integrated in the technique of semiconductor package part 1400, specifically, earthing rod 1281 is directly from the upper of packaging body 140
Surface 140u extends to the ground connection connection pad 1124 of substrate 1210.Ground connection connection pad 1124 is electrically connected at a ground terminal, makes shielded layer
1250 are grounded by earthing rod 1281 and ground connection connection pad 1124.In addition, the line layer 1121 ' of substrate 1210 can pass through conductive hole
1123 are electrically connected at semiconductor chip 130.
There is shielded layer 1250 an at least aperture 1250h connect antenna stack 1270 between several earthing rods 1281
The signal of receipts can enter from aperture 1250h between these first signals transmission column 570, or the letter exported from semiconductor chip 130
It is radiate after conducting number between these earthing rods 1281 from aperture 1250h.In this example, packaging body 140 is, for example, waveguide material
Material, fills up the space between these earthing rods 1281, makes signal that can carry out wave conduction between these earthing rods 1281.
The upper surface 1250u and lateral surface 1250s of the covering shielded layer 1250 of dielectric layer 1260, that is to say, that dielectric layer
The 1260 entire shielded layers 1250 of cladding, can complete preservation shielded layer 1250.Antenna stack 1270 is formed in the upper table of dielectric layer 1260
On the 1260u of face, and the aperture 1250h for corresponding to shielded layer 1250 is arranged, and makes signal between antenna stack 1270 and aperture 1250h
Transmission path it is shorter or most short.
Referring to figure 2. 1, it is painted the cross-sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package
Piece installing 1800 includes substrate 1210, the first signal contact 120, semiconductor chip 130, packaging body 140, shielded layer 1250, dielectric
Layer 1260, antenna stack 1270 and several first signals transmit column 570.
Compared to semiconductor package part 1700 (Figure 20), the dielectric layer 1260 of this example covers the upper surface of shielded layer 1250
1250u, but the lateral surface of shielded layer 1250 is not covered.
2A to 22G referring to figure 2. is painted the process drawing of the semiconductor package part of Fig. 5 A.
As shown in fig. 22, to be, for example, that surface is pasted technology (Surface Mounted Technology, SMT), setting
At least semiconductor chip 130 is electrically connected semiconductor chip 130 and substrate on substrate 110, and with an at least bonding wire 131
110。
Substrate 110 includes substrate 111, the first composite layer 112 and the second composite layer 113, wherein the first composite layer 112 and the
Two composite layers 113 are respectively formed on the upper surface 111u and lower surface 111b of substrate 111.Substrate 111 is, for example, BT substrate, glass
Glass substrate, dielectric substrate or other suitable substrates.First composite layer 112 includes at least a line layer 1121, at least a dielectric layer
1122 and at least one conductive hole (conductive via) 1123, dielectric layer 1122 adjacent two line layers 1121 are isolated, and
Adjacent two line layers 1121 can be electrically connected by corresponding conductive hole 1123.The structure of second composite layer 113 can be similar to
One composite layer 112, holds this and repeats no more.In addition, the first signal contact 120 is formed on the upper surface 110u of substrate 110, it can
To be a part of line layer 1121.
As shown in fig. 22, it to be, for example, compression forming, injection moulding or metaideophone molding, forms the cladding of packaging body 140 and partly leads
Body chip 130 and bonding wire 131.
As shown in Figure 22 B, to be, for example, laser drill, injection (jetting) drilling or machine drilling, at least one letter is formed
Number groove 140r is in packaging body 140, and wherein signal groove 140r extends to the first signal from the upper surface 140u of packaging body 140 and connects
Point 120, to expose the first signal contact 120.
As shown in fig. 22 c, to be, for example, material formation technology, the first ground plane 160 and signal bonding pad 121 are formed.First
Ground plane 160 includes inside portion 161, top 162 and bottom 163, and wherein inside portion 161 is formed in the inside of signal groove 140r
On wall 140r1, top 162 is formed on the upper surface 140u of packaging body 140, and bottom 163 is formed in the line layer of substrate 110
On 1121.Signal bonding pad 121 is formed on the first signal contact 120.
It is, for example, chemical vapor deposition, electroless plating method (electroless plating), electrolysis that above-mentioned material, which forms technology,
(electrolytic plating), printing, spin coating, spraying, sputter (sputtering) or vacuum deposition method (vacuum is electroplated
deposition)。
As shown in figure 22d, it in a manner of filler, forms dielectric layer 150 and fills up signal groove 140r, in this example, dielectric layer 150
It can be epoxy resin.So far, the structure of the semiconductor package part 100 of Figure 1A is formed.The semiconductor of Fig. 5 A is continued to explain below
The manufacturing method of packaging part 500.
As shown in figure 22e, it to be, for example, laser, injection or cutter, forms an at least perforation 150h and runs through corresponding dielectric
Layer 150, wherein perforation 150h extends to signal bonding pad 121 from the upper surface 150u of dielectric layer 150.In another example, if omitting letter
Number connection pad 121, then perforation 150h extends directly to the first signal contact 120 from the upper surface 150u of dielectric layer 150.
As shown in figure 22f, to be, for example, above-mentioned material formation technology, the first signal transmission column 570 is formed in perforation 150h
It is interior, wherein some materials 573 of the first signal transmission column 570 protrude from the upper surface 150u of dielectric layer 150.
Then, to be, for example, patterning techniques, the top 162 of the first ground plane 160 is patterned, to obtain scheduled figure
Case.In addition, in patterning step, can modified part material 573 simultaneously edge, to obtain suitable or expected size.This
The patterning techniques at place are, for example, lithography process (photolithography), chemical etching (chemical etching), swash
Drill finish hole (laser drilling) or machine drilling (mechanical drilling).
As shown in figure 22g, with such as cutter or laser, an at least Cutting Road P1 is formed by the first ground plane 160, encapsulation
Body 140 and substrate 110, to form the structure at least just like semiconductor package part 500 shown in Fig. 5 A.
The manufacturing method of semiconductor package part 200,300,400 and 600 is similar to the system of the semiconductor package part 500 of Fig. 5 A
Method is made, holds this and repeats no more.
In the manufacturing process of semiconductor package part 700, the substrate 110 of 22A figure can be replaced with substrate 710, and is omitted
Signal groove 140r (Figure 22 B), the first ground plane 160 (Figure 22 C), dielectric layer 150 (Figure 22 D), perforation 150h (Figure 22 E) and
One signal transmits the forming step of column 570 (Figure 22 F).
The manufacturing process of semiconductor package part 800 is similar to semiconductor package part 700, holds this and repeats no more.
In the manufacturing process of semiconductor package part 900, the substrate 110 of Figure 22 A can be replaced with substrate 710, it so can shape
At semiconductor package part 900.
3A to 23O referring to figure 2. is painted the process drawing of the semiconductor package part of Figure 12 A.
As shown in fig. 23 a, a substrate 1200 is provided, substrate 1200 is led including substrate 111, the first conductive layer 1212 and second
Electric layer 1213, the first conductive layer 1212 and the second conductive layer 1213 are covered each by the entire upper surface 111u of substrate 111 and entire
Lower surface 111b.In this example, substrate 111 can be insulator.
As shown in fig. 23b, it to be, for example, laser drill, jet hole or machine drilling, forms an at least perforation 1210h and passes through
Wear entire substrate 1200.
As shown in fig. 23 c, to be, for example, plating mode, earthing rod 1281 is formed on the inner sidewall of perforation 1210h, wherein
Earthing rod 1281 is connected to the first conductive layer 1212 and the second conductive layer 1213.
As shown in fig. 23d, to be, for example, to form dielectric layer 150 and fill up perforation 1210h in a manner of filler.
As shown in Figure 23 E, to be, for example, laser drill, jet hole or machine drilling, forms an at least perforation 150h and pass through
Wear entire dielectric layer 150.
As shown in figure 23f, with above-mentioned material formed technology, formed the first signal transmission column 570, the first cushion layer 571 and
Second cushion layer 572, wherein the first signal transmission column 570 fills up perforation 150h, and the first cushion layer 571 and the second cushion layer
572 are covered each by the first conductive layer 1212 and the second conductive layer 1213 and are electrically connected at the first signal transmission column 570.
As shown in Figure 23 G, with above-mentioned patterning techniques, the first conductive layer 1212 and the second conductive layer 1213 are patterned, with
Electrically isolate the first signal transmission column 570 and earthing rod 1281.After patterning, the first conductive layer 1212 and the second conductive layer 1213
It is respectively formed the first cushion layer 571 and the second cushion layer 572, respectively includes an at least connection pad.
As shown in Figure 23 H, to be, for example, cutter or laser, it is conductive by substrate 111, first to form an at least Cutting Road P1
Layer 1212 and the second conductive layer 1213, to be formed at least just like signal transmission component 1280 shown in Figure 12 A.
As shown in Figure 23 I, a substrate 1210 is provided.Substrate 1210 is, for example, multilayered structure comprising an at least line layer
1121 and at least one conductive hole 1123.In another example, substrate 1210 can be single layer structure.In addition, substrate 1210 further include to
A few grounding point 1211, protrudes from the upper surface 1210u of substrate 1210 and is formed；In another example, grounding point 1211 is extensible
Between the upper surface 1210u and lower surface 1210b of substrate 1210.
As shown in Figure 23 I, to be, for example, that technology is pasted on surface, setting at least semiconductor chip 130 on substrate 110,
And semiconductor chip 130 and substrate 1210 are electrically connected with an at least bonding wire 131.
As shown in Figure 23 I, to be, for example, that technology is pasted on surface, the signal transmission component 1280 of Figure 23 H is set in substrate
On 1210, wherein the second cushion layer 572 of signal transmission component 1280 and the first signal transmission column 570 are electrically connected in line
Road floor 1121 (line layer 1121 being isolated with the first signal contact 120) and the first signal contact 120.Second cushion layer 572 is logical
Cross the ground connection of line layer 1121.
As shown in Figure 23 J, to be, for example, compression forming, injection moulding or metaideophone molding, forms the cladding of packaging body 140 and partly lead
Body chip 130, bonding wire 131 and signal transmission component 1280.
As shown in Figure 23 K, with such as lapping mode, 140 top material of packaging body is removed, and forms the upper of packaging body 140
Surface 140u, wherein the first cushion layer 571 of signal transmission component 1280 is exposed from the upper surface 140u of packaging body 140.
As shown in Figure 23 L, to be, for example, cutter or laser, forms an at least Cutting Road P1 and pass through packaging body 140, Zhi Daolu
The grounding point 1211 of substrate 1210 out.Since Cutting Road P1 does not completely cut through substrate 1210, such cutting mode is known as " it partly wears and cuts
(half-cut)".In another example, Cutting Road P1 can cut through entire packaging body 140 and entire substrate 1210, such cutting mode claim
For " wear entirely and cut (full-cut) ".
As shown in figure 23m, technology is formed with above-mentioned material, forms the lateral surface that shielded layer 1250 covers packaging body 140
140s and upper surface 140u.
As shown in Figure 23 N, to be, for example, coating technique, the upper surface that dielectric layer 1260 covers shielded layer 1250 is formed
1250u。
As shown in Figure 23 N, technology is formed with above-mentioned material, forms antenna stack 1270 in the upper surface of dielectric layer 1260
1260u, and feeding portion 1271 is formed in the aperture 1260h of dielectric layer 1260, antenna stack 1270 can be made to pass through 1271 electricity of feeding portion
Property be connected to the first signal transmission column 570.
It as shown in Figure 23 O, forms an at least Cutting Road P2 and passes through substrate 1210, to be formed at least just like shown in Figure 12 A
Semiconductor package part 1200.
In the manufacturing process of semiconductor package part 1300 (Figure 16), perforation 150h (Figure 23 E), the transmission of the first signal are omitted
The forming step of column 570 (Figure 23 F), aperture 1260h and feeding portion 1271, remaining manufacturing step are similar to manufacture semiconductor packages
The correspondence step of part 1200, holds this and repeats no more.
In the manufacturing process of semiconductor package part 1400 (Figure 17), compared to the manufacture of semiconductor package part 1300
Journey can omit the forming step of dielectric layer 1260 and antenna stack 1270, remaining manufacturing step is similar to manufacture semiconductor package part
1300 correspondence step, holds this and repeats no more.
The manufacturing process of semiconductor package part 1500 and 1600 is similar to the manufacturing process of semiconductor package part 1400, holds this
It repeats no more.
4A to 24I referring to figure 2. is painted the process drawing of the semiconductor package part of Figure 20.
As shown in fig. 24 a, a substrate 1210 is provided, wherein substrate 1210 is, for example, multilayered structure comprising an at least line
Road floor 1121, at least a conductive hole 1123, at least a grounding point 1211 and at least one ground connection connection pad 1124.
As shown in fig. 24 a, to be, for example, that technology is pasted on surface, at least semiconductor chip is set on substrate 1210.
As shown in fig. 24b, it to be, for example, compression forming, injection moulding or metaideophone molding, forms the cladding of packaging body 140 and partly leads
Body chip 130 and ground connection connection pad 1124.
As shown in Figure 24 C, to be, for example, above-mentioned patterning techniques, an at least perforation 141h is formed from the upper of packaging body 140
Surface 140u extends to ground connection connection pad 1124, is grounded connection pad 1124 to expose.
As shown in Figure 24 D, to be, for example, above-mentioned material formation technology, forms an at least earthing rod 1281 and fill up corresponding pass through
Hole 141h is grounded earthing rod 1281 by ground connection connection pad 1124.
As shown in Figure 24 E, to be, for example, cutter or laser, an at least Cutting Road P1 is formed from the upper surface of packaging body 140
140u extends to grounding point 1211, to expose grounding point 1211.Since Cutting Road P1 does not cut off total, so kind cutting
Mode is known as " partly wear and cut ".In right another example, it also can be used and wear blanking method entirely, is i.e. Cutting Road P1 cuts off entire substrate 1210.
As shown in Figure 24 F, to be, for example, above-mentioned material formation technology, shielded layer 1250 is formed in the outside of packaging body 140
On face 140s and upper surface 140u, wherein shielded layer 1250 is electrically connected at grounding point 1211.Shielded layer 1250 has at least one
Aperture 1250h, between several earthing rods 1281.
As shown in Figure 24 G, to be, for example, coating technique, the upper surface that dielectric layer 1260 covers shielded layer 1250 is formed
1250u and lateral surface 1250s.
As shown in Figure 24 H, to be, for example, above-mentioned material formation technology, antenna stack 1270 is formed in the upper table of dielectric layer 1260
On the 1260u of face, wherein the position of 1270 face aperture 1250h of antenna stack, makes the signal between antenna stack 1270 and aperture 1250h
Transmission range is most short, and loss is minimum.
As shown in Figure 24 I, to be, for example, cutter or laser, forms an at least Cutting Road P2 and pass through dielectric layer 1260 and substrate
1210, to be formed at least just like semiconductor package part 1700 shown in Figure 20.
5A to 25C referring to figure 2. is painted the process drawing of the semiconductor package part of Figure 21.
As shown in fig. 25 a, to be, for example, coating technique, the upper surface that dielectric layer 1260 covers shielded layer 1250 is formed
1250u, but expose the lateral surface 1250s of shielded layer 1250.
As shown in Figure 25 B, to be, for example, above-mentioned material formation technology, antenna stack 1270 is formed in the upper table of dielectric layer 1260
On the 1260u of face, wherein the position of 1270 face aperture 1250h of antenna stack, makes the signal between antenna stack 1270 and aperture 1250h
Transmission range is most short, and loss is minimum.
As shown in fig. 25 c, it forms an at least Cutting Road P2 and passes through substrate 1210, to be formed at least just like shown in Figure 21 half
Conductor packaging part 1800.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various change and profit can be made
Decorations.Therefore, the scope of protection of the present invention is defined by those of the claims.
Claims (3)
1. a kind of semiconductor package part characterized by comprising
One substrate is set in the substrate through the substrate and one second ground plane including an at least perforation and is connected to the perforation
Inner sidewall；
Semiconductor chip is set on the substrate；
One first signal contact is set on the substrate, and is electrically connected the semiconductor chip；
One third signal transmits column, is arranged in the perforation and extends to first signal contact；
One signal bonding pad is formed in the end face of third signal transmission column；
Several ground connection connection pads around the signal bonding pad, and are electrically connected second ground plane；And
One packaging body, to coat the semiconductor chip and there is a upper surface.
2. semiconductor package part as described in claim 1, which is characterized in that further include:
One second signal contact；And
One fourth signal transmits column, is arranged in another perforation and extends to the second signal contact.
3. semiconductor package part as described in claim 1, which is characterized in that the semiconductor package part further includes:
One packaging body coats semiconductor chip and has a upper surface and a signal groove, and the signal groove is from the packaging body
The upper surface extends to first signal contact；
One first ground plane is formed in the upper surface on the inner sidewall of the signal groove with the packaging body；And
One dielectric layer is formed in the signal groove.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910004316.0A CN109712946B (en) | 2013-03-29 | 2013-03-29 | Semiconductor package |
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| CN201910004316.0A CN109712946B (en) | 2013-03-29 | 2013-03-29 | Semiconductor package |
| CN201310109829.0A CN103151327B (en) | 2013-03-29 | 2013-03-29 | Semiconductor package assembly and a manufacturing method thereof |
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| CN201310109829.0A Division CN103151327B (en) | 2013-03-29 | 2013-03-29 | Semiconductor package assembly and a manufacturing method thereof |
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| CN201610347969.5A Active CN106024730B (en) | 2013-03-29 | 2013-03-29 | Semiconductor package assembly and a manufacturing method thereof |
| CN201910004316.0A Active CN109712946B (en) | 2013-03-29 | 2013-03-29 | Semiconductor package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4160668A1 (en) * | 2021-09-30 | 2023-04-05 | NXP USA, Inc. | Leadless power amplifier package including topside termination arrangements |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103400826B (en) * | 2013-06-21 | 2016-08-17 | 三星半导体(中国)研究开发有限公司 | Semiconductor packages and manufacture method thereof |
| CN103400816B (en) * | 2013-06-26 | 2016-08-10 | 三星半导体(中国)研究开发有限公司 | Packaging part and manufacture method thereof |
| FR3026529B1 (en) * | 2014-09-30 | 2017-12-29 | Linxens Holding | METHOD FOR MANUFACTURING CHIP CARD AND CHIP CARD OBTAINED THEREBY |
| CN106503338B (en) * | 2016-10-24 | 2020-06-16 | 上海华力微电子有限公司 | Anti-electromagnetic interference crystal oscillator resonant circuit |
| US10910329B2 (en) * | 2017-05-23 | 2021-02-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
| US11552026B2 (en) | 2019-01-31 | 2023-01-10 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages and methods of manufacturing the same |
| US11532875B2 (en) * | 2020-10-22 | 2022-12-20 | Mediatek Inc. | Antenna module |
| CN115632041B (en) * | 2022-09-16 | 2024-02-13 | 北京七星华创微电子有限责任公司 | TMV structure, preparation method thereof and packaging structure |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN109712946B (en) | 2021-01-19 |
| CN106024730B (en) | 2019-07-12 |
| CN106024730A (en) | 2016-10-12 |
| CN103151327A (en) | 2013-06-12 |
| CN103151327B (en) | 2016-06-22 |
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