CN109712653B

CN109712653B - Chip initialization method

Info

Publication number: CN109712653B
Application number: CN201811552754.2A
Authority: CN
Inventors: 仇斌
Original assignee: Shanghai Anlu Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co ltd
Priority date: 2018-02-27
Filing date: 2018-12-19
Publication date: 2021-08-31
Anticipated expiration: 2038-12-19
Also published as: CN109712653A

Abstract

The application relates to the field of integrated circuit digital design and discloses a chip initialization method. By means of the built-in flash memory unit, the attribute blocks on the flash memory unit are read before chip initialization to effectively reduce configuration and status indication IO of the chip, and various control register groups are configured at the stage to realize various flexible settings of the chip before chip code stream downloading. The method has strong universality, can quickly and effectively reduce the complexity and cost caused by redesigning to achieve the purpose in the aspects of different process manufacturers and different process procedures, and provides the design safety of the chip.

Description

Chip initialization method

Technical Field

The present invention relates to the field of integrated circuit digital design, and more particularly, to a chip initialization method.

Background

Some chips (such as FPGA) need to occupy a large number of IOs for supporting selection of various download modes and indicating the working state of the chip (for example, a circle 3 chip of altera configures the download mode with 4 IO msels [3:0], and indicates the working state of the chip with 2 IO nCONFIG and nstitus), and when the chip enters the working state of the user, these IOs are often wasted and cannot be used as the user IOs, especially in the case of a small number of chip package IOs, these IOs will reduce the number of IOs available for the user logic, and limit the use of the user.

Taking FPGA as an example, in practical use, the configuration code stream is generally downloaded through an external memory chip (for example, SPI flash). The connection between the SPI flash chip and the FPGA chip generally uses 4 IOs which are generally not logically used by a user in a user working state, so that the number of the IOs which can be used by the user of the small-packaged FPGA chip is very limited; the configuration register of the FPGA chip is generally positioned in the code stream, and the chip can obtain the information only in the process of downloading the code stream; however, the FPGA chip needs a period of time from power-on to start downloading the code stream, and in the period of time, certain characteristics of the chip are not programmable and controllable (such as IO state); in this case, the existing designs often do not provide good support.

Disclosure of Invention

The application aims to provide a chip initialization method, which can increase the number of user-available IO by reducing the number of configuration IO, and can improve the flexibility of the user-available IO and the configurable function of a chip by providing certain attributes of the chip before the chip is started.

In order to solve the above problems, the present application discloses a chip initialization method, where the chip includes a programmable logic unit and a flash memory unit including an attribute block, and data in the attribute block includes configuration information for selecting a download mode; the method comprises the following steps:

synchronizing the attribute blocks;

if the synchronization is successful, loading the data of the attribute block into a register of the programmable logic unit, finishing the selection of a downloading mode according to the data in the register, and downloading the code stream according to the selected downloading mode.

In a preferred embodiment, the FLASH memory unit is a volatile memory or a non-volatile memory, and the FLASH memory unit includes an SPI FLASH.

In a preferred embodiment, the data in the attribute block further includes: state information of various control register groups is used for indicating the characteristics of the chip before the code stream downloading starts; the attribute block is a contiguous block of memory stored at a particular address on the flash memory unit.

In a preferred embodiment, before the code stream downloading, the method further includes: and initializing the chip according to the data in the register.

In a preferred embodiment, the flash memory unit is a volatile memory, and the flash memory unit includes an SPI flash.

In a preferred embodiment, the method further comprises:

if the data synchronization fails, the chip is initialized and downloaded by default of a pre-configured register initial value and a default download mode through the programmable logic unit.

In a preferred embodiment, the chip further includes a power-on detection module, configured to detect a power supply condition of the chip before attempting the synchronous detection of the attribute block and performing the data synchronization.

In a preferred embodiment, the chip comprises an SIP package and an SOC package, and the packaging process is a packaging form for packaging the bare chip of the flash memory unit and the bare chip of the programmable logic unit together.

In a preferred embodiment, the method is suitable for the design of programmable logic circuits and application-specific integrated circuits; the programmable logic circuit comprises an FPGA and a CPLD.

The present application also discloses a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the steps in the method as described hereinbefore.

In the embodiment of the application, at least the following advantages are included:

(1) before the chip completes initialization (at the moment, the code stream does not start to be downloaded), the downloading mode is determined by reading the data of the attribute block of the internal flash unit, so that the number of unavailable IO (input/output) of a user in the package is reduced, and the number of available IO of the user is greatly improved;

(2) the attribute block (attribute block) not only includes downloading mode configuration information, but also includes various control register groups (pre _ cfg _ registers) for indicating the characteristics of the chip before the chip starts downloading the code stream, such as whether the state indicates IO multiplexing, IO pull-up/pull-down/tri-state, and the like, so as to improve the flexibility of user IO and configurable functions;

(3) the flash die and the FPGA die can be sealed together through simple SIP packaging, so that the complexity caused by redesigning the flash (flash) and the programmable logic circuit on the same die, which is possibly generated by realizing the functions of (1) and (2), is reduced;

(4) the method is not only suitable for SIP packaging of the programmable logic circuit and the SPI flash, but also suitable for special integrated circuit design with similar requirements; meanwhile, the method is suitable for different process manufacturers and different process procedures, and is simple in design and convenient to use.

The present specification describes a number of technical features distributed throughout the various technical aspects, and if all possible combinations of technical features (i.e. technical aspects) of the present specification are listed, the description is made excessively long. In order to avoid this problem, the respective technical features disclosed in the above summary of the invention of the present application, the respective technical features disclosed in the following embodiments and examples, and the respective technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which are considered to have been described in the present specification) unless such a combination of the technical features is technically infeasible. For example, in one example, the feature a + B + C is disclosed, in another example, the feature a + B + D + E is disclosed, and the features C and D are equivalent technical means for the same purpose, and technically only one feature is used, but not simultaneously employed, and the feature E can be technically combined with the feature C, then the solution of a + B + C + D should not be considered as being described because the technology is not feasible, and the solution of a + B + C + E should be considered as being described.

Drawings

Fig. 1 is a schematic flow chart of a chip initialization method according to a first embodiment of the present application

Fig. 2 is a schematic structural diagram of a chip initialization method according to a second embodiment of the present application

FIG. 3 is a block diagram illustrating an example of a structure of a chip initialization and stream code download module based on FPGA according to a second embodiment of the present application

Fig. 4 is an example of a structural block diagram of an SIP package chip initialization and stream code download module according to a second embodiment of the present application

Detailed Description

In the following description, numerous technical details are set forth in order to provide a better understanding of the present application. However, it will be understood by those skilled in the art that the technical solutions claimed in the present application may be implemented without these technical details and with various changes and modifications based on the following embodiments.

Description of partial concepts:

1, die: taking a silicon process as an example, generally, a whole silicon wafer is called wafer, and each unit is diced and packaged after passing through a process flow. The single unit die before packaging is called die.

2. Attribute block (attribute block): to a contiguous block of memory that includes a particular address on a flash memory cell.

3, SIP: the abbreviation of System In a Package, called System-In-Package, is a System or subsystem formed by a single standard Package that is used to preferentially assemble a plurality of active electronic components with different functions, optional passive devices, and other devices such as MEMS or optical devices to achieve a certain function; in terms of architecture, SIP integrates multiple functional chips, including processor, memory, etc., into one package, thereby implementing a substantially complete function.

4, SoC: the acronym of System on Chip, known as System on Chip, also known as System on Chip, means that it is a product, an integrated circuit with a specific purpose that contains the complete System with the entire contents of the embedded software.

5, SPI: the acronym of Serial Peripheral Interface, called Serial Peripheral Interface, is a high-speed, full-duplex, synchronous communication bus, and only four wires are occupied on the pins of the Chip, saving the pins of the Chip, the communication principle of SPI is simple, it works In a master-slave manner, this mode usually has a master and one or more slaves, at least 4 wires are needed, In fact 3 can also be (In one-way transmission, also common to all SPI-based devices, they are SDI (data input), SDO (data output), SCLK (Clock), CS (Chip Select), where SDI-Serial data In, Serial data input, SDO-Serial data out, Serial data output, SCLK-Serial Clock, Clock signal generated by the master, CS-Chip Select, slave enable signal, controlled by the master, where CS is the control signal whether the slave is selected by the master, that is, the operation of the master chip on the slave chip is only valid if the chip select signal is a predetermined enable signal (high or low). This makes it possible to connect multiple SPI devices on the same bus.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

A first embodiment of the present application relates to a chip initialization method.

The chip comprises a programmable logic unit and a flash memory unit containing an attribute block, wherein data in the attribute block comprises configuration information of download mode selection. Optionally, the attribute block is a contiguous block of memory stored at a particular address on the flash memory unit.

The packaging form of the chip is selected in various ways; alternatively, the chip may be a SIP package. Optionally, the chip is an SoC package.

Optionally, the packaging process is a packaging form of bonding together a die (die) of the flash memory unit and a die (die) of the programmable logic unit.

Optionally, the method according to the first embodiment of the present application is applicable to the design of programmable logic circuits and application specific integrated circuits; the variety of the programmable logic circuit is various, and optionally, the programmable logic unit comprises an FPGA and a CPLD.

The flash memory unit, which may be a volatile memory or a non-volatile memory, or alternatively, an SPI flash, may be of various kinds.

The method flow related to the first embodiment of the present application is shown in fig. 1, and specifically includes:

the execution of step 101 is started: the attribute block is synchronized. Optionally, the chip further includes a power-on detection module, configured to detect a power supply condition of the chip before attempting the synchronous detection of the attribute block and performing data synchronization, where the power supply condition starts after being normal.

Then, step 102 is executed: if the synchronization is successful, loading the data of the attribute block into a register of the programmable logic unit, finishing the selection of a downloading mode according to the data in the register, and downloading the code stream according to the selected downloading mode.

Then step 103 is executed: if the data synchronization fails, the chip is initialized and downloaded by default of a pre-configured register initial value and a default download mode through the programmable logic unit.

A second embodiment of the present application relates to a chip initialization method.

The chip comprises a programmable logic unit and a flash memory unit containing an attribute block, wherein data in the attribute block comprises configuration information of download mode selection and state information of various control register groups, and the state information of the control register groups is used for indicating the characteristics of the chip before the code stream download starts. Optionally, the attribute block is a contiguous block of memory stored at a particular address on the flash memory unit.

The packaging form of the chip is selected in various ways; alternatively, the chip may be a SIP package; optionally, the chip is an SoC package.

Alternatively, the packaging process may be, but is not limited to, a package that packages together a die (die) of a flash memory unit and a die (die) of a programmable logic unit.

The kind of the flash memory unit has various choices, and the flash memory unit is a volatile memory; alternatively, the flash memory unit may be an SPI flash.

A method flow related to the second embodiment of the present application is shown in fig. 2, and specifically includes:

the execution of step 201 is started: the attribute block is synchronized. Optionally, the chip further includes a power-on detection module, configured to detect a power supply condition of the chip before attempting the synchronous detection of the attribute block and performing data synchronization, where the power supply condition starts after being normal.

Then step 202 is executed: if the synchronization is successful, loading the data of the attribute block into a register of the programmable logic unit, and completing the selection of the download mode according to the data in the register.

Then step 203 is executed: the chip is initialized according to the data in the register in step 102.

Then, step 204 is executed: and downloading the code stream according to the download mode selected in the step 102.

Then step 205 is executed: if the data synchronization fails, the chip is initialized and downloaded by default of a pre-configured register initial value and a default download mode through the programmable logic unit.

In order to better understand the technical solutions of the present application, the following description is given with reference to two specific examples, in which the listed details are mainly for the sake of understanding and are not intended to limit the scope of the present application.

Fig. 3 is an example of a flowchart of data downloading of an attribute block (attribute block) and initialization of a chip during code stream downloading of the chip according to a second embodiment of the present application, where a programmable logic unit in the example is an FPGA unit, and a flash memory unit is an SPI flash; the example is described in detail in terms of the time axis as:

t1 start to try sync detection of the attribute block;

t2, acquiring data in the attribute block after the synchronization is successful;

t3, loading the acquired atterbte block data into an FPGA register and finishing the selection of a downloading mode;

t4, starting chip initialization;

t5, chip initialization is complete and download begins.

Fig. 4 is a block diagram of an initialization and stream code downloading module of an SIP package chip according to a second embodiment of the present application, in which the programmable logic unit is an FPGA unit and the flash memory unit is an SPI flash; the specific description of this example is:

1: the SPI flash die and the FPGA die in the SIP package are powered by the same power supply. After the power is on, after the level detected by the FPGA is stable, reading an attribute block by default in an SPI mode;

2: an attribute block is a contiguous block of memory stored at a particular address on the SPI flash. Whether valid information exists is decided by a sync word of the attribute block. And can decide whether to read attribute block at a specific time;

3: and under the condition that the attribute block cannot be synchronized, the FPGA skips the process of reading the attribute block, continues the initialization process of the architecture, and downloads the architecture in an SPI mode after the initialization is finished. Thus, the normal work of the chip can be ensured;

4: in the case where the attribute block can be synchronized, the FPGA will read the information in the attribute block and use this information to decide whether to download and configure pre _ cfg _ registers with other modes. Then, the initialization process is continued to be completed, after the initialization is completed, the downloading is started in the mode set in the attribute block, and the state of the chip is determined by using the information in the pre _ cfg _ registers in the downloading process.

It should be noted that, those skilled in the art should understand that the functions of the modules shown in the above embodiments can be realized by a program (executable instructions) running on a processor, and can also be realized by a specific logic circuit. The embodiments of the present application, if implemented in the form of software functional modules and sold or used as independent products, may also be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially implemented or portions thereof contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

Accordingly, the present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, the computer-executable instructions implement the method embodiments of the present application. Computer-readable storage media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable storage medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It is noted that, in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, same element in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that a certain action is executed according to a certain element, it means that the action is executed according to at least the element, and two cases are included: performing the action based only on the element, and performing the action based on the element and other elements. The expression of a plurality of, a plurality of and the like includes 2, 2 and more than 2, more than 2 and more than 2.

All documents mentioned in this application are to be considered as being incorporated in their entirety into the disclosure of this application so as to be subject to modification as necessary. It should be understood that the above description is only a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of the present disclosure should be included in the scope of protection of one or more embodiments of the present disclosure.

Claims

1. A chip initialization method is characterized in that the chip comprises a programmable logic unit and a flash memory unit containing an attribute block, the chip is in an SIP packaging form that a bare chip of the programmable logic unit and a bare chip of the flash memory unit are packaged together, data in the attribute block comprises configuration information of download mode selection and state information of a control register group, and the state information of the control register group is used for indicating the state of the chip before the start of code stream download;

the method comprises the following steps:

synchronizing the attribute blocks;

and if the synchronization is successful, loading the data of the attribute block into a register of the programmable logic unit, initializing the chip according to the data in the register, finishing the selection of a downloading mode according to the data in the register, and downloading the code stream according to the selected downloading mode.

2. The method of claim 1, wherein the flash memory cell is a volatile memory or a non-volatile memory, and wherein the flash memory cell comprises an SPI flash.

3. The method of claim 1, wherein the attribute block is a contiguous block of memory stored at a particular address on the flash memory cells.

4. The method of claim 3, wherein the flash memory cell is a volatile memory, and wherein the flash memory cell comprises an SPI flash.

5. The method of claim 1, further comprising:

and if the data synchronization fails, initializing the chip and downloading the stream codes through the default preconfigured register initial value and the default downloading mode of the programmable logic unit.

6. The method of claim 1, wherein the chip further comprises a power-up detection module for detecting a power-up condition of the chip before attempting the synchronous detection of the attribute blocks and performing the data synchronization.

7. The method of claim 1, wherein the method is applied to the design of programmable logic circuits and application specific integrated circuits; the programmable logic circuit comprises an FPGA and a CPLD.

8. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the steps in the method of any one of claims 1 to 7.