CN109712653A - Chip initiation method - Google Patents
Chip initiation method Download PDFInfo
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- CN109712653A CN109712653A CN201811552754.2A CN201811552754A CN109712653A CN 109712653 A CN109712653 A CN 109712653A CN 201811552754 A CN201811552754 A CN 201811552754A CN 109712653 A CN109712653 A CN 109712653A
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- chip
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- downloading
- attribute block
- programmable logic
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Abstract
This application involves Integrated circuit digital design fields, disclose a kind of chip initiation method.Pass through onboard flash memory unit, the attribute block on flash cell is read before chip initiation effectively to reduce configuration and the state instruction IO of the chip, and realize the various flexible settings of the chip before carrying under chip codeword stream by configuring various control register groups in this stage.The application is versatile, in terms of different process manufacturer and different process processing procedure, can quickly and effectively reduce in order to achieve the above objectives and redesign brought complexity and cost, provide the design safety of chip.
Description
Technical field
This application involves Integrated circuit digital design field, in particular to a kind of chip initiation method.
Background technique
Some chips (such as FPGA) need to occupy a large amount of IO for supporting selection and the instruction core of various downloading modes
(the cyclone3 chip of such as altera configures downloading mode with 4 IO msel [3:0] to the working condition of piece, with 2 IO
NCONFIG and nSTATUS indicates chip operation state), and when chip enters user working status, these IO are often unrestrained
Take and cannot function as user IO and come using especially in the case where chip package IO quantity is few, these IO are patrolled user is reduced
Available IO quantity is collected, the use of user is limited.
By taking FPGA as an example, generally pass through external memory chip (such as SPI flash) download configuration in actual use
Code stream.And the connection between SPI flash chip and fpga chip will generally use 4 IO, these IO are generally in user job
It will not be used by user logic under state, therefore the user of the fpga chip of small package can be used IO quantity extremely limited；FPGA
The configuration register of chip is normally in code stream, and chip only can just obtain these information during downloading code stream；But
Since fpga chip need a period of time, during this period of time, certain features of chip will be can not power on to downloading code stream
Programming Control (state of such as IO)；And in this case, existing design tends not to provide support well.
Summary of the invention
The application's is designed to provide a kind of chip initiation method, is on the one hand increased by reducing configuration IO quantity
Add user that can use IO quantity, on the other hand improves the chip by being just capable of providing certain attributes of chip before chip starting
User can use IO and configurable functionality flexibility.
To solve the above-mentioned problems, this application discloses a kind of chip initiation method, which includes programmable logic
Unit and flash cell comprising attribute block, the data in the attribute block include the configuration information of downloading mode selection；It should
Method includes:
The attribute block is synchronized；
If this synchronizes success, the data of the attribute block are loaded into the register of the programmable logic cells, and
Downloading mode selection is completed according to the data in the register, code stream downloading is carried out according to selected downloading mode.
In a preferred example, which is volatile memory or nonvolatile memory, which includes
SPI FLASH。
In a preferred example, the data in the attribute block further include: the status information of various control register groups is used for
Indicate the characteristic of the chip before code stream downloading starts；The attribute block is stored in the company of particular address on the flash cell
Continuous memory block.
In a preferred example, before the carry out code stream downloading, further includes: according to the data in the register to the chip into
Row initialization.
In a preferred example, which is volatile memory, which includes SPI flash.
In a preferred example, this method further include:
If the failure of data synchronization, register initial value and default are pre-configured by programmable logic cells default
Downloading mode is initialized to the chip and is flowed code downloading.
In a preferred example, which further includes powering on detection module, for detecting simultaneously in the synchronous of trial attribute block
Carry out the electric power thus supplied that the chip is detected before data synchronize.
In a preferred example, which includes SIP encapsulation and SOC encapsulation, packaging technology be by the bare die of flash cell and
Programmable logic cells bare die closes the packing forms being enclosed in together.
In a preferred example, this method is suitable for the design of programmable logic circuit and specific integrated circuit；This can be compiled
Journey logic circuit includes FPGA and CPLD.
Disclosed herein as well is a kind of computer readable storage medium, calculating is stored in the computer readable storage medium
Machine executable instruction, the computer executable instructions realize the step in method as previously described when being executed by processor.
In the application embodiment, following advantages is included at least:
(1) before chip completes initialization (this code stream does not have started downloading), by the attribute for reading internal flash unit
The data of block determine downloading mode, and to reduce the quantity of user unavailable IO in encapsulation, it is available to greatly improve user
The quantity of IO；
(2) the downloading mode configuration information that attribute block (attribute block) not only includes will also include various controls
Register group (pre_cfg_registers) processed is used to indicate the characteristic in chip chip before code stream downloading starts, such as state
Whether instruction IO is multiplexed, and IO pullup/pulldown/tri-state etc. improves the flexibility of user IO and configurable functionality with this；
(3) it can be encapsulated by simple SIP, flash die and FPGA die are closed to the SIP being enclosed in together and encapsulated, is subtracted
The function and issuable redesign flash memory (flash) and programmable logic circuit of realization (1) and (2) are in same die less
Upper bring complexity；
(4) this method is applicable not only to programmable logic circuit and the SIP encapsulation of SPI flash, has been also applied for similar
In demand ASIC Design；It is suitable for different process manufacturer, different process processing procedure simultaneously, design is simple, easy to use.
A large amount of technical characteristic is described in the description of the present application, is distributed in each technical solution, if to enumerate
Out if the combination (i.e. technical solution) of all possible technical characteristic of the application, specification can be made excessively tediously long.In order to keep away
Exempt from this problem, each technical characteristic disclosed in the application foregoing invention content, below in each embodiment and example
Each technical characteristic disclosed in disclosed each technical characteristic and attached drawing, can freely be combined with each other, to constitute each
The new technical solution (these technical solutions have been recorded because being considered as in the present specification) of kind, unless the group of this technical characteristic
Conjunction is technically infeasible.For example, disclosing feature A+B+C in one example, spy is disclosed in another example
A+B+D+E is levied, and feature C and D are the equivalent technologies means for playing phase same-action, it, can not as long as technically selecting a use
Can use simultaneously, feature E can be technically combined with feature C, then, and the scheme of A+B+C+D because technology is infeasible should not
It is considered as having recorded, and the scheme of A+B+C+E should be considered as being described.
Detailed description of the invention
Fig. 1 is a kind of chip initiation method flow diagram according to the application first embodiment
Fig. 2 is a kind of chip initiation method structural schematic diagram according to the application second embodiment
Fig. 3 is according to a kind of chip initiation based on FPGA of the application second embodiment and the knot of stream code download module
The example of structure block diagram
Fig. 4 is to encapsulate chip initiation according to a kind of SIP of the application second embodiment and flow the knot of code download module
The example of structure block diagram
Specific embodiment
In the following description, in order to make the reader understand this application better, many technical details are proposed.But this
The those of ordinary skill in field is appreciated that even if without these technical details and many variations based on the following respective embodiments
And modification, the application technical solution claimed also may be implemented.
The explanation of part concept:
The silicon wafer of full wafer: by taking silicon technology as an example, being generally called wafer by 1.die, passes through each unit after process flow
Can be by scribing, encapsulation.The bare die of individual unit before packaging is called die.
2. attribute block (attribute block): be related to include particular address on flash cell Coutinuous store block.
The abbreviation of 3.SIP:System In a Package, referred to as system in package, for by multiple with different function
Active electron component and optional passive device, and other devices such as MEMS or optical device are preferentially assemblied together,
The single standard packaging part for realizing certain function, forms a system or subsystem；From framework, SIP is will be a variety of
The functional chips such as functional chip, including processor, memory are integrated in an encapsulation, to realize a substantially complete function
Energy.
The abbreviation of 4.SoC:System on Chip, referred to as systems-on-a-chip, also there is title system on chip, it is intended that it is one
Product is the integrated circuit for having application-specific target, wherein including holonomic system and the full content for having embedded software.
The abbreviation of 5.SPI:Serial Peripheral Interface, referred to as Serial Peripheral Interface (SPI) are a kind of high speeds
, full duplex, synchronous communication bus, and four lines are only taken up on the pin of chip, save the pin of chip, SPI
Principle of Communication it is very simple, it is worked with master-slave mode, and this mode usually has a main equipment and one or more from equipment,
Need at least 4 lines, in fact 3 can also (when one-way transmission and all equipment based on SPI be shared, they are
SDI (data input), SDO (data output), SCLK (clock), CS (piece choosing), wherein SDI-SerialData In, serial number
According to input, SDO-SerialDataOut, serial data is exported, and SCLK-Serial Clock, clock signal is produced by main equipment
It is raw；CS-Chip Select is controlled from equipment enable signal by main equipment；Wherein, whether CS is to be chosen from chip by master chip
Control signal, that is to say, that only chip selection signal be prespecified enable signal when (high potential or low potential), master chip
It is just effective from the operation of chip to this.This just makes it possible to connect multiple SPI equipment in same bus.
Implementation to keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with attached drawing to the application
Mode is described in further detail.
The first embodiment of the application is related to a kind of chip initiation method.
The chip includes programmable logic cells and the flash cell comprising attribute block, the data packet in the attribute block
Include the configuration information of downloading mode selection.Optionally, which is stored in the continuous of particular address on the flash cell
Memory block.
The packing forms of the chip are multiple choices；Optionally, which can be SIP encapsulation.Optionally, the chip
It is SoC encapsulation.
Optionally, which is that the bare die (die) of flash cell and programmable logic cells bare die (die) are closed envelope
Packing forms together.
Optionally, the method that the application first embodiment is related to is suitable for programmable logic circuit and specific integrated circuit
Design in；The type of the programmable logic circuit be it is various, optionally, the programmable logic cells include FPGA and
CPLD。
The type of the flash cell has various selections, which is volatile memory or non-volatile memories
Device, optionally, the flash cell can be SPI flash.
Method flow that the application first embodiment is related to as shown in Figure 1, specifically:
Start to execute step 101: the attribute block is synchronized.Optionally, which further includes powering on detection module,
For detecting in the synchronization for attempting attribute block and carrying out the electric power thus supplied for detecting the chip before data synchronize, the electric power thus supplied is just
It is normal then the step of after starting.
Step 102 is executed later: if this synchronizes success, the data of the attribute block being loaded into the programmable logic list
In the register of member, and downloading mode selection is completed according to the data in the register, is carried out according to selected downloading mode
Code stream downloading.
Step 103 is executed later: if the failure of data synchronization, being pre-configured and is posted by programmable logic cells default
Storage initial value and default downloading mode are initialized to the chip and are flowed code downloading.
The second embodiment of the application is related to a kind of chip initiation method.
The chip includes programmable logic cells and the flash cell comprising attribute block, the data packet in the attribute block
Include the configuration information of downloading mode selection and the status information of various control register groups, the status information of the control register group
It is used to indicate the characteristic of the chip before code stream downloading starts.Optionally, which is stored on the flash cell
The Coutinuous store block of particular address.
The packing forms of the chip are multiple choices；Optionally, which can be SIP encapsulation；Optionally, the chip
It is SoC encapsulation.
Optionally, the packaging technology can with but it is unlimited be that the bare die (die) and programmable logic cells of flash cell is naked
Piece (die) closes the encapsulation being enclosed in together.
Optionally, the method that the application first embodiment is related to is suitable for programmable logic circuit and specific integrated circuit
Design in；The type of the programmable logic circuit be it is various, optionally, the programmable logic cells include FPGA and
CPLD。
The type of the flash cell has various selections, which is volatile memory；Optionally, the flash cell
It can be SPI flash.
Method flow that the second embodiment of the application is related to as shown in Fig. 2, specifically:
Start to execute step 201: the attribute block is synchronized.Optionally, which further includes powering on detection module,
For detecting in the synchronization for attempting attribute block and carrying out the electric power thus supplied for detecting the chip before data synchronize, the electric power thus supplied is just
It is normal then the step of after starting.
Step 202 is executed later: if this synchronizes success, the data of the attribute block being loaded into the programmable logic list
In the register of member, and downloading mode selection is completed according to the data in the register.
Step 203 is executed later: the chip being initialized according to the data in the register in step 102.
Step 204 is executed later: code stream downloading is carried out according to the downloading mode selected in step 102.
Step 205 is executed later: if the failure of data synchronization, being pre-configured and is posted by programmable logic cells default
Storage initial value and default downloading mode are initialized to the chip and are flowed code downloading.
In order to more fully understand the technical solution of the application, it is illustrated below with reference to two specific examples,
The details enumerated in the example is primarily to be easy to understand, not as the limitation to the application protection scope.
Fig. 3 is that attribute block (attribute during load is flowed down according to a kind of chip codeword of the application second embodiment
Block data) are downloaded and an example of the chip initiation flow chart, and the programmable logic cells in the example are FPGA
Unit, flash cell are SPI flash；The example is specifically described according to time shaft are as follows:
T1: the synchronous detection of attribute block is begun trying；
T2: after synchronizing successfully, the data in attribute block are obtained；
T3: the attribte block data that will acquire are loaded into FPGA register, and complete downloading mode selection；
T4: start chip initiation；
T5: chip initiation is completed and starts to download.
Fig. 4 is initialization and the stream code download module that chip is encapsulated according to a kind of SIP of the application second embodiment
Structural block diagram, the programmable logic cells in the example are FPGA unit, and flash cell is SPI flash；The example it is specific
Description are as follows:
SPI flash die and FPGA die passes through same power supply power supply in 1:SIP encapsulation.After powering on, detected in FPGA
Level equalization after, default start in spi modes read attribute block；
2:attribute block is stored in the Coutinuous store block of particular address on SPI flash.Pass through
The synchronization character of attribute block decides whether that there are effective informations.And it can decide whether to read in specific time
attribute block；
3: in the case where that can not synchronize attribute block, FPGA reads the mistake of attribute block by skipping
Journey continues its initialization procedure, and downloads in spi modes after completing initialization.It can guarantee that chip can work normally in this way；
4: in the case where that can synchronize attribute block, FPGA will read the letter in attribute block
Breath, and decided whether that pre_cfg_registers is downloaded and configured with other modes with this information.Then proceed to complete it initially
Change process starts to download, and use in downloading process after completing initialization with the mode set in attribute block
Information in pre_cfg_registers determines the state of chip.
It should be noted that it will be appreciated by those skilled in the art that the function of each module shown in above-mentioned embodiment
It can be realized, can also be realized by specific logic circuit and running on the program on processor (executable instruction).
If the embodiment of the present application is realized and when sold or used as an independent product in the form of software function module, can also deposit
Storage is in a computer readable storage medium.Based on this understanding, the technical solution of the embodiment of the present application substantially or
Person says that the part that contributes to existing technology can be embodied in the form of software products, computer software product storage
In one storage medium, including some instructions are used so that computer equipment (can be personal computer, server,
Or network equipment etc.) execute each embodiment the method for the application all or part.And storage medium above-mentioned includes:
USB flash disk, mobile hard disk, read-only memory (ROM, Read Only Memory), magnetic or disk etc. are various to can store program
The medium of code.It is combined in this way, the embodiment of the present application is not limited to any specific hardware and software.
Correspondingly, the application embodiment also provides a kind of computer readable storage medium, wherein being stored with computer can
It executes instruction, which realizes each method embodiment of the application when being executed by processor.Computer can
Reading storage medium includes that permanent and non-permanent, removable and non-removable media can be accomplished by any method or technique
Information storage.Information can be computer readable instructions, data structure, the module of program or other data.The storage of computer
The example of medium includes but is not limited to that phase change memory (PRAM), static random access memory (SRAM), dynamic randon access are deposited
Reservoir (DRAM), other kinds of random access memory (RAM), read-only memory (ROM), electrically erasable is read-only deposits
Reservoir (EEPROM), flash memory or other memory techniques, read-only disc read only memory (CD-ROM) (CD-ROM), digital multi light
Disk (DVD) or other optical storage, magnetic cassettes, tape magnetic disk storage or other magnetic storage devices or any other is non-
Transmission medium, can be used for storage can be accessed by a computing device information.As defined in this article, computer-readable storage medium
Matter does not include temporary computer readable media (transitory media), such as the data-signal and carrier wave of modulation.
It should be noted that relational terms such as first and second and the like are only in the application documents of this patent
For distinguishing one entity or operation from another entity or operation, without necessarily requiring or implying these entities
Or there are any actual relationship or orders between operation.Moreover, the terms "include", "comprise" or its any other
Variant is intended to non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only
It including those elements, but also including other elements that are not explicitly listed, or further include for this process, method, object
Product or the intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence " including one ", not
There is also other identical elements in the process, method, article or apparatus that includes the element for exclusion.The application of this patent
In file, if it is mentioned that certain behavior is executed according to certain element, then refers to the meaning for executing the behavior according at least to the element, wherein
Include two kinds of situations: executing the behavior according only to the element and the behavior is executed according to the element and other elements.Multiple,
Repeatedly, the expression such as a variety of include 2,2 times, 2 kinds and 2 or more, 2 times or more, two or more.
It is included in disclosure of this application with being considered as globality in all documents that the application refers to, so as to
It can be used as the foundation of modification if necessary.In addition, it should also be understood that, the foregoing is merely the preferred embodiments of this specification, and
The non-protection scope for being used to limit this specification.It is all this specification one or more embodiment spirit and principle within, institute
Any modification, equivalent substitution, improvement and etc. of work, should be included in this specification one or more embodiment protection scope it
It is interior.
Claims (10)
1. a kind of chip initiation method, which is characterized in that the chip includes programmable logic cells and comprising attribute block
Flash cell, the data in the attribute block include the configuration information of downloading mode selection；The described method includes:
The attribute block is synchronized；
If described synchronize success, the data of the attribute block are loaded into the register of the programmable logic cells,
And downloading mode selection is completed according to the data in the register, code stream downloading is carried out according to selected downloading mode.
2. the method according to claim 1, wherein the flash cell is volatile memory or non-volatile
Memory, the flash cell include SPI flash.
3. the method according to claim 1, wherein the data in the attribute block further include: various controls
The status information of register group is used to indicate the characteristic of the chip before code stream downloading starts；The attribute block is
It is stored in the Coutinuous store block of particular address on the flash cell.
4. according to the method described in claim 3, it is characterized in that, before the progress code stream downloading, further includes: according to described
Data in register initialize the chip.
5. mode according to claim 4, which is characterized in that the flash cell is volatile memory, the flash memory
Unit includes SPI flash.
6. the method according to claim 1, wherein the method also includes:
If the failure of data synchronization, is defaulted by the programmable logic cells and be pre-configured register initial value and default
Downloading mode is initialized to the chip and is flowed code downloading.
7. the method according to claim 1, wherein the chip further includes powering on detection module, for tasting
The synchronous electric power thus supplied detected and carry out the detection chip before data synchronize of examination attribute block.
8. encapsulating work the method according to claim 1, wherein the chip includes SIP encapsulation and SoC encapsulation
Skill includes that the bare die of flash cell and programmable logic cells bare die are closed the packing forms being enclosed in together.
9. the method according to claim 1, wherein the method is suitable for programmable logic circuit and dedicated collection
At in the design of circuit；The programmable logic circuit includes FPGA and CPLD.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer in the computer readable storage medium
Executable instruction is realized as described in any one of claim 1 to 9 when the computer executable instructions are executed by processor
Method in step.
Applications Claiming Priority (2)
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| CN201810164073 | 2018-02-27 | ||
| CN2018101640732 | 2018-02-27 |
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Cited By (1)
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| CN111949597A (en) * | 2020-07-02 | 2020-11-17 | 江苏华创微系统有限公司 | Internal register structure for on-chip power-on initialization |
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