CN109684253A - Data transmission control circuit - Google Patents
Data transmission control circuit Download PDFInfo
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- CN109684253A CN109684253A CN201710976860.2A CN201710976860A CN109684253A CN 109684253 A CN109684253 A CN 109684253A CN 201710976860 A CN201710976860 A CN 201710976860A CN 109684253 A CN109684253 A CN 109684253A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
Abstract
It includes universal asynchronous receiving-transmitting transmitter (UART), data transmission conversion element and control circuit that the present invention, which provides a kind of data transmission control circuit,.Control signal is coupled to the transmission end TX of UART, and the voltage level of data transmission conversion element driving data input is determined according to the voltage level of transmission end TX.When transmission end TX is first voltage level, the high voltage level that control circuit provides is exported to the driving enable pin of data transmission conversion element so that the single-ended transmission signal for driving data input pin is converted to differential transmission signal by data transmission conversion element.
Description
Technical field
The invention relates to a kind of data transmission control circuits, especially interrogate for single-ended transmission signal and differential transmission
Number conversion data transmission control circuit.
Background technique
In general, in personal computer, notebook computer, tablet computer or point-of-sale intelligence channel machine
(Point of Sale；POS) board etc., due to transport interface or the difference of standard, still needs between electronic devices or electronic component
The transmitting just to there is method to carry out data by some conversions.For RS-232 and RS-485 serial port standard, the news of data
Number be delivered in the interface RS-232 as single-ended transmission, and be then differential transmission in the interface RS-485, therefore, signal there is still a need for
Data could be transmitted mutually by conversion appropriate.
Further, since the interface of RS-485 is half-duplex (Half Duplex), single direction can only be allowed in the same time
Transmission (for example, sending or receive), also therefore between the interface RS-232 and the interface RS-485 signal conversion, need to do into
The controlling mechanism of one step is to switch sending or receive for the interface RS-485.However traditionally for the switching operated, electronics
The processing unit of device also needs to control using additional GPIO pin and corresponding control program, and it is single not only to increase processing
The work loading of member, the opposite speed for slowing down processing unit, while also quite expending time and cost.Therefore, it is still necessary to
A kind of data transmission control circuit of improvement is to improve the above problem.
Summary of the invention
That the technical problem to be solved in the present invention is to provide a kind of circuit designs is simple, processing speed is fast, manufacturing cost
Low data transmission control circuit.
In order to solve the above technical problems, the data transmission control circuit of one embodiment of the invention, is suitable for an electronic device,
Include: a universal asynchronous receiving-transmitting transmitter (UART), has a transmission end (TX)；One data transmission conversion element has one
It drives enable pin (DE), driving data input (Driver data input) pin and a differential transmission end (A, B),
And above-mentioned driving data input pin is coupled to above-mentioned transmission end；And a control circuit, there is a control signal and one
Control output end, above-mentioned control signal are coupled to the above-mentioned transmission end of above-mentioned universal asynchronous receiving-transmitting transmitter (UART)
(TX), above-mentioned control output end is coupled to the above-mentioned driving enable pin of above-mentioned data transmission switching element, and according to above-mentioned control
The voltage level of input terminal processed determines the voltage level of above-mentioned control output end；Wherein, when the above-mentioned control of above-mentioned control circuit
When input terminal is a first voltage level, above-mentioned control output end one high voltage level of output to above-mentioned driving enable pin, with
Make above-mentioned data transmission conversion element that one single-ended transmission signal of above-mentioned driving data input pin is converted to a differential transmission
Signal is exported from above-mentioned differential transmission end.
Preferably, when the above-mentioned control signal of above-mentioned control circuit is a second voltage level, above-mentioned control output
End output ground voltage to above-mentioned driving enable pin, above-mentioned data transmission conversion element stopping connects above-mentioned driving data input
The above-mentioned single-ended transmission signal of foot is converted to above-mentioned differential transmission signal, so that above-mentioned data transmission conversion element is above-mentioned differential
Transmission end is zero potential.In addition, above-mentioned first voltage level is low-voltage level (LOW), and above-mentioned second voltage level is height
Voltage level (HIGH).
Preferably, above-mentioned control circuit includes a MOS transistor, and the gate of above-mentioned MOS transistor is coupled to above-mentioned general
The above-mentioned transmission end of asynchronous receiving-transmitting transmitter, the source electrode of above-mentioned MOS transistor is coupled to ground connection (GND) and above-mentioned MOS is brilliant
The drain of body pipe is coupled to the voltage node with above-mentioned high voltage level.
Preferably, above-mentioned universal asynchronous receiving-transmitting transmitter further includes a receiving end (RX), and above-mentioned data transmission is converted
Element further includes receiving data output (Receive data output) pin, above-mentioned universal asynchronous receiving-transmitting transmitter
Above-mentioned receiving end is coupled to the above-mentioned of above-mentioned data transmission conversion element and receives data output connecting pin.
Preferably, above-mentioned data transmission conversion element further include one it is counter receive enable pin (/RE), when above-mentioned control circuit
Above-mentioned control signal when being a second voltage level, above-mentioned control output end exports ground voltage and counter receives enable to above-mentioned
Pin so that above-mentioned data transmission conversion element the above-mentioned differential transmission signal at above-mentioned differential transmission end is converted to it is above-mentioned single-ended
Transmission signal receives the output of data output connecting pin from above-mentioned.
Preferably, above-mentioned anti-enable pin and the above-mentioned driving enable pin received couples, above-mentioned when above-mentioned control circuit
When control signal is a first voltage level, above-mentioned control output end output HIGH voltage level, above-mentioned data transmission conversion member
The above-mentioned differential transmission signal at above-mentioned differential transmission end is converted to above-mentioned single-ended transmission signal and receives data from above-mentioned by part stopping
Output connecting pin output.
Preferably, the above-mentioned transmission end of above-mentioned universal asynchronous receiving-transmitting transmitter belongs to the interface RS-232, and above-mentioned differential
Transmission end is the interface RS-485.
Preferably, above-mentioned differential transmission signal is the transmission signal of half-duplex (half-duplex) kenel.
Compared to the prior art, data transmission control circuit of the present invention, when the transmission end Tx of UART is low-voltage level,
The differential transmission end A of data transmission conversion element is low-voltage level, and differential transmission end B is then high voltage level.Anti-, when
When the transmission end Tx of UART is high voltage level, differential transmission end A, B of data transmission conversion element are then zero potential simultaneously.Cause
This, the electronic component or device being coupled on differential transmission end A, B still are able to according to the upper differential transmission signal of differential transmission end A, B
Timing judge with logic and obtain corresponding UART transmission end Tx data.On the other hand, due to the transmission end of UART
Tx can transmit low-voltage level, such as the beginning bit (Start bit) of low-voltage level in progress data transmission, through control
Circuit can automatically and synchronously open the driving of data transmission conversion element when receiving transmission end Tx low-voltage level
Function, without additionally carrying out control data transmission through a GPIO foot on UART to generate an additional control signal
The translative mode of conversion element simplifies the design of circuit, reduces the cost of the manufacturing.
[Detailed description of the invention]
Fig. 1 is the schematic diagram for showing data transmission control circuit described in an embodiment according to the present invention.
Fig. 2 is the waveform diagram for showing each signal in data transmission control circuit described in an embodiment according to the present invention.
[specific embodiment]
Please referring to is the schematic diagram for showing data transmission control circuit 100 described in an embodiment according to the present invention shown in Fig. 1.Money
Expect that transmission control circuit 100 is used in electronic device, for example, personal computer, notebook computer, tablet computer or pin
Sell time point intelligence channel machine (Point of Sale；POS) in the electronic devices such as board, mainly to convert the format of signal
It is another format to carry out the data transmission between element or electronic device.
Refering to Figure 1, data transmission control circuit 100 includes universal asynchronous receiving-transmitting transmitter 102
(Universal Asynchronous Receiver/Transmitter；Hereinafter referred to as UART 102), control circuit 104 with
And data transmission conversion element 106.Data transmission conversion element 106 is to the single-ended transmission on the transmission end Tx by UART 102
The differential transmission signal that signal is converted to half-duplex (half-duplex) is exported in differential transmission end A, B, and will be input into difference
The semiduplex differential transmission signal of dynamic transmission end A, B is converted to single-ended transmission signal and is sent to receiving end Rx.Control circuit 104
Then according to the signal on the Tx of transmission end, switch the translative mode of data transmission conversion element 106.
In some embodiment of the invention, UART 102 can be an independent modularization chip, or be integrated and be included in
In the processor of electronic device, UART 102 includes transmission end to provide or receive single-ended transmission signal, UART 102
Tx and receiving end Rx is respectively to transmit and receive single-ended transmission signal, for example, the end TXD and the end RXD at the interface RS-232.It answers
Recognize, since transmission end Tx and receiving end Rx is coupled to the electricity with high voltage level (HIGH) via resistance R1, R2 respectively
Potential source Vcc, therefore transmission end Tx and receiving end Rx can maintain high voltage in the case where not being transmitted or reception data
Level.In addition, the voltage level and tolerance level of transmission signal are also different with the difference of transport interface, one
As for, the voltage level of signal is between ± 3 ~ ± 15V under the interface RS-232, the common-mode voltage of signal under the interface RS-422
Between -7 ~+7V, and the common-mode voltage of signal is between -7 ~+12V under the interface RS-485.Therefore, in some embodiments, if
UART 102 is the interface RS-232, and data transmission conversion element 106 is the interface RS-485, then UART 102 and control circuit
It may be provided with voltage-regulating circuit or element between 104, adjusting the voltage level of signal to corresponding interface, to keep away
The voltage level for exempting from the signal on UART 102 causes data transmission conversion member beyond the range (for example, ± 15V) of -7 ~+12V
Part 106 can not interpretation.Or the model for avoiding the voltage level of signal on data transmission conversion element 106 from exceeding ± 3 ~ ± 15V
It encloses (for example, 2V) and causes UART 102 can not interpretation.It will be understood that the above voltage range is only used for illustrating, it is not limited to
The present invention can also have different voltage ranges with the difference of applied electronic device and circuit.
Data transmission conversion element 106 has driving data input pin Dr, receives data output connecting pin R, driving enable
Pin DE, anti-enable pin (/RE), differential transmission end A and differential transmission end B are received.Data transmission conversion element 106
The transmission end Tx of data input pin Dr and UART 102 is driven to couple, with the data from UART 102 of reception, data transmission
The receiving end Rx for receiving data output connecting pin R and UART 102 of conversion element 106 is coupled, to transmit data to UART 102.
Differential transmission end A and differential transmission end B may be coupled to other electronic component or electronics dresses with identical differential transport interface
It sets and (is not depicted in diagram).
In some embodiment of the invention, when the driving enable pin DE of data transmission conversion element 106 is high voltage position
On time, driving function is enabled, and data transmission conversion element 106 then can be by list received by driving data input pin Dr
By differential transmission end A and B (for example, the end D- at the interface RS-485 after holding transmission signal to be converted to semiduplex differential transmission signal
And the end D+) export to other electronic components or electronic device (not shown) being connected.In some embodiments, data transmission turns
When the driving enable pin DE for changing element 106 is high voltage level, the differential transmission end A of data transmission conversion element 106 can be defeated
Out with driving data input pin Dr with the signal of phase, and the signal between differential transmission end A and B is reverse phase.As shown in Fig. 2,
When driving enable pin DE is high voltage level, when the signal of driving data input pin Dr is (that is, the transmission end of UART 102
The signal of Tx) be high voltage level when, differential transmission end A be high voltage level, differential transmission end B is then low-voltage level.Instead
, it is poor when differential transmission end A is low-voltage level when the signal of data input pin Dr is low-voltage level
Dynamic transmission end B is then high voltage level.
In addition, in some embodiment of the invention, anti-enable pin (/RE) of receiving should be regarded as receiving the anti-of enable pin
In other words phase when to receive enable pin/RE be not high voltage level for data transmission conversion element 106 counter, receives function
It can be enabled, differential transmission signal received by differential transmission end A and B is then converted to list by data transmission conversion element 106
By receiving data output connecting pin R output after the transmission signal of end.It will be understood that in some embodiments, it is counter to receive enable such as Fig. 1
Pin (/RE) and driving enable pin DE are electrically connected, and data transmission conversion element 106 can be made only in the same time whereby
The single-ended transmission signal of data input pin Dr is converted into differential transmission signal and is exported by differential transmission end A and B, or will
The differential transmission signal of differential transmission end A and B is converted to single-ended transmission signal by receiving data output connecting pin R output, Bu Huitong
Time carries out the two and causes data interpretation mistake.That is, when the counter of data transmission conversion element 106 receives enable and connects
When foot/RE is ground connection, since driving enable pin DE is all ground connection, data transmission conversion element 106 also stops that data will be driven
Single-ended transmission signal received by input pin Dr is converted to differential transmission signal.When the drive of data transmission conversion element 106
When dynamic enable pin DE is high voltage level, since the anti-enable pin/RE that receives is all high voltage level, data transmission conversion member
Part 106 also stops the differential transmission signal that differential transmission end A and B are received being converted to single-ended transmission signal.
In some embodiment of the invention, control circuit 104 is according to the signal on the Tx of transmission end, to determine output to data
It transmits the driving enable pin DE of conversion element 106 and counter receives enable pin/RE voltage level.Control circuit 104 is main
It is completed through transistor MOS, transistor MOS is metal oxide semiconductcor field effect transistor (MOSFET), transistor MOS's
Gate G is coupled to the transmission end Tx of UART 102 through resistance R3, and the source S of transistor MOS is coupled to ground terminal GND, crystal
The drain D of pipe MOS is coupled to voltage source Vcc through resistance R4, and the drain D of transistor MOS is also coupled to driving enable pin
DE receives enable pin (/RE) with counter.It will be understood that in other embodiments of the invention, the transistor of control circuit 104
MOS also can pass through equivalent bipolar transistor (BJT) Lai Shixian, be not limited to this.
The control circuit when waveform diagram of Fig. 2 more being cooperated to illustrate the transmission end Tx transmission data of UART 102 of the present invention below
104 operation situation.In some embodiment of the invention, when the transmission end Tx of UART 102 is in transmission low-voltage level (Low)
Data when, when the gate G of transistor MOS receives the low-voltage level that it starts bit via resistance R3, transistor MOS is then
It is not turned on.At this point, the voltage source Vcc of high voltage level (HIGH) can then be mentioned via resistance R4 in the drain D of transistor MOS
Be supplied to data transmission conversion element 106 driving enable pin DE and it is counter receive enable pin (/RE), and then start data pass
The driving function of defeated conversion element 106.Simultaneously as driving enable pin DE is high voltage level, data transmission conversion element
106 single-ended transmission signal can will be converted to after differential transmission signal by differential biography received by driving data input pin Dr
Defeated end A and B output, the signal of driving data input pin Dr is low-voltage level, and differential transmission end A is low-voltage level,
Differential transmission end B is then high voltage level.
On the other hand, in some embodiment of the invention, when the transmission end Tx of UART 102 is in transmission high voltage level
(High) data is not being transmitted when maintaining high voltage level, and the gate G of transistor MOS is received via resistance R3
When starting the high voltage level of bit to it, drain D and source S can be then connected in transistor MOS.At this point, drawing in transistor MOS
Pole D because transistor MOS be connected due to be grounded, ground terminal be then provided to the driving enable pin DE of data transmission conversion element 106 with
And it is counter receive enable pin (/RE), and then close data transmission conversion element 106 driving function.At this time due to driving enable
Pin DE is ground connection, and data transmission conversion element 106 will stop the signal of conversion driving data input pin Dr, so that differential
Transmission end A and B output are zero potential.
Refering to Fig. 2 and above description it is found that in data transmission control circuit 100 of the invention, when the biography of UART 102
When sending end Tx is low-voltage level, the differential transmission end A of data transmission conversion element 106 is low-voltage level, differential transmission end B
It is then high voltage level.Anti-, when the transmission end Tx of UART 102 is high voltage level, data transmission conversion element 106
Differential transmission end A, B are then zero potential simultaneously.Therefore, the electronic component or device being coupled on differential transmission end A, B still are able to
Timing according to the upper differential transmission signal of differential transmission end A, B judges with logic and obtains the transmission end of corresponding UART 102
The data of Tx.On the other hand, low-voltage level can be transmitted in progress data transmission due to the transmission end Tx of UART 102, such as low
The beginning bit (Start bit) of voltage level can receive transmission end Tx low-voltage level through control circuit 104
When, the driving function of data transmission conversion element 106 automatically and is synchronously opened, without additional saturating on UART 102
A GPIO foot is crossed to generate the translative mode that an additional control signal carrys out control data transmission conversion element 106, is simplified
The design of circuit, reduces the cost of the manufacturing.
Method of the invention or specific kenel or its part can exist with the kenel of procedure code.Procedure code may include
In tangible media, such as floppy disk, disc, hard disk or any other machine-readable (such as computer-readable) storage media,
Or it is not limited to the computer program product of external form, wherein when procedure code is by machine, when being loaded into and execute such as computer,
This machine becomes to participate in the device of the invention.Procedure code can also penetrate some transmission media, such as electric wire or cable, light
Fine or any transmission kenel is transmitted, wherein when procedure code is by machine, when receiving, be loaded into and execute such as computer, this
Machine becomes to participate in the device of the invention.In general service processing unit implementation, procedure code combination processing unit is mentioned
The unique apparatus using particular logic circuit is similar to for an operation.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
It covers in protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of data transmission control circuit is suitable for an electronic device characterized by comprising
One universal asynchronous receiving-transmitting transmitter has a transmission end；
One data transmission conversion element has a driving enable pin, a driving data input pin and a differential transmission end,
And above-mentioned driving data input pin is coupled to above-mentioned transmission end；
One control circuit has a control signal and a control output end, and above-mentioned control signal is coupled to above-mentioned general
The above-mentioned transmission end of asynchronous receiving-transmitting transmitter, above-mentioned control output end are coupled to the above-mentioned drive of above-mentioned data transmission switching element
Enable pin is moved, and determines the voltage level of above-mentioned control output end according to the voltage level of above-mentioned control signal；
When the above-mentioned control signal of above-mentioned control circuit is a first voltage level, the high electricity of above-mentioned control output end output one
Press level to above-mentioned driving enable pin, so that above-mentioned data transmission conversion element is single by the one of above-mentioned driving data input pin
End transmission signal is converted to a differential transmission signal and exports from above-mentioned differential transmission end.
2. data transmission control circuit according to claim 1, it is characterised in that: above-mentioned first voltage level is low-voltage
Level.
3. data transmission control circuit according to claim 1, it is characterised in that: when the above-mentioned control of above-mentioned control circuit
When input terminal is a second voltage level, above-mentioned control output end exports ground voltage to above-mentioned driving enable pin, above-mentioned money
Material transmission conversion element stops the above-mentioned single-ended transmission signal of above-mentioned driving data input pin being converted to above-mentioned differential transmission
Signal, so that the above-mentioned differential transmission end of above-mentioned data transmission conversion element is zero potential.
4. data transmission control circuit according to claim 3, it is characterised in that: above-mentioned first voltage level is low-voltage
Level, and above-mentioned second voltage level is high voltage level.
5. data transmission control circuit according to claim 1, it is characterised in that: above-mentioned control circuit includes a MOS brilliant
Body pipe, the gate of above-mentioned MOS transistor are coupled to the above-mentioned transmission end of above-mentioned universal asynchronous receiving-transmitting transmitter, and above-mentioned MOS is brilliant
The source electrode of body pipe is coupled to ground connection and the drain of above-mentioned MOS transistor is coupled to the voltage section with above-mentioned high voltage level
Point.
6. data transmission control circuit according to claim 1, it is characterised in that: above-mentioned universal asynchronous receiving-transmitting transmitter
It further include a receiving end, and above-mentioned data transmission conversion element further includes receiving data output connecting pin, above-mentioned universal asynchronous
The above-mentioned receiving end of receiving-transmitting transmitter is coupled to the above-mentioned of above-mentioned data transmission conversion element and receives data output connecting pin.
7. according to data transmission control circuit of the claim as described in 6, it is characterised in that: above-mentioned data transmission conversion element is also
Including one it is counter receive enable pin, when the above-mentioned control signal of above-mentioned control circuit be a second voltage level when, above-mentioned control
Output end processed export ground voltage to it is above-mentioned it is counter receive enable pin so that above-mentioned data transmission conversion element is by above-mentioned differential biography
The above-mentioned differential transmission signal at defeated end is converted to above-mentioned single-ended transmission signal and receives the output of data output connecting pin from above-mentioned.
8. data transmission control circuit according to claim 7, it is characterised in that: it is above-mentioned it is counter receive enable pin with it is above-mentioned
The coupling of enable pin is driven, when the above-mentioned control signal of above-mentioned control circuit is a first voltage level, above-mentioned control is defeated
Outlet output HIGH voltage level, above-mentioned data transmission conversion element stop the above-mentioned differential transmission signal at above-mentioned differential transmission end
It is converted to above-mentioned single-ended transmission signal and receives the output of data output connecting pin from above-mentioned.
9. data transmission control circuit according to claim 1, it is characterised in that: above-mentioned universal asynchronous receiving-transmitting transmitter
Above-mentioned transmission end belong to the interface RS-232, and above-mentioned differential transmission end is the interface RS-485.
10. data transmission control circuit according to claim 1, it is characterised in that: above-mentioned differential transmission signal is half pair
The transmission signal of drum state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710976860.2A CN109684253A (en) | 2017-10-19 | 2017-10-19 | Data transmission control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710976860.2A CN109684253A (en) | 2017-10-19 | 2017-10-19 | Data transmission control circuit |
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| Publication Number | Publication Date |
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| CN109684253A true CN109684253A (en) | 2019-04-26 |
Family
ID=66184095
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710976860.2A Pending CN109684253A (en) | 2017-10-19 | 2017-10-19 | Data transmission control circuit |
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| CN (1) | CN109684253A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI829060B (en) * | 2021-12-29 | 2024-01-11 | 新唐科技股份有限公司 | Processing circuit, control system and control method |
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| TWI829060B (en) * | 2021-12-29 | 2024-01-11 | 新唐科技股份有限公司 | Processing circuit, control system and control method |
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Application publication date: 20190426 |
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