CN109669804B - Method and apparatus for reducing the actual soft error rate of a storage area of an ECC memory - Google Patents

Method and apparatus for reducing the actual soft error rate of a storage area of an ECC memory Download PDF

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CN109669804B
CN109669804B CN201811442659.7A CN201811442659A CN109669804B CN 109669804 B CN109669804 B CN 109669804B CN 201811442659 A CN201811442659 A CN 201811442659A CN 109669804 B CN109669804 B CN 109669804B
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storage area
disassembly
level
ecc memory
error rate
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CN109669804A (en
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张战刚
雷志锋
彭超
何玉娟
黄云
恩云飞
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China Electronic Product Reliability and Environmental Testing Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Abstract

The invention relates to a method and a device for reducing the actual soft error rate of a storage area of an ECC memory. There is provided a method for reducing an actual soft error rate of a storage area of an ECC memory, the method comprising: acquiring a functional relation of the actual soft error rate of a storage area of an ECC memory; determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation; determining the number of words and the number of bits in a single word of a storage area after k-level disassembly is performed on a storage architecture of the ECC storage according to the disassembly level k; and determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained number of bits in a single word. The method disassembles the single word of the storage area into a plurality of words, reduces the soft error rate of the ECC memory, effectively improves the soft error resistance of the storage area of the ECC memory, and enhances the reliability of the ECC memory.

Description

Method and apparatus for reducing the actual soft error rate of a storage area of an ECC memory
Technical Field
The present invention relates to the field of electronic device reliability, and more particularly to a method and apparatus for reducing the actual soft error rate of a storage area of an ECC memory.
Background
Soft errors may occur during use of the memory, and the causes of soft errors include radiation particles (alpha particles, neutrons, protons, heavy ions, etc.), random noise, signal integrity problems, manufacturing or design defects, critical cells, etc. When a soft error occurs, the stored data of the memory changes, which affects the correctness of the output data and further affects the system operation.
Ecc (error correction code), which is an error correction code, is to add some check bits to the original memory data bits for detecting and correcting soft errors. One of the most commonly used ECC codes is the hamming code, which can realize the functions of correcting one bit error and detecting two bit errors, i.e. "correct one bit and detect two bits". ECC circuits are often used in conjunction with interleaved architecture, refresh, to eliminate soft errors in memory.
With the continuous improvement of the integration degree of the memory, the distance between the memory cells is continuously reduced, the critical charge of the memory cells is continuously reduced, and soft errors are more likely to occur, and the two factors jointly cause the probability of the ECC memory failure to increase. At present, some researches on the relationship between the failure probability of an ECC memory, the probability of soft errors occurring in storage bits and a storage architecture have been made, but a storage area soft error resistant optimization design method for the ECC memory is lacked, so that a memory using an advanced process faces a greater ECC failure risk.
Disclosure of Invention
Based on this, it is necessary to provide a method and apparatus for reducing the actual soft error rate of the storage area of the ECC memory in view of the current problem of lacking an effective soft error resistant optimization design method for the storage area of the ECC memory.
According to one aspect of the present invention, there is provided a method for reducing an actual soft error rate of a storage area of an ECC memory, the method comprising: acquiring a functional relation of the actual soft error rate of a storage area of an ECC memory; determining a disassembly level k for disassembling a storage architecture of the ECC memory according to the functional relationship, wherein k is an integer greater than or equal to 1; determining the number of words and the number of bits in a single word of a storage area after k-level disassembly is performed on a storage architecture of the ECC storage according to the disassembly level k; and determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained number of bits in a single word.
In one embodiment, obtaining the functional relationship of the actual soft error rate of the storage area of the ECC memory comprises: a mathematically derived functional relationship between the actual soft error rate of a storage region of an ECC memory and the number of words in the storage region and the number of bits in a single word is obtained.
In one embodiment, determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship includes: and determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, a preset target soft error rate and system parameters, wherein the system parameters comprise the bandwidth, the working frequency and the power consumption of a system applying the ECC memory.
In one embodiment, the ECC is a hamming code with a function of correcting one error and two errors, and the function relationship of the obtained actual soft error rate of the storage area of the ECC memory is as follows:
Figure GDA0001971206780000021
or
Figure GDA0001971206780000022
Wherein R issystemFor the actual soft error rate, T, of the storage area of the ECC memory when the ECC function is turned onscrubIs the refresh period of the ECC memory, NwNumber of words, N, being a storage area of an ECC memorybRefers to the number of bits in a single word, RrawThe original soft error rate of the ECC memory in the storage area when the ECC function is closed.
In one embodiment, determining the number of words and the number of bits in a single word of the memory area after the k-level disassembly of the memory architecture of the ECC memory according to the disassembly level k includes determining the number of words and the number of bits in a single word of the memory area after the k-level disassembly of the memory architecture of the ECC memory according to the following formulas:
Nw,k＝Nw，0·2k，
Nb,k＝Nd,k+Nc,k，
wherein N isw,kAfter k-level disassemblyNumber of words, N, of a storage area of an ECC memoryw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits N after k-level disassemblyd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000031
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In one embodiment, determining the actual soft error rate of the memory area of the ECC memory after performing k-level disassembly according to the functional relationship and the obtained word number of the disassembled memory area and the obtained number of bits in a single word includes: determining the actual soft error rate of the storage area subjected to k-level disassembly as follows:
Figure GDA0001971206780000032
or
Figure GDA0001971206780000033
Wherein R issystem,kFor the actual soft error rate, T, of the storage area after k-level disassemblyscrubIs the refresh period of the ECC memory, RrawFor the original soft error rate of the storage area of the ECC memory when the ECC function is closed, Nw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,k＝Nw，0·2k，Nw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nb,k＝Nd,k+Nc,k，Nd,kFor the data bits after k-level disassembly, Nc,kPerforming k-level disassembly for the check bits after k-level disassemblyThe latter data bit Nd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000041
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In one embodiment, check bit N after k-level disassemblyc,kIs set to satisfy
Figure GDA0001971206780000042
Is the smallest integer of (a).
In one embodiment, the determined level of disassembly k is 1 or 2.
According to another aspect of the present invention, there is provided an apparatus for reducing an actual soft error rate of a storage area of an ECC memory, the apparatus comprising: the functional relation acquisition module is used for acquiring the functional relation of the actual soft error rate of the storage area of the ECC memory; a disassembly level determining module, configured to determine a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship, where k is an integer greater than or equal to 1; the parameter determining module after disassembly determines the word number of a storage area and the number of bits in a single word after k-level disassembly of a storage framework of the ECC memory according to the disassembly level k; and the soft error rate determining module is used for determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained digit number in the single word.
According to a further aspect of the invention, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the method described in any of the embodiments above.
The method, the device and the computer readable storage medium for reducing the actual soft error rate of the storage area of the ECC memory are characterized in that firstly, the functional relation of the actual soft error rate of the storage area of the ECC memory is obtained, the disassembly level k for disassembling the storage architecture of the ECC memory is determined according to the functional relation, the word number of the storage area and the number of bits in a single word after the k-level disassembly of the storage architecture of the ECC memory are determined according to the disassembly level k, and the actual soft error rate of the disassembled storage area is determined.
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Preferred, but non-limiting, embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which:
FIG. 1 is a flow chart of a method for reducing an actual soft error rate of a storage area of an ECC memory in one embodiment of the present application;
FIG. 2 is a diagram of an apparatus for reducing an actual soft error rate of a storage area of an ECC memory according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The present application provides a method for reducing the actual soft error rate of a storage area of an ECC memory, as shown in fig. 1, the method comprising the steps of:
step S100, acquiring the functional relation of the actual soft error rate of the storage area of the ECC memory.
In particular, the ECC memory refers to a memory having an ECC function. The actual soft error rate of the storage area of the ECC memory is the soft error rate of the storage area of the ECC memory when the ECC function is started. In order to reduce the actual soft error rate of the storage area of the ECC memory, the functional relationship thereof needs to be obtained first to know the relationship between the soft error rate and various factors.
And S200, determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation.
Specifically, k is an integer of 1 or more. The disassembly is implemented in hardware. Specifically, when the circuit design of the ECC memory is performed, the number of words N in the memory areawAnd data bit N within a single worddThe data bit N in a word of the memory is set on the premise that the product (i.e., the effective storage capacity) of (A) is not changeddThe original 64-bit memory is changed to 32-bit memory in hardware circuit design, for example, by multiple times.
And step S300, determining the number of words and the number of bits in a single word of the storage area after k-level disassembly is performed on the storage architecture of the ECC memory according to the disassembly level k.
Specifically, after k-level disassembly is performed on the storage architecture of the ECC memory, both the number of words in the storage area of the ECC memory and the number of bits in a single word change, and in order to determine the soft error rate after disassembly, the number of words in the storage area and the number of bits in a single word after k-level disassembly is performed on the storage architecture of the ECC memory need to be determined according to the disassembly level k.
And step S400, determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained digit number in a single word.
Specifically, after the disassembly level k to be disassembled is determined, the actual soft error rate of the memory area of the ECC memory after the k-level disassembly needs to be determined according to the functional relationship and the obtained word number of the disassembled memory area and the number of bits in a single word.
The method for reducing the actual soft error rate of the storage area of the ECC memory comprises the steps of firstly obtaining the functional relation of the actual soft error rate of the storage area of the ECC memory, determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, determining the word number of the storage area and the digit number in a single word after the k-level disassembly of the storage architecture of the ECC memory according to the disassembly level k, and determining the actual soft error rate of the disassembled storage area.
In one embodiment, obtaining a functional relationship of actual soft error rates of a storage area of an ECC memory comprises: a mathematically derived functional relationship between the actual soft error rate of a storage region of an ECC memory and the number of words in the storage region and the number of bits in a single word is obtained.
Specifically, the actual soft error rate of the memory area of the ECC memory and the word number N of the memory area can be determined by a mathematical derivation methodwAnd a data bit N within a single worddFunctional relationship between them. In other embodiments, the actual soft error rate of the memory area and the word number N of the memory area of the ECC memory obtained by an experimental way can be obtainedwAnd a data bit N within a single worddFunctional relationship between them.
In one embodiment, determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship includes: and determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, the preset target soft error rate and the system parameters.
In particular, the system parameters include bandwidth, operating frequency, and power consumption of the system to which the ECC memory is applied. On one hand, the words in the storage area of the ECC memory are disassembled into a plurality of words, and each word is respectively subjected to ECC protection, so that the soft error rate of the storage area of the ECC memory can be effectively reduced; on the other hand, the increasing of the disassembly level can increase the complexity of the ECC encoding and decoding circuit, and the effect of reducing the soft error rate is gradually weakened along with the deepening of the disassembly degree. Therefore, when determining the disassembly level k, not only the preset target soft error rate but also the limitation of the system parameter on the disassembly level need to be considered, and the disassembly level k for disassembling the storage architecture of the ECC memory needs to be determined according to the functional relationship, the preset target soft error rate and the system parameter.
In one embodiment, the ECC is a hamming code with a function of correcting one error and two errors, and the function relationship of the obtained actual soft error rate of the storage area of the ECC memory is as follows:
Figure GDA0001971206780000081
or
Figure GDA0001971206780000082
Wherein R issystemFor the actual soft error rate, T, of the storage area of the ECC memory when the ECC function is turned onscrubIs the refresh period of the ECC memory, NwNumber of words, N, being a storage area of an ECC memorybRefers to the number of bits in a single word, RrawThe original soft error rate of the ECC memory in the storage area when the ECC function is closed.
Specifically, the ECC is a simple hamming code with a function of correcting one error and detecting two errors. From the above formula, the actual soft error rate R of the storage areasystemAnd the number of words N in the memory areawAnd the number of bits N in a single wordbIs positively correlated with the square of, or with the number of words N in the memory areawAnd the number of bits N in a single wordb·(Nb-1) positive correlation. In other embodiments, the ECC is other types of error correcting codes, the optimization principle is the same as that of the simple hamming code embodiment, and the simple hamming code accounts for more than 90% of the practical application, and thus is not described again.
In one embodiment, the ECC is a simple Hamming code with one-to-two correction. Determining the number of words and the number of bits in a single word of a storage area after k-level disassembly of the storage architecture of the ECC memory according to the disassembly level k, wherein the number of words and the number of bits in a single word of the storage area after k-level disassembly of the storage architecture of the ECC memory are determined according to the following formulas respectively:
Nw,k＝Nw，0·2k，
Nb,k＝Nd,k+Nc,k，
wherein N isw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits N after k-level disassemblyd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000091
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In one embodiment, determining the actual soft error rate of the storage area of the ECC memory after performing k-level disassembly includes: determining the actual soft error rate of the storage area subjected to k-level disassembly as follows:
Figure GDA0001971206780000092
or
Figure GDA0001971206780000093
Wherein R issystem,kFor the actual soft error rate, N, of the storage area after k-level disassemblyw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,k＝Nw，0·2k，Nw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs a bit within a single word in the memory area after k-level disassemblyNumber, Nb,k＝Nd,k+Nc,k，Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits N after k-level disassemblyd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000094
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In particular, in the above embodiments, it can be seen that the disassembly is performed on data bits in a single word, and the total number of bits in the single word is equal to the sum of the data bits and the check bits. The product of the number of words in the disassembled storage area and the disassembled data bits is equal to the product of the original number of words in the storage area and the original data bits, so that the effective storage space is unchanged.
In one embodiment, check bits N after k-level disassembly are performedc,kIs set to satisfy
Figure GDA0001971206780000095
Is the smallest integer of (a).
In particular, to save the total number of bits within a single word, the check bit N is usedc,kIs set to satisfy
Figure GDA0001971206780000101
Is the smallest integer of (a). For example, when the data bits are 64 bits, the check bits are 8 bits; when the data bits are 32 bits, the check bits are 7 bits; when the data bits are 16 bits, the check bits are 6 bits; when the data bit is 8 bits, the check bit is 5 bits; when the data bits are 4 bits, the check bits are 4 bits.
The most common memory architecture (72,64) of ECC memory is used as an example to compare the soft error rate after defragmentation with the soft error rate before defragmentation. For the storage architecture (72,64), where Nb＝72，Nd＝64，Nc8. Soft error rate without disassembly and soft error rates after first, second, third and fourth level disassembly, e.g.The following table shows:
Figure GDA0001971206780000102
as can be seen from the above table, the more the number of the defragmentation is, the more the soft error rate is reduced, and the more slowly the error rate is reduced as the defragmentation level is increased. In addition, when determining the level of disassembly, the preset target soft error rate and parameters of the system to which the ECC memory is applied, including bandwidth, operating frequency, power consumption, etc., need to be considered.
In one embodiment, the determined level of disassembly k is typically 1 or 2. Specifically, generally, one or two levels are generally split, i.e., k is determined to be 1 or 2, by comprehensively considering a preset target soft error rate, and the bandwidth, operating frequency, power consumption, etc. of the system. In this way, with appropriate disassembly, the desired reduction in soft error rate can be achieved without significantly increasing the complexity of the ECC encoding and decoding circuitry.
The present application also provides an apparatus for reducing the actual soft error rate of a storage area of an ECC memory, as shown in fig. 2, the apparatus includes the following modules:
a functional relationship obtaining module 100, configured to obtain a functional relationship of an actual soft error rate of a storage area of the ECC memory;
a disassembly level determining module 200, configured to determine a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship, where k is an integer greater than or equal to 1;
the disassembled parameter determining module 300 determines the number of words and the number of bits in a single word of the storage area after k-level disassembly of the storage architecture of the ECC memory according to the disassembly level k;
and a soft error rate determining module 400, configured to determine, according to the functional relationship and the obtained word number of the disassembled storage area and the obtained number of bits in a single word, an actual soft error rate of the storage area of the ECC memory after k-level disassembly.
The device for reducing the actual soft error rate of the storage area of the ECC memory comprises the steps of firstly obtaining the functional relation of the actual soft error rate of the storage area of the ECC memory, determining the disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, determining the word number of the storage area and the digit number in a single word after the k-level disassembly of the storage architecture of the ECC memory according to the disassembly level k, and determining the actual soft error rate of the disassembled storage area.
In an embodiment, the functional relationship obtaining module 100 is specifically configured to: a mathematically derived functional relationship between the actual soft error rate of a storage region of an ECC memory and the number of words in the storage region and the number of bits in a single word is obtained.
In one embodiment, the disassembly level determination module 200 is specifically configured to: and determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, a preset target soft error rate and system parameters, wherein the system parameters comprise the bandwidth, the working frequency and the power consumption of a system applying the ECC memory.
In one embodiment, the ECC is a hamming code with a function of correcting one error and two errors, and the function relationship of the obtained actual soft error rate of the storage area of the ECC memory is as follows:
Figure GDA0001971206780000121
or
Figure GDA0001971206780000122
Wherein R issystemFor the actual soft error rate, T, of the storage area of the ECC memory when the ECC function is turned onscrubIs the refresh period of the ECC memory, NwNumber of words, N, being a storage area of an ECC memorybRefers to the number of bits in a single word, RrawThe original soft error rate of the ECC memory in the storage area when the ECC function is closed.
In one embodiment, the disassembled parameter determining module 300 is specifically configured to determine the number of words and the number of bits in a single word of the storage area after performing k-level disassembly on the storage architecture of the ECC memory according to the following formulas:
Nw,k＝Nw，0·2k，
Nb,k＝Nd,k+Nc,k，
wherein N isw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits N after k-level disassemblyd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000123
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In one embodiment, the soft error rate determining module 400 is specifically configured to determine the actual soft error rate of the storage area after k-level disassembly according to the following formula:
Figure GDA0001971206780000124
or
Figure GDA0001971206780000131
Wherein R issystem,kFor the actual soft error rate, T, of the storage area after k-level disassemblyscrubIs the refresh period of the ECC memory, RrawFor the original soft error rate of the storage area of the ECC memory when the ECC function is closed, Nw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,k＝Nw，0·2k，Nw,0Of zones of ECC memory not subject to disassemblyNumber of original words, Nb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nb,k＝Nd,k+Nc,k，Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits N after k-level disassemblyd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000132
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In one embodiment, check bits N after k-level disassembly are performedc,kIs set to satisfy
Figure GDA0001971206780000133
Is the smallest integer of (a).
In one embodiment, the determined level of disassembly k is typically 1 or 2.
The present application also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of: acquiring a functional relation of the actual soft error rate of a storage area of an ECC memory; determining a disassembly level k for disassembling a storage architecture of the ECC memory according to the functional relationship, wherein k is an integer greater than or equal to 1; determining the number of words and the number of bits in a single word of a storage area after k-level disassembly is performed on a storage architecture of the ECC storage according to the disassembly level k; and determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained number of bits in a single word.
In one embodiment, obtaining a functional relationship of actual soft error rates of a storage area of an ECC memory comprises: a mathematically derived functional relationship between the actual soft error rate of a storage region of an ECC memory and the number of words in the storage region and the number of bits in a single word is obtained.
In one embodiment, determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship includes: and determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, a preset target soft error rate and system parameters, wherein the system parameters comprise the bandwidth, the working frequency and the power consumption of a system applying the ECC memory.
In one embodiment, the ECC is a hamming code with a function of correcting one error and two errors, and the function relationship of the obtained actual soft error rate of the storage area of the ECC memory is as follows:
Figure GDA0001971206780000141
or
Figure GDA0001971206780000142
Wherein R issystemFor the actual soft error rate, T, of the storage area of the ECC memory when the ECC function is turned onscrubIs the refresh period of the ECC memory, NwNumber of words, N, being a storage area of an ECC memorybRefers to the number of bits in a single word, RrawThe original soft error rate of the ECC memory in the storage area when the ECC function is closed.
In one embodiment, determining the number of words and the number of bits in a single word of the memory area after the k-level defragmentation of the memory architecture of the ECC memory according to the defragmentation level k includes determining the number of words and the number of bits in a single word of the memory area after the k-level defragmentation of the memory architecture of the ECC memory according to the following formulas, respectively:
Nw,k＝Nw，0·2k，
Nb,k＝Nd,k+Nc,k，
wherein N isw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits after k-level disassemblyNd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000143
Wherein N isd,k＝Nd,0/2k，Nd,0Are the original data bits of the storage area of the ECC memory that have not been disassembled.
In one embodiment, determining the actual soft error rate of the memory area of the ECC memory after performing k-level disassembly according to the functional relationship and the obtained word number of the disassembled memory area and the obtained number of bits in a single word includes: determining the actual soft error rate of the storage area subjected to k-level disassembly as follows:
Figure GDA0001971206780000151
or
Figure GDA0001971206780000152
Wherein R issystem,kFor the actual soft error rate, T, of the storage area after k-level disassemblyscrubIs the refresh period of the ECC memory, RrawFor the original soft error rate of the storage area of the ECC memory when the ECC function is closed, Nw,kIs the number of words, N, of the storage area of the ECC memory after k-level disassemblyw,k＝Nw，0·2k，Nw,0Is the original number of words, N, of the memory area of the ECC memory without disassemblyb,kIs the number of bits within a single word in the memory area after k-level disassembly, Nb,k＝Nd,k+Nc,k，Nd,kFor the data bits after k-level disassembly, Nc,kFor the check bits after k-level disassembly, the data bits N after k-level disassemblyd,kAnd check bit N after k-level disassemblyc,kSatisfy the requirement of
Figure GDA0001971206780000154
Wherein N isd,k＝Nd,0/2k，Nd,0Is storage of ECC memory without disassemblyThe original data bits of the region.
In one embodiment, check bits N after k-level disassembly are performedc,kIs set to satisfy
Figure GDA0001971206780000153
Is the smallest integer of (a).
In one embodiment, the determined level of disassembly k is typically 1 or 2.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (9)

1. A method for reducing the actual soft error rate of a storage area of an ECC memory, the method comprising the steps of:
acquiring a functional relation of the actual soft error rate of a storage area of an ECC memory, wherein the functional relation is used for representing the incidence relation between the actual soft error rate of the storage area and other factors of the ECC memory; the obtaining of the functional relationship of the actual soft error rate of the storage area of the ECC memory includes: acquiring a functional relation between the actual soft error rate of the storage area of the ECC storage, which is obtained by mathematical derivation, and the number of words in the storage area and the number of bits in a single word;
determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship, wherein k is an integer greater than or equal to 1;
determining the number of words and the number of bits in a single word of a storage area after k-level disassembly is performed on a storage architecture of the ECC storage according to the disassembly level k;
and determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained number of bits in a single word.
2. The method of claim 1, wherein determining a disassembly level k for disassembling a storage architecture of an ECC memory according to the functional relationship comprises:
and determining a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relation, a preset target soft error rate and system parameters, wherein the system parameters comprise the bandwidth, the working frequency and the power consumption of a system applying the ECC memory.
3. The method as claimed in claim 1, wherein the ECC is a hamming code with a function of correcting one error and two errors, and the function relationship of the actual soft error rate of the storage area of the ECC memory is obtained as follows:
Figure 158806DEST_PATH_IMAGE001
or is or
Figure 319660DEST_PATH_IMAGE002
，
Wherein the content of the first and second substances,R system for the actual soft error rate of the storage area of the ECC memory when the ECC function is turned on,T scrub is the refresh period of the ECC memory,N w is the number of words of a storage area of the ECC memory,N b refers to the number of bits within a single word,R raw the original soft error rate of the ECC memory in the storage area when the ECC function is closed.
4. The method of claim 3, wherein determining the number of words and the number of bits in a single word for the storage area after the storage architecture of the ECC memory is disassembled into k levels according to the disassembly level k comprises determining the number of words and the number of bits in a single word for the storage area after the storage architecture of the ECC memory is disassembled into k levels according to the following formulas:
Figure 587830DEST_PATH_IMAGE003
，
Figure 767008DEST_PATH_IMAGE004
，
wherein the content of the first and second substances,
Figure 728011DEST_PATH_IMAGE005
is the number of words in the storage area of the ECC memory after k-level disassembly,
Figure 376161DEST_PATH_IMAGE006
is the original number of words of the storage area of the ECC memory that have not been disassembled,
Figure 182443DEST_PATH_IMAGE007
is the number of bits within a single word in the memory area after k levels of disassembly,
Figure 91493DEST_PATH_IMAGE008
to perform the k-level disassembly of the data bits,
Figure 85381DEST_PATH_IMAGE009
for the check bits after k-level disassembly, the data bits after k-level disassembly
Figure 345461DEST_PATH_IMAGE008
And check bits after k-level disassembly
Figure 565221DEST_PATH_IMAGE009
Satisfy the requirement of
Figure 594357DEST_PATH_IMAGE010
Wherein, in the step (A),
Figure 21796DEST_PATH_IMAGE011
，
Figure 238014DEST_PATH_IMAGE012
are the original data bits of the storage area of the ECC memory that have not been disassembled.
5. The method of claim 4, wherein determining the actual soft error rate of the ECC memory after performing k-level defragmentation according to the functional relationship and the obtained word count and the obtained number of bits in a single word of the defragmented memory area comprises: determining the actual soft error rate of the storage area subjected to k-level disassembly as follows:
Figure 651678DEST_PATH_IMAGE013
or is or
Figure 410686DEST_PATH_IMAGE014
，
Wherein the content of the first and second substances,
Figure 884393DEST_PATH_IMAGE015
to perform the actual soft error rate of the storage area after k-level disassembly,T scrub is the refresh period of the ECC memory,R raw for the original soft error rate of the storage area of the ECC memory when the ECC function is turned off,
Figure 712540DEST_PATH_IMAGE016
is the number of words in the storage area of the ECC memory after k-level disassembly,
Figure 664316DEST_PATH_IMAGE017
，
Figure 543410DEST_PATH_IMAGE018
is the original number of words of the storage area of the ECC memory that have not been disassembled,
Figure 188018DEST_PATH_IMAGE007
is the number of bits within a single word in the memory area after k levels of disassembly,
Figure 378828DEST_PATH_IMAGE019
，
Figure 258928DEST_PATH_IMAGE020
to perform the k-level disassembly of the data bits,
Figure 851584DEST_PATH_IMAGE009
for the check bits after k-level disassembly, the data bits after k-level disassembly
Figure 542459DEST_PATH_IMAGE020
And check bits after k-level disassembly
Figure 486144DEST_PATH_IMAGE009
Satisfy the requirement of
Figure 172865DEST_PATH_IMAGE021
Wherein, in the step (A),
Figure 620027DEST_PATH_IMAGE011
，
Figure 216225DEST_PATH_IMAGE012
are the original data bits of the storage area of the ECC memory that have not been disassembled.
6. Method according to claim 4 or 5, characterized in that said check bits after k-level disassembly
Figure 647206DEST_PATH_IMAGE009
Is set to satisfy
Figure 869109DEST_PATH_IMAGE022
Is the smallest integer of (a).
7. The method according to any of claims 1-5, characterized in that the determined un-disassembly level k is 1 or 2.
8. An apparatus for reducing an actual soft error rate of a storage region of an ECC memory, the apparatus comprising:
the functional relation obtaining module is used for obtaining the functional relation of the actual soft error rate of the storage area of the ECC memory, and the functional relation is used for representing the incidence relation between the actual soft error rate of the storage area and other factors of the ECC memory; the functional relation acquisition module is used for acquiring the functional relation between the actual soft error rate of the storage area of the ECC storage, the word number of the storage area and the number of bits in a single word, wherein the functional relation is obtained through mathematical derivation;
a disassembly level determining module, configured to determine a disassembly level k for disassembling the storage architecture of the ECC memory according to the functional relationship, where k is an integer greater than or equal to 1;
the disassembled parameter determining module is used for determining the word number of the storage area and the number of bits in a single word after k-level disassembly is carried out on the storage architecture of the ECC storage according to the disassembly level k;
and the soft error rate determining module is used for determining the actual soft error rate of the storage area of the ECC memory after k-level disassembly according to the functional relation, the obtained word number of the disassembled storage area and the obtained number of bits in a single word.
9. A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1-7.
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