TWI718060B - Memory controller and method of accessing flash memory - Google Patents

Abstract

A method of accessing a flash memory, for use in a memory controller of a data storage device, is provided. The method includes the steps of: storing data to a flash memory of the data storage device via a storage procedure; obtaining a channel value read from a flash memory of the data storage device; obtaining a codeword difference and calculating a syndrome according to the codeword difference; and in each LDPC decoding iteration, performing the following steps: determining a syndrome weight according to the channel value and the syndrome; obtaining a previous codeword generated by a previous LDPC decoding iteration; obtaining a first flipping-strategy lookup table from a plurality of flipping-strategy lookup tables according to a decoding target of the memory controller; determining a flipping strategy in the bit-flipping algorithm for each codeword bit in the previous codeword according to the syndrome weight, a predetermined threshold, and the first flip-strategy lookup table and flipping one or more codeword bits in the previous codeword according to the determined flipping strategy for each codeword bit to generate an updated codeword; and subtracting the previous codeword from the updated codeword to generate the codeword difference.

Description

Memory controller and flash memory access method

The present invention relates to data access, and particularly relates to a memory controller and flash memory access method.

With the advancement of semiconductor technology, low-density parity check (LDPC) codes have been implemented with very-large-scale integration (VLSI) circuits in recent years and are widely used in digital The field of communication (for example, including wireless communication and optical fiber communication) and the field of data transmission (for example, for data storage devices, such as solid state drives) are used as error correction codes (ECC).

The low-density parity checking decoder uses a linear error correction code with parity bits for decoding, where the parity bit provides a parity equation for verifying the received codeword to the LDPC decoder. For example, the low-density parity check code can be a binary code with a fixed length, in which all symbols add up to zero.

In the process of data encoding, all data bits are repeatedly executed and sent to the corresponding encoder, where each encoder generates a parity symbol. The codeword is composed of k information digits and r check digits. If the code word has n bits in total, it means k=n-r. The above codeword can be represented by a parity check matrix, where the parity check matrix has r columns (representing the number of equations) and n rows (representing the number of bits), as shown in FIG. 1. These codes are called "low density" because the number of bit 1 is relatively small compared to the number of bit 0 in the parity check matrix. During the decoding process, each parity check can be regarded as a parity check code, and then cross-check with other parity check codes. The decoding will be performed at the check node. The interactive inspection will be carried out at the variable node.

The low-density parity check decoder supports three modes: hard decision hard decoding, soft decision soft decoding, and soft decision hard decoding. Figure 1A is a schematic diagram of the parity check matrix H. Figure 1B is a schematic diagram of the Tanner Graph. As shown in FIG. 1A, each column of the parity check matrix H can form a check node, for example, check nodes C1, C2, C3, and C4, respectively. Each row of the parity check matrix H can form a variable node, such as variable nodes V1, V2, V3, V4, V5, V6, and V7.

The Tanner diagram is another way of representing codewords, and it can be used to explain some of the hard decision soft decoding operations of the low-density parity check decoder when a bit flipping algorithm is used.

As shown in Figure 1B, in the Tanner diagram, the check nodes represented by square nodes C1~C4 represent the number of parity bits, and the variable nodes represented by circular nodes V1~V7 are Is the number of bits in a codeword. If a specific equation is related to a code symbol, the corresponding check node and variable node will be represented by a line. The estimated information will be passed along these connections and combined in different ways on the nodes.

When the LDPC decoding is started, the variable node will send an estimate to the check nodes on all connections, where these connections contain bits that are considered correct. Then, each check node will perform a new estimate for each variable node based on the connected estimate of all other connections, and send the new estimate information back to the variable node. The new estimation system is based on: the parity check equation forces all variable nodes to be connected to a specific check node so that the sum is zero.

These variable nodes will receive new estimation information and use a majority rule (ie, hard decision) to determine whether the value of the original bit transmitted is correct. If it is judged that the value of the original bit is incorrect, the original bit will be flipped. The flipped bits are then transmitted back to the check nodes, and the above steps are performed iteratively for a predetermined number of times until the parity check equations of these check nodes are met. If these parity check equations are met (that is, the value calculated by the check node matches the value received from the variable node), early termination can be enabled, which will cause the system to end the decoding process before the maximum number of iterations is reached .

These parity check restrictions are implemented by performing a syndrome check. A valid codeword will conform to the equation: H. C ^T =S=0, where H is a parity check matrix, C is a hard decision codeword, and S is a syndrome. When S is equal to zero, it means that the decoding process has been completed and no further information is needed. Generally speaking, the hard decision and symptom check will be performed during the iteration, where a non-zero symptom indicates the existence of odd parity, and a new decoding iteration is required.

Traditional bit-flipping LDPC decoders often limit the data transfer of each codeword bit to one bit for performance and low power consumption considerations. That is, in each iteration process, each codeword bit only exchanges sign bit information. Under this limitation, it is very difficult to increase the decoding performance of the decoder, such as throughput or correction rate.

Therefore, the present invention proposes a memory controller and a flash memory access method, which enables variable node units in a low-density parity check decoder to execute configurable decoding strategies and increase decoding Performance, increase the correction rate, and/or reduce power consumption.

The present invention provides a memory controller used in a data storage device. The memory controller includes a variable node unit and a check node unit. The variable node unit is used to obtain a channel value read from a flash memory of the data storage device. The check node unit is used to obtain a codeword difference from the variable node unit, and calculate a syndrome according to the codeword difference. During each iteration of LDPC decoding, the variable node unit executes: Determine a syndrome weight based on the channel value and the symptom value from the check node unit; obtain a previous LDPC decoding iteration A previous codeword generated; obtain a first flip strategy lookup table from a plurality of flip strategy lookup tables according to a decoding target of the memory controller; look up based on the symptom weight, a predetermined threshold and the first flip strategy The table is used to determine a flip strategy of the bit-flipping algorithm of each codeword bit of the previous codeword, and flip one or more codeword bits in the previous codeword according to the flipping strategy Yuan to generate an updated codeword; and subtract the updated codeword from the previous codeword to generate the codeword difference.

In some embodiments, the flip order used in the flip strategy lookup tables includes a first flip order, a second flip order, and a third flip order, and the LDPC iterations used in the flip strategy lookup tables The number of times includes a first number of iterations, a second number of iterations, and a third number of iterations, wherein the first flip order is greater than the second flip order, and the second flip order is greater than the third flip order, Wherein the first iteration number is greater than the second iteration number, and the second iteration number is greater than the third iteration number.

In some embodiments, when the decoding goal is to improve throughput, the first flipping strategy look-up table uses the first flipping order and the third iteration number. In other embodiments, when the decoding goal is to increase the correction rate, the first flipping strategy look-up table uses the second flipping order and the first iteration number. In still other embodiments, when the decoding goal is to reduce power consumption, the first flip strategy look-up table uses the third flip order and the third iteration number.

The present invention further provides a flash memory access method, which is applied to a memory controller in a data storage device. The method includes the following steps: storing data to a flash memory of the data storage device through a storage program Memory; obtain a channel value read from a flash memory of the data storage device; obtain a codeword difference value from the variable node unit, and calculate a syndrome value (syndrome) based on the codeword difference value ; And during each iteration of LDPC decoding, perform the following steps: determine a symptom weight (syndrome weight) according to the channel value and the symptom value from the check node unit; obtain a previous LDPC decoding iteration A previous codeword generated; obtain a first flip strategy lookup table from a plurality of flip strategy lookup tables according to a decoding target of the memory controller; look up based on the symptom weight, a predetermined threshold and the first flip strategy The table is used to determine a flip strategy of the bit-flipping algorithm of each codeword bit of the previous codeword, and flip one or more codeword bits in the previous codeword according to the flipping strategy Yuan to generate an updated codeword; and subtract the updated codeword from the previous codeword to generate the codeword difference.

The present invention further provides a memory controller used in a data storage device. The memory controller includes: a variable node unit and a check node unit. The variable node unit is used to obtain a channel value read from a flash memory of the data storage device. The check node unit is used to obtain a codeword difference from the variable node unit, and calculate a syndrome according to the codeword difference. During each iteration of LDPC decoding, the variable node unit executes: Determine a syndrome weight based on the symptom value from the check node unit; obtain a syndrome weight generated by a previous LDPC decoding iteration The previous codeword; according to the channel value and the previous codeword to determine whether each codeword bit in the previous codeword has been flipped; for the previous codeword, each codeword bit has been flipped and not After each codeword bit has been flipped, a first flip strategy lookup table and a second flip strategy lookup table are respectively selected, wherein the first flip strategy lookup table is different from the second flip strategy lookup table; according to the symptom weight , A predetermined threshold and the selected first flipping strategy lookup table or the second flipping strategy lookup table to determine one of the bit-flipping algorithms of each codeword bit of the previous codeword Strategy, and flip one or more codeword bits in the previous codeword according to the flipping strategy to generate an updated codeword; and subtract the previous codeword from the updated codeword to generate the codeword difference.

The following description is a preferred implementation of the invention, and its purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "include", "include" and other words used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements, and/or components, but they do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" used in the claims are used to modify the elements in the claims, and are not used to indicate that there is an order of priority, an antecedent relationship, or an element Prior to another element, or the chronological order of execution of method steps, is only used to distinguish elements with the same name.

FIG. 2 is a block diagram of a data storage device according to an embodiment of the invention.

In one embodiment, the data storage device 200 may be a portable memory device (for example, a memory card compliant with SD/MMC, CF, MS, and XD standards) or a solid-state drive (SSD), and The host 230 is an electronic device that can be connected to the data storage device 200, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the data storage device 200 may be installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the main device 130 may be a processor of the electronic device. .

As shown in FIG. 2, the data storage device 200 includes a memory controller 210 and a flash memory 220. The memory controller 210 is used to access the flash memory 220. In one embodiment, the memory controller 210 includes a processing unit 211, a storage unit 212, a control logic 216, a buffer memory 218, and access interfaces 250 and 252. The processing unit 211 may be implemented by a dedicated hardware circuit or a general-purpose hardware, a processor with multiple processing cores or a multiprocessor with parallel processing capabilities, and the foregoing implementation manner may be, for example, a General-Purpose Processor. , Or Microcontroller, but the present invention is not limited to this.

The storage unit 212 may be a non-volatile memory, such as read-only memory (read-only memory, ROM), erasable programmable read-only memory (erasable programmable read-only memory, EPROM), electronic memory Erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM) or electronic fuse (E-Fuse). The storage unit 212 stores a startup program 213, which includes a startup code (Boot Code) or a startup program (Bootloader), and can be executed by the processing unit 211. The memory controller 210 completes the boot based on the startup program 213 and starts to control the flash The operation of the memory 220, for example, reads In System Programming (ISP) codes.

The flash memory 220 is, for example, a NAND flash memory, and the flash memory 220 includes a plurality of physical blocks 240 and each physical block includes a plurality of physical pages 241.

The transmission of data and operation commands between the processing unit 211 and the flash memory 220 is coordinated through a number of electronic signals. The electronic signals include a data line, a clock signal, and a control signal. . The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE).

The access interface 250 can communicate with the flash memory 220 using a double data rate (DDR) communication protocol, for example, open NAND flash interface (ONFI), double data rate switch (DDR Toggle) ) Or other interfaces. The processing unit 211 can also use the access interface 252 to communicate with the host 230 through a designated communication protocol, such as universal serial bus (USB), advanced technology attachment (ATA), serial advanced technology attachment ( Serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E), non-volatile memory transfer specification (Non-Volatile Memory Express, NVMe) or other interfaces.

The buffer memory 218 may be a volatile memory, for example, including a dynamic random access memory (DRAM) and/or a static random access memory (SRAM). In this embodiment, the buffer memory 218 includes a channel value memory (CHVMem) 2181 and a variable node memory (VNMem) 2182. The channel value memory 2181 is used to temporarily store original page data (or codewords) from the flash memory 220 read by the access interface 250 or to temporarily store host commands from the host 230. The variable node memory 2182 is used to temporarily store the variable node data of each variable node during the decoding process of the low-density parity check. In addition, the code words stored in the channel value memory 2181 can be, for example, information read by the flash memory 220 in a hard decision or a soft decision. The hard decision uses a single read voltage threshold, so The obtained codeword has only sign information. Soft decision (soft decision) uses multiple read voltage thresholds, so in addition to symbol information, the obtained codeword also contains reliability information. For example, each codeword bit can use at least one bit of reliability. Degree information. If the reliability information is represented by one bit, 0 and 1 can be used to represent two different reliability levels, namely strong and weak respectively. The code word bit collocation reliability can be divided into strong "1", Weak "1", weak "0" and strong "0".

The control logic 216 includes an encoder 214 and a decoder 215. In some embodiments, the encoder 214, the decoder 215, and the control logic 216 can be, for example, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). , A complex programmable logic device (CPLD), or a logic circuit with the same function, but the invention is not limited to this.

In this embodiment, the encoder 214 is, for example, a low-density parity check code (LDPC) encoder, and can generate a corresponding check code based on the data from the host 230, and the generated check code conforms to a check code check matrix. Specifically, referring to Figure 3, suppose the check code check matrix is a matrix of size c*t (for example, the number of columns c=5, the number of rows t=48), and the check code check matrix can be divided into the left The matrix M (size c*(tc)) and the right matrix K (size c*c), in order to find the check code generation matrix corresponding to the check code check matrix, you can first find the inverse of the matrix K Matrix K ^-1 (inverse matrix), and then multiply the inverse matrix (K ^-1 ) with matrix M to obtain matrix P, and the transpose matrix of matrix P can be used as a check code to generate a matrix. In other words, after finding the transposed matrix of matrix P, the encoder 214 can multiply the data from the host 230 by the transposed matrix of matrix P to obtain the check code corresponding to the data, and the encoder 214 can then The data and the check code are multiplied by the check matrix to determine whether the check code is correct. For example, if the multiplication result is equal to "0", it is judged that the encoding is correct; if the multiplication result is not equal to "0", it is judged that the encoding is wrong. After the code is judged to be correct, the data and the corresponding check code will be written into one of the physical pages of the flash memory 220.

The decoder 215 is, for example, a low-density parity check code (LDPC) decoder. When the host 230 sends a read command to the data storage device 230, the memory controller 210 obtains the initial page data from the flash memory 220, which is also called channel value, for example. The initial page data includes, for example, initial data and error correction code data. Because the initial data and the error correction code data may generate errors when transmitted through the channel, the decoder 215 can use the error correction code data to perform error correction on the initial data and/or the error correction code data itself, for example, a bit reversal can be used. (bit flipping) algorithm for LDPC decoding. The details of the decoder 215 will be detailed in the following embodiments.

Figure 4 is a block diagram of the decoder 215 in an embodiment according to the present invention. As shown in FIG. 4, the decoder 215 includes a variable node unit (VNU) 410 and a check node unit (CNU) 420. During LDPC decoding, the data will be iterated between the variable node unit 410 and the check node unit 420 until the correct codeword is solved or the number of iterations is reached. For example, when the decoder 215 starts decoding, the value of the previous codeword and the initial symptom value temporarily stored in the variable node memory 2182 are reset to zero. The variable node unit 410 obtains the channel value or code word (for example, it may be called the previous code word VN_prev) from the channel value memory 2181, and performs the first iteration operation. The variable node unit 410 stores the updated codeword (VN_new) generated by the iterative operation to the variable node memory 2182, and transmits the difference between the updated codeword and the previous codeword (VN_prev) to the inspection The node unit 420 is used to perform correlation calculations on syndrome values.

If the symptom value from the check node unit 420 is not 0, the variable node unit 410 will continue to perform the second or subsequent iteration operations. For example, the variable node unit 410 obtains the previous code word VN_prev, the symptom value, and the channel value from the variable node memory 2182, the check node unit 420, and the channel value memory 2181, respectively, and calculates the previous code word Those codeword bits in need to be reversed. If the symptom value from the check node unit 420 is equal to 0, the variable node unit 410 will output the updated code word generated by the current iteration process to output the correct page data. Therefore, the processing unit 211 in the memory controller 210 can report the correct page data to the host 230.

Figure 5 is a block diagram of the variable node unit in the first embodiment of the present invention. Please refer to FIG. 4 and FIG. 5 at the same time. In the first embodiment, the variable node unit 410 includes, for example, a syndrome weight sum unit 511, a threshold calculator 512, and a flip Unit (flipping unit) 513.

The symptom weight summation unit 511 is used to generate the symptom weight ws corresponding to each codeword bit according to the symptom value syndrome generated by the check node unit 420 and the channel value CH_sgn from the channel value memory 2181.

The threshold calculation unit 512 is used to calculate a threshold used in the current decoding process. In this embodiment, the threshold value generated by the threshold value calculation unit 512 for the decoding process may be changed depending on the actual decoding situation, for example.

The flip unit 513 includes a comparator 5131 and a bit flip circuit 5132. The comparator 5131 is used to compare the symptom weight ws of each codeword bit with the aforementioned threshold. The bit flip circuit 5132 determines whether the corresponding code word bit needs to be flipped according to the above comparison result, and stores the updated code word VN_new after bit flipping to the variable node memory 2182. For example, if the symptom weight ws of one of the codeword bits is greater than or equal to the above threshold th, the bit flip circuit 5132 will flip the above codeword bits, such as flipping from 0 to 1 or from 1 Is 0. The bit flip circuit 5132 calculates the codeword difference Diff between the previous codeword obtained in this iterative operation and the updated codeword, and transmits the codeword difference Diff to the check node unit 420.

Wherein, the calculation method of the codeword difference Diff is, for example, VN_next-VN_prev. The updated codeword and the previous codeword are both binary digital representations. If the updated codeword VN_next is 0111 and the previous codeword VN_prev is 0101, the codeword difference Diff is 0010.

FIG. 6A is a block diagram of the variable node unit in the second embodiment of the present invention. Please refer to FIG. 4 and FIG. 6A at the same time. In the second embodiment, the variable node unit 410 includes, for example, a syndrome weight sum unit 611, a threshold calculator 612, and a flip Unit (flip unit) 613. The symptom weight summation unit 611 is used to generate the symptom weight ws corresponding to each codeword bit according to the symptom value syndrome generated by the check node unit 420 and the channel value CH_sgn from the channel value memory 2181. The threshold calculation unit 612 is used to calculate a threshold used in the current decoding process. In this embodiment, the threshold value generated by the threshold value calculation unit 612 for the decoding process is, for example, a fixed value.

The flip unit 613 includes a flip determination unit 6131 and a bit flip circuit 6132. The flipping determination unit 6131 is used for determining a flipping strategy according to the current symptom weight ws of each codeword bit and the above threshold. For ease of description, the rollover determination unit 6131 can be implemented by, for example, a rollover strategy lookup table 601. The rollover strategy lookup table 601 can be pre-stored in the storage unit 212, and when the data storage device 200 is turned on, the processing unit 211 can search for the rollover strategy. The table 601 is loaded into the buffer memory 218 or a register file.

In one embodiment, the flip strategy look-up table 601 can be searched using hard information and codewords or soft information and codewords. For example, for normal flash memory, the error rate is about 1% or less, which means that the accuracy of the data is very high, so it is suitable to use a hard decision to read the page data. If hard decision is used when reading the page data of the flash memory 220, it means that the channel value/codeword stored in the channel value memory 2181 does not carry reliability information. At this time, the inversion unit 613 can reset the reliability information (for example, it can be represented by 1 or more bits) corresponding to each codeword bit from the channel value memory 2181 to 1 when starting LDPC decoding, for example. With the iterative calculations in the decoding process, if the reliability information is 1 bit, the value of each codeword bit and the corresponding reliability information may be switched to different values, such as strong "1" and weak "1", weak "0" and strong "0", where strong/weak means reliability information, and the corresponding (reliability, codeword bits) of the above four combinations can be expressed as (1, 1), ( 0, 1), (0, 0) and (1, 0), or can be represented as S1, W1, W0, and S0, respectively.

In another embodiment, the variable node unit in Figure 6 can also receive page data read by using soft decision (soft decision, for example, using multiple read voltage thresholds to read flash memory), and it can also receive data from the channel. The codeword of the value memory 2181 will carry soft information, for example, one or more bits of reliability information. At this time, the reversing unit 613 may directly use the respective codeword bits and the corresponding reliability information from the channel value memory 2181 when starting LDPC decoding, for example.

In this embodiment, the look-up result of the flip strategy look-up table 601 using the symptom weight ws and the threshold th can be divided into a variety of different bit flip methods, such as strong flip, weak flip and Do nothing, where the symptom weight ws and the threshold th are, for example, natural numbers. However, the present invention is not limited to this.

For example, strong flip, weak flip and no action can be represented by S, W, and X, respectively. If the result of the look-up table is expressed as a strong flip S, the strong "0" will be flipped to a weak "1", a weak "0" will be flipped to a strong "1", and a weak "1" will be flipped to a strong "0" , Strong "1" will be flipped to weak "0". If the result of the look-up table is expressed as a weak flip S, the strong "0" will be flipped to a weak "0", a weak "0" will be flipped to a weak "1", and a weak "1" will be flipped to a weak "0" , The strong "1" will be flipped to the weak "1". If the result of the look-up table is indicated as inactive, the strong "1", weak "1", weak "0" and strong "0" will all maintain their original values.

The reversal methods of strong flip, weak flip and no action are organized as shown in Table 1: Strong flip Weak flip No action S0 → W1 S0 → W0 S0 → S0 W0 → S1 W0 → W1 W0 → W0 W1 → S0 W1 → W0 W1 → W1 S1 → W0 S1 → W1 S1 → S1 Table 1

It should be noted that the present invention is not limited to the turning methods and numbers in Table 1, and those with ordinary knowledge in the field of the present invention can design suitable turning methods and numbers according to actual conditions. It is worth noting that if S1, W1, W0, and S0 are regarded as 4 logic states arranged in sequence, and the adjacent logic states can be regarded as the order difference 1, as shown in Fig. 6B. The method of strong flip means that the above state will be flipped to a state two steps or more away when flipped, for example, state S1 is flipped to state W0, state S0 is flipped to state W1, and so on. The method of weak flip refers to the state where the above state will be flipped at an interval when flipped, for example, state S1 is flipped to state W1, state S0 is flipped to state W0, and so on. However, regardless of whether it is a strong or weak reversal, the states S1, W1, W0, and S0 will have symmetry during reversal, as shown in Table 1.

In one embodiment, if the symptom weight ws and the threshold th are both integers ranging from 0 to 4, the rollover strategy look-up table 601 may, for example, use Table 2 to indicate the rollover strategies corresponding to different symptom weights ws and threshold th: th ws 0 1 2 3 4 0 X X W W W 1 X X X W W 2 X X X W W 3 X X X W S 4 X X X X S Table 2

For example, in the rollover strategy look-up table 601, for example, it can be designed to improve throughput. When the value of the symptom weight ws and the threshold th is larger, it means that the error probability in the code word bit is higher, so the strong flip method is used.

In some embodiments, the flip decision unit 6131 may include a plurality of flip strategy lookup tables, and different flip strategy lookup tables correspond to different decoding targets and can be optimized for design, such as increasing throughput and improving Correction rate, or reduce power consumption, etc. When the decoder 215 is set as one of the decoding targets, the flip decision unit 6131 can select the flip strategy lookup table corresponding to the decoding target from the above multiple flip strategy lookup tables.

For example, a look-up table for a flip strategy for improving throughput can use an overall more aggressive flip strategy with a smaller number of iterations. When the decoder 215 is under the same hardware parallelism, selecting a look-up table of the flip strategy to improve throughput can, for example, double the throughput of hard decoding. The look-up table of the flip strategy to improve the correction rate can use a neutral flip strategy with a higher number of iterations in order to perform error correction on codewords with more errors, such as an additional correction of 0.05% under the same correction rate The raw bit error rate (raw bit error rate, RBER). The flip strategy lookup table for reducing power consumption can use a more conservative flip strategy with fewer iterations, so the power consumption of the decoder 215 can be reduced under the same hardware parallelism. In some embodiments, the partial flip strategy lookup table in the flip decision unit 6131 can be designed for two or more decoding targets, for example, the throughput and the correction rate can be improved at the same time, but the present invention is not limited to this. In addition, compared to Fig. 5, the decoder using the variable node unit in Fig. 6 can have better decoding performance.

The bit flip circuit 6132 determines whether the corresponding code word bit and its reliability information R need to be flipped according to the table lookup result DR of each code word bit, and updates the code word VN_new after bit flipping and the update reliability The degree information R_new is stored in the variable node memory 2182. The bit flip circuit 6132 calculates the codeword difference Diff between the previous codeword obtained in this iterative operation and the updated codeword, for example, VN_next-VN_prev, and transmits the codeword difference Diff To check node unit 420. It should be noted that the bit flip circuit 6132 transmits the codeword difference to the check node unit 420, but the bit flip circuit 6132 does not transmit the update reliability information R_new to the check node unit 420, but updates the reliability. The information R_new is stored in the variable node memory 2182 for use in the next iteration operation.

Fig. 7 is a block diagram of the variable node unit in the third embodiment of the present invention. Please refer to FIG. 4 and FIG. 7 at the same time. In the third embodiment, the variable node unit 410 includes, for example, a syndrome weight sum unit 711, a threshold calculator 712, and a flip Unit (flip unit) 613. The calculation method of the symptom weight summation unit 711 in Fig. 7 is different from that of the symptom weight summation unit 611 in Fig. 6A. The symptom weight summation unit 711 is used to generate data from the check node unit 420. The symptom value syndrome is used to generate the symptom weight ws corresponding to each code word bit. The threshold calculation unit 612 is used to calculate a threshold used in the current decoding process. In this embodiment, the threshold value generated by the threshold value calculation unit 712 for the current decoding iteration process is, for example, a fixed value, but the threshold value of each decoding iteration process is not necessarily the same.

The flip unit 713 includes a flip decision unit 7131 and a bit flip circuit 7132. The flip decision unit 7131 includes flip strategy lookup tables 701 and 702, wherein the flip strategy lookup tables 701 and 702 respectively have different flip strategies. The rollover strategy lookup tables 701 and 702 can be pre-stored in the storage unit 212, and when the data storage device 200 is turned on, the processing unit 211 can load the rollover strategy lookup tables 701 and 702 into the buffer memory 218 or a register set (register file).

The rollover determination unit 7131 determines which one of the rollover strategy look-up tables 701 and 702 should be selected according to the channel value CH_sgn from the channel value memory 2181 and the previous code word VN_prev from the variable node memory 2182. When one of the flipping strategy look-up tables 701 and 702 is selected, the flipping determining unit 7131 can determine the corresponding flipping strategy based on the current symptom weight ws of each codeword bit and the above-mentioned threshold th.

In detail, the channel value CH_sgn and the previous codeword VN_prev have the same length, and both include a plurality of bits. The channel value CH_sgn can be regarded as the original codeword, for example. Because in the current iteration process (for example, the number of iterations is N), the previous code word VN_prev is the variable node unit 410 in the operation of the previous iteration (for example, the number of iterations is N-1). The word VN_prev is the updated code word VN_new generated after bit flipping. Therefore, the channel value CH_sgn and the previous codeword VN_prev obtained in the current iteration process can be used to determine which codeword bits in the original codeword have been inverted.

It should be noted that for the normal flash memory 220, the data error rate is about 1% or less, so the probability that each code word bit in the channel value CH_sgn is the correct bit is relatively high. Therefore, for the codeword bits that have not been flipped in the previous codeword VN_prev, the flipping determination unit 7131 will use the flipping strategy look-up table 701 and determine the corresponding value according to the current symptom weight ws of each codeword bit and the above threshold th. The rollover strategy in which the rollover strategy look-up table 701 is shown in Table 3. For the codeword bits that have been flipped in the previous codeword VN_prev, the flip determination unit 7131 will use the flip strategy lookup table 702 and determine the corresponding flip based on the current symptom weight ws of each codeword bit and the above threshold th Strategy, in which the rollover strategy look-up table 702 is shown in Table 4. th ws 0 1 2 3 4 0 X W W W W 1 X W W W W 2 X X W W W 3 X X X W S 4 X X X W S table 3 th ws 0 1 2 3 4 0 X X W W W 1 X X X W W 2 X X X X W 3 X X X X W 4 X X X X S Table 4

In this embodiment, compared to the flip strategy used in the flip strategy lookup table 701, the flip strategy used in the flip strategy lookup table 702 is more conservative, which means the flip strategy used in the flip strategy lookup table 702 The overall flip order will be lower than the overall flip order lookup table 701. For example, for a normal flash memory 220 with a very low data error rate, if the original codeword (ie, channel value) read from the flash memory 220 has an error ratio, Very low. Since in this case, some codeword bits are still bit flipped by the variable node unit 410, it means that the symptom weight ws corresponding to these codeword bits may be too high, and if more aggressive flipping is performed Strategies, such as the aforementioned strong reversal method, have a greater probability of reversing the codeword bits into codeword bits that are actually wrong. At this time, the codeword bits of the flipped error still need more iterations to be corrected, which means that the penalty for flipping errors is also higher, so the codeword bits that have been flipped will be more conservative The flip strategy, such as the aforementioned weak flip or no action mode.

The bit flip circuit 7132 determines whether the corresponding code bit and its reliability information R need to be flipped according to the table lookup result DR of each code word bit, and updates the code word VN_new after bit flipping and the update reliability The degree information R_new is stored in the variable node memory 2182. The bit flip circuit 7132 calculates the codeword difference Diff between the previous codeword obtained in this iterative operation and the updated codeword, for example, VN_next-VN_prev, and transmits the codeword difference Diff To check node unit 420. It should be noted that the bit flip circuit 7132 transmits the codeword difference to the check node unit 420, but the bit flip circuit 7132 does not transmit the update reliability information R_new to the check node unit 420, but updates the reliability. The information R_new is stored in the variable node memory 2182 for use in the next iteration operation.

In some embodiments, the function of the syndrome weight adding unit 711 in Figure 7 is similar to the syndrome weight adding unit 611 in Figure 6, which can be based on the syndrome value generated from the check node unit 420 syndrome and the channel value CH_sgn from the channel value memory 2181 to generate the syndrome weight ws corresponding to each code word bit.

In addition, the embodiments of Fig. 6 and Fig. 7 of the present invention can also be implemented in combination. For example, in Figure 6, different flipping strategy lookup tables can be selected for different decoding goals of the decoder, such as increasing throughput, increasing correction rate, or reducing power consumption, etc. . After adding the design of the embodiment in Figure 7, the different flipping strategy lookup tables in Figure 6 can be subdivided into the first flipping strategy lookup table for the codeword bits that have not been flipped and the lookup table for the flipped codeword bits. The second flipping strategy lookup table for codeword bits. Therefore, the above implementation can further increase the performance of the decoder 215.

FIG. 8 is a flowchart of a method for accessing a flash memory according to an embodiment of the present invention. Please refer to Fig. 2 and Fig. 8 at the same time. The procedure of the flash memory access method is as follows. The access method of the flash memory in Figure 8, for example, uses a strategy-based bit-reversal LDPC decoding method when reading data from the flash memory.

In step S805, the data is stored in the flash memory 220 of the data storage device 200 through a storage procedure. For example, the above-mentioned storage process may pass the data that the host wants to store to the data storage device 200 through an encoding process (for example, LDPC encoding), and write the encoded data to the flash memory 220.

In step S810, the variable node unit 410 obtains a channel value read from a flash memory 220 of the data storage device 200. For example, starting from step S810 is the decoding process performed by the memory controller 210 reading data from the flash memory 220, and the decoding process is relative to the encoding process described above.

In step S820, the check node unit 420 obtains a codeword difference from the variable node unit 410, and calculates a syndrome according to the codeword difference.

In step S830, during each iteration of LDPC decoding, the variable node unit 410 executes steps S832 to S840.

In step S832, it is determined whether the symptom value generated by the check node unit 420 is zero. If the symptom value is 0, the decoding process is ended. If the symptom value is not 0, continue to perform step S834.

In step S834, a syndrome weight is determined according to the channel value and the syndrome value from the check node unit 420. Among them, each codeword bit in the previous codeword has a corresponding symptom weight.

In step S836, a previous codeword generated by a previous LDPC decoding iteration is obtained. For example, the updated codeword generated in the previous iteration is the previous codeword used in the current iteration.

In step S838, a flip strategy of one bit flip algorithm of each codeword bit of the previous codeword is determined according to the symptom weight and a predetermined threshold, and one or more of the previous codewords are flipped according to the flip strategy The codeword bits are used to generate an updated codeword. For example, the flip decision unit 6131 includes a flip strategy look-up table 601 for recording different values of symptom weights and flip strategies corresponding to predetermined thresholds. The flip strategies include strong flip strategies and weak flip strategies. ) Strategy and non-action strategy, but the present invention is not limited to this.

In step S840, the updated codeword is subtracted from the previous codeword to generate a codeword difference. It should be noted that in the above-mentioned bit flipping process, the reliability information of each codeword bit will be considered together and the bit flipping will be performed according to the flipping strategy, but the bit flipping circuit 6132 will update the codeword. After subtracting the previous codeword to generate the codeword difference, only the codeword difference is sent to the check node unit 420, and the reliability information corresponding to each codeword bit in the updated codeword is stored in the variable node memory 2182.

In summary, the present invention provides a memory controller and flash memory access method, which allows the variable node unit in an LDPC decoder using bit-flipper to execute configurable The decoding strategy, for example, can be set for different decoding goals of the decoder, including: increasing throughput, increasing correction rate, or reducing power consumption, etc. In addition, the variable node unit of the decoder in the present invention can select appropriate flipping strategy lookup tables for the codeword bits that have been flipped and the codeword bits that have not been flipped, thereby improving decoding performance.

Although the present invention is disclosed as above in a preferred embodiment, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. Retouching, therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.

200: data storage device 210: memory controller 211: processing unit 212: storage unit 213: startup program 214: encoder 215: decoder 216: control logic 218: buffer memory 2181: channel value memory 2182: variable node Memory 220: Flash memory 230: Host 240: Physical block 241: Physical page 250, 252: Access interface 410: Variable node unit 420: Check node unit 511, 611, 711: Symptom weight summing unit 512 , 612, 712: threshold calculation unit 513, 613, 713: flip unit 5131: comparator 6131, 7131: flip decision unit 5132, 6132, 7132: bit flip circuit 601, 701, 702: flip strategy lookup table S805-S840 : Step H: Parity check matrix c: Number of columns t: Number of rows M, K, P: Matrix K ^-1 : Inverse matrix syndrome: Symptom value CH_sgn: Channel value ws: Weight th: Threshold Diff: Code word difference VN_prev: previous code word VN_new: update code word C1-C4: check node V1-V7: variable node S1, S0, W1, W0: status

Figure 1A is a schematic diagram of the parity check matrix. Figure 1B is a schematic diagram of the Tanner Graph. FIG. 2 is a block diagram of a data storage device according to an embodiment of the invention. Figure 3 is a schematic diagram of a check code check matrix and a check code generation matrix. Figure 4 is a block diagram of the decoder 215 in an embodiment according to the present invention. Figure 5 is a block diagram of the variable node unit in the first embodiment of the present invention. FIG. 6A is a block diagram of the variable node unit in the second embodiment of the present invention. FIG. 6B is a schematic diagram of the logic state of the flip strategy according to the second embodiment of the present invention. Fig. 7 is a block diagram of the variable node unit in the third embodiment of the present invention. FIG. 8 is a flowchart of a method for accessing a flash memory according to an embodiment of the present invention.

200: Data storage device

210: Memory Controller

211: Processing Unit

212: storage unit

213: Start the program

214: encoder

215: decoder

216: control logic

218: buffer memory

2181: Channel value memory

2182: Variable node memory

220: flash memory

230: host

240: physical block

241: Entity page

250, 252: Access interface

Claims (12)

A memory controller for a data storage device, the memory controller includes: A variable node unit for obtaining a channel value read from a flash memory of the data storage device; and A check node unit for obtaining a codeword difference from the variable node unit, and calculating a syndrome according to the codeword difference; Among them, during each iteration of low-density parity check code (LDPC) decoding, the variable node unit executes: Determine a syndrome weight based on the channel value and the syndrome value from the check node unit; Obtain a previous codeword generated by a previous LDPC decoding iteration; Obtaining a first flipping strategy lookup table from a plurality of flipping strategy lookup tables according to a decoding target of the memory controller; According to the symptom weight, a predetermined threshold, and the first flipping strategy look-up table to determine a bit-flipping algorithm for each bit-flipping algorithm of the previous codeword, and according to the flipping Strategy to flip one or more codeword bits in the previous codeword to generate an updated codeword; and The updated codeword is subtracted from the previous codeword to generate the codeword difference. For the memory controller described in item 1 of the scope of patent application, wherein the flipping order used in the flipping strategy look-up tables includes a first flipping order, a second flipping order, and a third flipping order, and these The number of LDPC iterations used in the flip strategy lookup table includes the first iteration, the second iteration, and the third iteration. Wherein the first flip order is greater than the second flip order, and the second flip order is greater than the third flip order, Wherein the first iteration number is greater than the second iteration number, and the second iteration number is greater than the third iteration number. The memory controller according to the second item of the scope of patent application, wherein when the decoding goal is to improve throughput, the first flipping strategy look-up table uses the first flipping order and the third iteration number. The memory controller described in item 2 of the scope of patent application, wherein when the decoding goal is to increase the correction rate, the first flip strategy look-up table uses the second flip order and the first iteration number. For the memory controller described in item 2 of the scope of patent application, when the decoding goal is to reduce power consumption, the first flip strategy look-up table uses the third flip order and the third iteration number. For example, the memory controller described in item 1 of the scope of patent application, wherein the variable node unit further flips one or more codeword bits in the previous codeword according to the flipping strategy and the corresponding reliability of each codeword bit Degree information to generate the update codeword and the reliability information corresponding to each codeword bit in the update codeword, and the reliability information corresponding to the update codeword and each codeword bit in the update codeword The information is stored in a variable node memory for the next iteration of LDPC decoding. A method for accessing flash memory is applied to a memory controller in a data storage device. The method includes: Store data to a flash memory of the data storage device through a storage procedure; Obtain a channel value read from the flash memory; Obtain a codeword difference, and calculate a syndrome according to the codeword difference; and During each iteration of low-density parity check code (LDPC) decoding, perform the following steps: Determine a syndrome weight based on the channel value and the symptom value; Obtain a previous codeword generated by a previous LDPC decoding iteration; Obtaining a first flipping strategy lookup table from a plurality of flipping strategy lookup tables according to a decoding target of the memory controller; According to the symptom weight, a predetermined threshold, and the first flipping strategy look-up table to determine a bit-flipping algorithm for each bit-flipping algorithm of the previous codeword, and according to the flipping Strategy to flip one or more codeword bits in the previous codeword to generate an updated codeword; and The updated codeword is subtracted from the previous codeword to generate the codeword difference. For the flash memory access method described in item 7 of the scope of patent application, wherein the flip order used in the flip strategy look-up tables includes the first flip order, the second flip order, and the third flip order , And the number of LDPC iterations used in these flipping strategy lookup tables includes the first iteration, the second iteration and the third iteration Wherein the first flip order is greater than the second flip order, and the second flip order is greater than the third flip order, Wherein the first iteration number is greater than the second iteration number, and the second iteration number is greater than the third iteration number. The method for accessing flash memory as described in item 8 of the scope of patent application, wherein when the decoding goal is to improve throughput, the first flipping strategy look-up table uses the first flipping order and the third iteration frequency. The flash memory access method described in item 8 of the scope of patent application, wherein when the decoding goal is to improve the correction rate, the first flip strategy look-up table uses the second flip order and the first iteration frequency. The method for accessing flash memory as described in item 8 of the scope of patent application, wherein when the decoding goal is to reduce power consumption, the first flip strategy look-up table uses the third flip order and the third iteration frequency. The flash memory access method described in item 7 of the scope of patent application further includes: According to the flipping strategy, one or more codeword bits in the previous codeword and the reliability information corresponding to each codeword bit are flipped to generate the updated codeword and the corresponding codeword bits in the updated codeword The reliability information of; and The updated codeword and the reliability information corresponding to each codeword bit in the updated codeword are stored in a variable node memory for the next LDPC decoding iteration.

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