TW202013192A - Decoder design method and storage controller - Google Patents
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
Description
本發明是有關於一種解碼器設計方法,且特別是有關於準循環低密度奇偶校驗解碼器的一種解碼器設計方法,以及儲存控制器。The present invention relates to a decoder design method, and more particularly to a decoder design method for a quasi-cyclic low-density parity check decoder and a storage controller.
數位相機、行動電話與MP3播放器在這幾年來的成長十分迅速,使得消費者對儲存媒體的需求也急速增加。由於可複寫式非揮發性記憶體模組(例如,快閃記憶體)具有資料非揮發性、省電、體積小,以及無機械結構等特性,所以非常適合內建於上述所舉例的各種可攜式多媒體裝置中。Digital cameras, mobile phones and MP3 players have grown rapidly in recent years, and consumers' demand for storage media has also increased rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for the built-in various Portable multimedia device.
一般來說,為了避免從記憶體裝置中讀取出來的資料發生錯誤,欲儲存在記憶體裝置中的資料會被編碼爾後再被儲存。當欲讀取此資料時,整個編碼資料會被讀取出來並且被解碼。藉此,可透過解碼程序來更正可能存在的錯誤。在解碼過程期間,糾錯碼用於確定讀取碼字(讀取數據)中的一個或多個錯誤,並且校正所確定的錯誤。其中一個著名的錯誤更正碼稱為準循環低密度奇偶校驗(Quasi-Cyclic low-density parity check,QC-LDPC)碼。 在QC-LDPC中,置換網路在解碼效率和高數據速率方面起著重要作用。傳統上,會實現全尺寸多層置換網路。但是當置換網路變得更大時,放置晶片/選擇器(QC-LDPC解碼器的置換網路中的電子元件)以及連接到元件的路由線(佈線)的難度變得更大。另一個問題是,由於在較大的置換網路中,訊號會通過較長的運算路徑,需要更多時間來完成整個解碼過程,導致解碼過程的處理週期將變得更長。In general, in order to avoid errors in the data read from the memory device, the data to be stored in the memory device will be encoded and then stored. When you want to read this data, the entire encoded data will be read and decoded. In this way, possible errors can be corrected through the decoding process. During the decoding process, the error correction code is used to determine one or more errors in the read codeword (read data) and correct the determined errors. One of the well-known error correction codes is called Quasi-Cyclic low-density parity check (QC-LDPC) codes. In QC-LDPC, the replacement network plays an important role in decoding efficiency and high data rate. Traditionally, full-scale multilayer replacement networks have been implemented. But as the replacement network becomes larger, it becomes more difficult to place the chip/selector (the electronic component in the replacement network of the QC-LDPC decoder) and the routing line (wiring) connected to the component. Another problem is that, in a larger replacement network, the signal will pass through a longer computing path, requiring more time to complete the entire decoding process, resulting in a longer processing cycle of the decoding process.
因此,如何設計QC-LDPC解碼器的置換網路以減少解碼過程的時間/功耗並降低置換電路的硬件成本以進一步提高QC-LDPC解碼器的效率,為本領域技術人員的研究的主題之一。Therefore, how to design the replacement network of the QC-LDPC decoder to reduce the time/power consumption of the decoding process and reduce the hardware cost of the replacement circuit to further improve the efficiency of the QC-LDPC decoder is the subject of research by those skilled in the art One.
本發明提供一種解碼器設計方法,與儲存控制器,可減少所需的選擇器/移位暫存器之數量,提昇解碼的速度,進而增進解碼器的效率。The invention provides a decoder design method and a storage controller, which can reduce the number of selectors/shift registers required, increase the decoding speed, and thus improve the efficiency of the decoder.
本發明的一實施例提供一種解碼器設計方法,適用於設計對應一可複寫式非揮發性記憶體模組的一準循環低密度奇偶校驗碼(quasi-cyclic low-density parity check,QC-LDPC)解碼器的置換電路。所述方法包括:辨識可複寫式非揮發性記憶體模組的實體頁面的大小為頁面大小,其中所述實體頁面用以儲存多個碼字;根據所述多個碼字與所述頁面大小來獲得所述多個碼字的每一個的碼字長度;辨識所述OC-LDPC解碼器的預定檢查矩陣,其中所述檢查矩陣包括MⅹN個子矩陣,其中每一所述子矩陣為ZⅹZ矩陣,其中Z為每個子矩陣的預設維度值,並且所述預設維度值為經由對所述碼字長度除以N所獲得的商值;根據所述預設維度值來計算一第一數值,並且根據所述第一數值、所述預設維度值和所述檢查矩陣的移位類型識別第一置換網路,其中所述第一置換網路包括依序排列的多個第一置換層,所述第一置換層中的每一個第一置換層具有相同數量的第一節點,其中第一置換層的數量由所述第一數值所設置,並且每個第一置換層的第一節點的數量由所述預設維度值所設置,其中所述多個第一置換層中的一個第一置換層的每一個第一節點連接至下一個第一置換層的一對第一節點;根據所述檢查矩陣的所述移位類型辨識所述第一置換網路的所述多個第一置換層中的目標第一置換層,並經由從所述第一置換網路中去除所述目標第一置換層來建構第二置換網路;以及設置多個選擇器於所述置換電路的所述第二置換網路的多個第二節點上,並且根據所述第二置換網路將多條路由線設置到所述置換電路中以連接所述多個選擇器,其中所述多個選擇器更分別連接至所述QC-LDPC解碼器的解碼控制器,其中所述解碼控制器用以控制所述多個選擇器來將對應一目標碼字的多個第一變量群組移位成為多個第二變量群組,其中所述多個第二變量群組根據對應所述多個第一變量群組與所述多個第二變量群組的多個目標偏移量分別被移位,其中所述多個目標偏移量是根據所述檢查矩陣所辨識的。An embodiment of the present invention provides a decoder design method suitable for designing a quasi-cyclic low-density parity check (QC-) corresponding to a rewritable non-volatile memory module LDPC) decoder replacement circuit. The method includes: identifying a physical page size of a rewritable non-volatile memory module as a page size, wherein the physical page is used to store a plurality of codewords; based on the plurality of codewords and the page size To obtain the codeword length of each of the plurality of codewords; identify a predetermined check matrix of the OC-LDPC decoder, wherein the check matrix includes MⅹN sub-matrices, each of which is a ZⅹZ matrix, Where Z is a preset dimension value of each sub-matrix, and the preset dimension value is a quotient value obtained by dividing the codeword length by N; a first value is calculated according to the preset dimension value, And identify a first replacement network according to the first value, the preset dimension value, and the shift type of the check matrix, wherein the first replacement network includes a plurality of first replacement layers arranged in sequence, Each first replacement layer in the first replacement layer has the same number of first nodes, where the number of first replacement layers is set by the first value, and the first node of each first replacement layer The number is set by the preset dimension value, wherein each first node of one first replacement layer of the plurality of first replacement layers is connected to a pair of first nodes of the next first replacement layer; The shift type of the check matrix identifies a target first replacement layer among the plurality of first replacement layers of the first replacement network, and removes the target first object from the first replacement network A replacement layer to construct a second replacement network; and setting a plurality of selectors on a plurality of second nodes of the second replacement network of the replacement circuit, and according to the second replacement network A routing line is provided in the replacement circuit to connect the plurality of selectors, wherein the plurality of selectors are respectively connected to the decoding controller of the QC-LDPC decoder, wherein the decoding controller is used to control all Multiple selectors to shift multiple first variable groups corresponding to a target codeword into multiple second variable groups, wherein the multiple second variable groups correspond to the multiple first variables The multiple target offsets of the group and the multiple second variable groups are respectively shifted, wherein the multiple target offsets are identified according to the inspection matrix.
本發明的另一實施例提供一種儲存控制器。所述儲存控制器用以控制具有可複寫式非揮發性記憶體模組的儲存裝置。所述儲存控制器包括的錯誤檢查與校正電路、記憶體介面控制電路以及處理器。所述錯誤檢查與校正電路包括準循環低密度奇偶校驗碼(Quasi-Cyclic low-density parity check,QC-LDPC)解碼器,其中所述準循環低密度奇偶校驗碼解碼器用以執行解碼程序於目標碼字,其中所述準循環低密度奇偶校驗碼解碼器包括置換電路。所述記憶體介面控制電路用以耦接至可複寫式非揮發性記憶體模組。所述可複寫式非揮發性記憶體模組具有多個實體頁面,並且每一所述多個實體頁面的大小被辨識為一頁面大小,其中所述實體頁面用以儲存多個碼字,並且所述目標碼字從所述多個實體頁面中的目標實體頁面被讀取,其中每一所述多個碼字的長度根據所述多個碼字的數量與所述頁面大小被獲得,為一碼字長度。所述處理器耦接至所述錯誤檢查與校正電路與所述記憶體介面控制電路。所述記憶體介面控制電路傳送從可複寫式非揮發性記憶體模組所讀取的所述碼字至所述錯誤檢查與校正電路,並且所述處理器用以指示所述錯誤檢查與校正電路對所述目標碼字執行所述解碼程序。所述置換電路包括多個選擇器、連接至每一所述多個選擇器的多個路由線、多個輸入端與多個輸出端。所述QC-LDPC解碼器的預定檢查矩陣被辨識,並且所述檢查矩陣包括MⅹN個子矩陣,其中每一所述子矩陣為ZⅹZ矩陣,其中Z為每個子矩陣的預設維度值,並且所述預設維度值為經由對所述碼字長度除以N所獲得的商值,其中用以設置所述多個選擇器與所述多個路由線至所述置換電路的一第二置換網路經由從一第一置換網路中移除一目標第一置換層被建構。所述第一置換網路是根據所述第一數值、所述預設維度值和所述檢查矩陣的移位類型所辨識的,其中所述第一置換網路包括依序排列的多個第一置換層,所述第一置換層中的每一個第一置換層具有相同數量的第一節點,其中第一置換層的數量由所述第一數值所設置,並且每個第一置換層的第一節點的數量由所述預設維度值所設置,其中所述多個第一置換層中的一個第一置換層的每一個第一節點連接至下一個第一置換層的一對第一節點。其中所述第一置換網路中的所述多個第一置換層中的目標第一置換層是根據所述檢查矩陣的所述移位類型所辨識的。此外,所述多個選擇器於被設置於所述置換電路的所述第二置換網路的多個第二節點上,並且所述多條路由線根據所述第二置換網路被設置到所述置換電路中以連接所述多個選擇器,其中所述多個選擇器更分別連接至所述QC-LDPC解碼器的解碼控制器,其中所述解碼控制器用以控制所述多個選擇器來將對應一目標碼字的多個第一變量群組移位成為多個第二變量群組,其中所述多個第二變量群組根據對應所述多個第一變量群組與所述多個第二變量群組的多個目標偏移量分別被移位,其中所述多個目標偏移量是根據所述檢查矩陣所辨識的。Another embodiment of the invention provides a storage controller. The storage controller is used to control a storage device having a rewritable non-volatile memory module. The storage controller includes an error checking and correcting circuit, a memory interface control circuit, and a processor. The error checking and correcting circuit includes a quasi-cyclic low-density parity check (QC-LDPC) decoder, wherein the quasi-cyclic low-density parity check decoder is used to perform a decoding process For the target codeword, the quasi-cyclic low density parity check code decoder includes a replacement circuit. The memory interface control circuit is used to couple to a rewritable non-volatile memory module. The rewritable non-volatile memory module has multiple physical pages, and the size of each of the multiple physical pages is recognized as a page size, wherein the physical page is used to store multiple codewords, and The target codeword is read from the target physical page among the plurality of physical pages, wherein the length of each of the plurality of codewords is obtained according to the number of the plurality of codewords and the page size, is One codeword length. The processor is coupled to the error checking and correcting circuit and the memory interface control circuit. The memory interface control circuit transmits the codeword read from the rewritable non-volatile memory module to the error checking and correction circuit, and the processor is used to instruct the error checking and correction circuit The decoding procedure is performed on the target codeword. The replacement circuit includes multiple selectors, multiple routing lines connected to each of the multiple selectors, multiple input terminals, and multiple output terminals. A predetermined check matrix of the QC-LDPC decoder is identified, and the check matrix includes MⅹN sub-matrices, where each of the sub-matrices is a ZⅹZ matrix, where Z is a preset dimension value of each sub-matrix, and the The preset dimension value is a quotient value obtained by dividing the codeword length by N, wherein a second replacement network for setting the plurality of selectors and the plurality of routing lines to the replacement circuit It is constructed by removing a target first replacement layer from a first replacement network. The first replacement network is identified based on the first value, the preset dimension value, and the shift type of the check matrix, wherein the first replacement network includes a plurality of A substitution layer, each of the first substitution layers in the first substitution layer has the same number of first nodes, wherein the number of first substitution layers is set by the first value, and each of the first substitution layers The number of first nodes is set by the preset dimension value, wherein each first node of one first replacement layer of the plurality of first replacement layers is connected to a pair of first nodes of the next first replacement layer node. The target first replacement layer among the plurality of first replacement layers in the first replacement network is identified according to the shift type of the check matrix. In addition, the plurality of selectors are provided on a plurality of second nodes of the second replacement network provided in the replacement circuit, and the plurality of routing lines are set to The plurality of selectors are connected in the replacement circuit, wherein the plurality of selectors are respectively connected to a decoding controller of the QC-LDPC decoder, wherein the decoding controller is used to control the plurality of selections To shift a plurality of first variable groups corresponding to a target codeword into a plurality of second variable groups, wherein the plurality of second variable groups correspond to the plurality of first variable groups and all The multiple target offsets of the multiple second variable groups are respectively shifted, wherein the multiple target offsets are identified according to the inspection matrix.
基於上述,本發明的實施例所提供的解碼器設計方法與儲存控制器,可以經由根據QC-LDPC解碼器的檢查矩陣的移位類型從第一置換網路中移除目標第一置換層,以構建改進的第二置換網路,所述第二置換網路用於在QC-LDPC解碼器的置換電路中佈置較少的選擇器和路由線。如此一來,可使置換電路的硬件成本降低,並且相應地降低功耗和產生的熱量。Based on the above, the decoder design method and the storage controller provided by the embodiments of the present invention can remove the target first replacement layer from the first replacement network via the shift type according to the check matrix of the QC-LDPC decoder, In order to construct an improved second replacement network, the second replacement network is used to arrange fewer selectors and routing lines in the replacement circuit of the QC-LDPC decoder. In this way, the hardware cost of the replacement circuit can be reduced, and the power consumption and heat generated can be reduced accordingly.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.
一般而言,記憶體儲存裝置(亦稱,記憶體儲存系統)包括可複寫式非揮發性記憶體模組(rewritable non-volatile memory module)與控制器(亦稱,控制電路)。通常記憶體儲存裝置是與主機系統一起使用,以使主機系統可將資料寫入至記憶體儲存裝置或從記憶體儲存裝置中讀取資料。Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also known as a control circuit). Usually, the memory storage device is used together with the host system, so that the host system can write data to the memory storage device or read data from the memory storage device.
圖1是根據本發明的一實施例所繪示的主機系統、記憶體儲存裝置及輸入/輸出(I/O)裝置的示意圖。圖2是根據本發明的另一實施例所繪示的主機系統、記憶體儲存裝置及I/O裝置的示意圖。FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an embodiment of the invention. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another embodiment of the invention.
請參照圖1與圖2,主機系統11一般包括處理器111、隨機存取記憶體(random access memory, RAM)112、唯讀記憶體(read only memory, ROM)113及資料傳輸介面114。處理器111、隨機存取記憶體112、唯讀記憶體113及資料傳輸介面114皆耦接至系統匯流排(system bus)110。Referring to FIGS. 1 and 2, the
在本實施例中,主機系統11是透過資料傳輸介面114與記憶體儲存裝置10耦接。例如,主機系統11可經由資料傳輸介面114將資料儲存至記憶體儲存裝置10或從記憶體儲存裝置10中讀取資料。此外,主機系統11是透過系統匯流排110與I/O裝置12耦接。例如,主機系統11可經由系統匯流排110將輸出訊號傳送至I/O裝置12或從I/O裝置12接收輸入訊號。In this embodiment, the
在本實施例中,處理器111、隨機存取記憶體112、唯讀記憶體113及資料傳輸介面114可設置在主機系統11的主機板20上。資料傳輸介面114的數目可以是一或多個。透過資料傳輸介面114,主機板20可以經由有線或無線方式耦接至記憶體儲存裝置10。記憶體儲存裝置10可例如是隨身碟201、記憶卡202、固態硬碟(Solid State Drive, SSD)203或無線記憶體儲存裝置204。無線記憶體儲存裝置204可例如是近距離無線通訊(Near Field Communication, NFC)記憶體儲存裝置、無線傳真(WiFi)記憶體儲存裝置、藍牙(Bluetooth)記憶體儲存裝置或低功耗藍牙記憶體儲存裝置(例如,iBeacon)等以各式無線通訊技術為基礎的記憶體儲存裝置。此外,主機板20也可以透過系統匯流排110耦接至全球定位系統(Global Positioning System, GPS)模組205、網路介面卡206、無線傳輸裝置207、鍵盤208、螢幕209、喇叭210等各式I/O裝置。例如,在一實施例中,主機板20可透過無線傳輸裝置207存取無線記憶體儲存裝置204。In this embodiment, the
在一實施例中,所提及的主機系統為可實質地與記憶體儲存裝置配合以儲存資料的任意系統。雖然在上述實施例中,主機系統是以電腦系統來作說明,然而,圖3是根據本發明的另一實施例所繪示的主機系統與記憶體儲存裝置的示意圖。請參照圖3,在另一實施例中,主機系統31也可以是數位相機、攝影機、通訊裝置、音訊播放器、視訊播放器或平板電腦等系統,而記憶體儲存裝置30可為其所使用的SD卡32、CF卡33或嵌入式儲存裝置34等各式非揮發性記憶體儲存裝置。嵌入式儲存裝置34包括嵌入式多媒體卡(embedded MMC, eMMC)341及/或嵌入式多晶片封裝儲存裝置(embedded Multi Chip Package, eMCP)342等各類型將記憶體模組直接耦接於主機系統的基板上的嵌入式儲存裝置。In one embodiment, the mentioned host system is any system that can substantially cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above embodiment, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another embodiment of the invention. Referring to FIG. 3, in another embodiment, the
圖4是根據本發明的一實施例所繪示的記憶體儲存裝置的概要方塊圖。4 is a schematic block diagram of a memory storage device according to an embodiment of the invention.
請參照圖4,記憶體儲存裝置10包括連接介面單元402、記憶體控制電路單元404與可複寫式非揮發性記憶體模組406。4, the
在本實施例中,連接介面單元402是相容於序列先進附件(Serial Advanced Technology Attachment, SATA)標準。然而,必須瞭解的是,本發明不限於此,連接介面單元402亦可以是符合並列先進附件(Parallel Advanced Technology Attachment, PATA)標準、電氣和電子工程師協會(Institute of Electrical and Electronic Engineers, IEEE)1394標準、高速周邊零件連接介面(Peripheral Component Interconnect Express, PCI Express)標準、通用序列匯流排(Universal Serial Bus, USB)標準、安全數位(Secure Digital, SD)介面標準、超高速一代(Ultra High Speed-I, UHS-I)介面標準、超高速二代(Ultra High Speed-II, UHS-II)介面標準、記憶棒(Memory Stick, MS)介面標準、多晶片封裝(Multi-Chip Package)介面標準、多媒體儲存卡(Multi Media Card, MMC)介面標準、崁入式多媒體儲存卡(Embedded Multimedia Card, eMMC)介面標準、通用快閃記憶體(Universal Flash Storage, UFS)介面標準、嵌入式多晶片封裝(embedded Multi Chip Package, eMCP)介面標準、小型快閃(Compact Flash, CF)介面標準、整合式驅動電子介面(Integrated Device Electronics, IDE)標準或其他適合的標準。連接介面單元402可與記憶體控制電路單元404封裝在一個晶片中,或者連接介面單元402是佈設於一包含記憶體控制電路單元404之晶片外。In this embodiment, the
記憶體控制電路單元404用以執行以硬體型式或韌體型式實作的多個邏輯閘或控制指令並且根據主機系統11的指令在可複寫式非揮發性記憶體模組406中進行資料的寫入、讀取與抹除等運作。The memory
可複寫式非揮發性記憶體模組406是耦接至記憶體控制電路單元404並且用以儲存主機系統11所寫入之資料。可複寫式非揮發性記憶體模組406可以是單階記憶胞(Single Level Cell, SLC)NAND型快閃記憶體模組(即,一個記憶胞中可儲存1個位元的快閃記憶體模組)、多階記憶胞(Multi Level Cell, MLC)NAND型快閃記憶體模組(即,一個記憶胞中可儲存2個位元的快閃記憶體模組)、複數階記憶胞(Triple Level Cell,TLC)NAND型快閃記憶體模組(即,一個記憶胞中可儲存3個位元的快閃記憶體模組)、其他快閃記憶體模組或其他具有相同特性的記憶體模組。The rewritable
圖5A是根據本發明的一實施例所繪示的記憶體控制電路單元的概要方塊圖。5A is a schematic block diagram of a memory control circuit unit according to an embodiment of the invention.
請參照圖5A,記憶體控制電路單元404包括記憶體管理電路502、主機介面504、記憶體介面506及錯誤檢查與校正電路508。5A, the memory
記憶體管理電路502用以控制記憶體控制電路單元404的整體運作。具體來說,記憶體管理電路502具有多個控制指令,並且在記憶體儲存裝置10運作時,此些控制指令會被執行以進行資料的寫入、讀取與抹除等運作。以下說明記憶體管理電路502的操作時,等同於說明記憶體控制電路單元404的操作。The
在本實施例中,記憶體管理電路502的控制指令是以韌體型式來實作。例如,記憶體管理電路502具有微處理器單元(未繪示)與唯讀記憶體(未繪示),並且此些控制指令是被燒錄至此唯讀記憶體中。當記憶體儲存裝置10運作時,此些控制指令會由微處理器單元來執行以進行資料的寫入、讀取與抹除等運作。In this embodiment, the control commands of the
在另一實施例中,記憶體管理電路502的控制指令亦可以程式碼型式儲存於可複寫式非揮發性記憶體模組406的特定區域(例如,記憶體模組中專用於存放系統資料的系統區)中。此外,記憶體管理電路502具有微處理器單元(未繪示)、唯讀記憶體(未繪示)及隨機存取記憶體(未繪示)。特別是,此唯讀記憶體具有開機碼(boot code),並且當記憶體控制電路單元404被致能時,微處理器單元會先執行此開機碼來將儲存於可複寫式非揮發性記憶體模組406中之控制指令載入至記憶體管理電路502的隨機存取記憶體中。之後,微處理器單元會運轉此些控制指令以進行資料的寫入、讀取與抹除等運作。In another embodiment, the control commands of the
此外,在另一實施例中,記憶體管理電路502的控制指令亦可以一硬體型式來實作。例如,記憶體管理電路502包括微控制器、記憶胞管理電路、記憶體寫入電路、記憶體讀取電路、記憶體抹除電路與資料處理電路。記憶胞管理電路、記憶體寫入電路、記憶體讀取電路、記憶體抹除電路與資料處理電路是耦接至微控制器。其中,記憶胞管理電路用以管理可複寫式非揮發性記憶體模組406的實體抹除單元;記憶體寫入電路用以對可複寫式非揮發性記憶體模組406下達寫入指令序列以將資料寫入至可複寫式非揮發性記憶體模組406中;記憶體讀取電路用以對可複寫式非揮發性記憶體模組406下達讀取指令序列以從可複寫式非揮發性記憶體模組406中讀取資料;記憶體抹除電路用以對可複寫式非揮發性記憶體模組406下達抹除指令序列以將資料從可複寫式非揮發性記憶體模組406中抹除;而資料處理電路用以處理欲寫入至可複寫式非揮發性記憶體模組406的資料以及從可複寫式非揮發性記憶體模組406中讀取的資料。寫入指令序列、讀取指令序列及抹除指令序列可各別包括一或多個程式碼或指令碼並且用以指示可複寫式非揮發性記憶體模組406執行相對應的寫入、讀取及抹除等操作。In addition, in another embodiment, the control commands of the
主機介面504是耦接至記憶體管理電路502並且用以接收與識別主機系統11所傳送的指令與資料。也就是說,主機系統11所傳送的指令與資料會透過主機介面504來傳送至記憶體管理電路502。在本實施例中,主機介面504是相容於SATA標準。然而,必須瞭解的是本發明不限於此,主機介面504亦可以是相容於PATA標準、IEEE 1394標準、PCI Express標準、USB標準、SD標準、UHS-I標準、UHS-II標準、MS標準、MMC標準、eMMC標準、UFS標準、CF標準、IDE標準或其他適合的資料傳輸標準。The
記憶體介面506是耦接至記憶體管理電路502並且用以存取可複寫式非揮發性記憶體模組406。也就是說,欲寫入至可複寫式非揮發性記憶體模組406的資料會經由記憶體介面506轉換為可複寫式非揮發性記憶體模組406所能接受的格式。具體來說,若記憶體管理電路502要存取可複寫式非揮發性記憶體模組406,記憶體介面506會傳送對應的指令序列。例如,這些指令序列可包括指示寫入資料的寫入指令序列、指示讀取資料的讀取指令序列、指示抹除資料的抹除指令序列、以及用以指示各種記憶體操作(例如,改變讀取電壓準位或執行垃圾回收程序等等)的相對應的指令序列,在此不一一贅述。這些指令序列例如是由記憶體管理電路502產生並且透過記憶體介面506傳送至可複寫式非揮發性記憶體模組406。這些指令序列可包括一或多個訊號,或是在匯流排上的資料。這些訊號或資料可包括指令碼或程式碼。例如,在讀取指令序列中,會包括讀取的辨識碼、記憶體位址等資訊。The
錯誤檢查與校正電路508是耦接至記憶體管理電路502並且用以執行錯誤檢查與校正程序以確保資料的正確性。具體來說,當記憶體管理電路502從主機系統11中接收到寫入指令時,錯誤檢查與校正電路508會為對應此寫入指令的資料產生對應的錯誤更正碼(error correcting code, ECC)及/或錯誤檢查碼(error detecting code,EDC),並且記憶體管理電路502會將對應此寫入指令的資料與對應的錯誤更正碼及/或錯誤檢查碼寫入至可複寫式非揮發性記憶體模組406中。之後,當記憶體管理電路502從可複寫式非揮發性記憶體模組406中讀取資料時會同時讀取此資料對應的錯誤更正碼及/或錯誤檢查碼,並且錯誤檢查與校正電路508會依據此錯誤更正碼及/或錯誤檢查碼對所讀取的資料執行錯誤檢查與校正程序。The error check and
在本實施例中,錯誤檢查與校正電路508所使用的是低密度奇偶檢查碼(low density parity code,LDPC)。然而,在另一實施例中,錯誤檢查與校正電路508所使用的也可以是BCH碼、迴旋碼(convolutional code)、渦輪碼(turbo code)、位元翻轉(bit flipping)等編/解碼演算法。In this embodiment, the error check and
在一實施例中,記憶體控制電路單元404還包括緩衝記憶體510與電源管理電路512。緩衝記憶體510是耦接至記憶體管理電路502並且用以暫存來自於主機系統11的資料與指令或來自於可複寫式非揮發性記憶體模組406的資料。電源管理電路512是耦接至記憶體管理電路502並且用以控制記憶體儲存裝置10的電源。In one embodiment, the memory
在本實施例中,記憶體管理電路502會配置邏輯單元來映射至可複寫式非揮發性記憶體模組406中的實體單元。例如,在本實施例中,主機系統11是透過邏輯位址來存取可複寫式非揮發性記憶體模組406中的資料,因此,每一個邏輯單元是指一個邏輯位址。然而,在另一實施例中,每一個邏輯單元也可以是指一個邏輯扇、一個邏輯頁或者由多個連續的邏輯位址組成。每一個邏輯單元是映射至一或多個實體單元。在本實施例中,一個實體單元是指一個實體區塊。然而,在另一實施例中,一個實體單元也可以是一個實體位址、一個實體扇、一個實體頁或者是由多個連續的實體位址組成,本發明不加以限制。In this embodiment, the
記憶體管理電路502會將邏輯單元與實體單元之間的映射關係記錄於一邏輯-實體映射表。當主機系統11欲從記憶體儲存裝置10讀取資料或寫入資料至記憶體儲存裝置10時,記憶體管理電路502可根據此邏輯-實體映射表來執行對於記憶體儲存裝置10的資料存取。The
圖5B是根據本發明的一實施例所繪示的記憶體控制電路單元的錯誤檢查與校正電路的方塊示意圖。請參照圖5B,錯誤檢查和校正電路508包括用於處理解碼操作的解碼器5081和用於處理編碼操作的編碼器5082。更具體地,錯誤檢查和校正電路508使用準循環LDPC(QC-LDPC)算法多次執行迭代解碼操作以解碼待解碼的碼字,並且下面的實施例中的解碼器5081例如是QC-LDPC解碼器。5B is a block diagram of an error checking and correcting circuit of a memory control circuit unit according to an embodiment of the invention. Referring to FIG. 5B, the error checking and
在該實施例中,由錯誤檢查和校正電路508對一個數據(碼字)執行的解碼操作包括初始校驗子計算操作,該初始校驗子計算操作可用於獲得用於確定解碼是否正確的最終校驗子。然後,可以根據解碼是否正確來確定是否需要執行一個或多個後續的迭代操作。每次(每輪)迭代操作結束時,計算對應於當前碼字的最終校驗子,以便確定當前迭代操作是否成功。如果解碼成功(在解碼之後產生的碼字是正確的,即有效碼字),則結束當前的迭代操作,並且也結束對該碼字的整個解碼操作; 如果解碼失敗(在解碼之後產生的碼字不正確,即無效的碼字),則結束當前的迭代操作,並重新開始一個新的(下一輪)迭代操作。In this embodiment, the decoding operation performed on a piece of data (codeword) by the error check and
在本實施例中,將記錄在每個解碼操作中所執行的多個迭代操作的總數目。在每個解碼操作中,連續執行迭代操作,直到迭代操作的總數目達到預設上限值。製造商可以根據需求設置預設上限值,本發明不限於此。錯誤檢查與校正電路508所使用的LDPC演算法的進一步細節將隨著之後的圖6來解釋。In this embodiment, the total number of multiple iteration operations performed in each decoding operation will be recorded. In each decoding operation, iterative operations are continuously performed until the total number of iterative operations reaches a preset upper limit value. The manufacturer can set a preset upper limit value according to requirements, and the present invention is not limited thereto. Further details of the LDPC algorithm used by the error checking and
圖5C是根據本發明的一實施例所繪示的錯誤檢查與校正電路的解碼器的方塊示意圖。請參考圖5C,在本實施例中,解碼器5081包括解碼控制器581,緩衝器582,檢查節點電路583,變量節點電路584,置換電路585,校驗子計算電路586和終止電路587。解碼控制器581耦接(電性連接)至緩衝器582,檢查節點電路583,變量節點電路584,置換電路585,校驗子計算電路586和終止電路587。5C is a block diagram of a decoder of an error checking and correcting circuit according to an embodiment of the invention. 5C, in this embodiment, the
解碼控制器581,用以根據記憶體管理電路502發出的指令,來管理所執行的解碼過程的整個過程。此外,解碼控制器581被配置為接收要解碼的碼字(也稱為目標碼字),並根據(默認)奇偶檢查矩陣(也稱為稀疏奇偶檢查矩陣或檢查矩陣)將碼字的多個資料位元值(例如,有n個資料位元值)分組為多個資料位元值組(例如,N個數據位元值組,其中N = n / Z)。例如,根據碼字中的所有資料位元值的序列,從第一資料位元值開始,每Z個資料位元值被分組為一個資料位元值組。The
在本實施例中,可複寫式非揮發性記憶體模組406包括多個實體頁面,這些實體頁面將被分組為多個實體區塊。每個實體頁面的長度(空間)被預設為頁面大小。每個實體頁面用以儲存多個碼字。In this embodiment, the rewritable
緩衝器582被用以暫時儲存資料,例如對應於碼字的多個變量(或多個變量群組),檢查矩陣,對數似然比(LLR)表或在解碼過程中使用的其他合適的數據。The
在本實施例中,解碼控制器581還用以在開始對目標碼字執行解碼過程的同時對目標碼字執行初始化(initialization)。在初始化期間,解碼控制器581用以通過例如根據目標碼字查找所儲存的解碼表來獲得多個變量,其中通過初始化獲得的變量也稱為初始變量。在一實施例中,解碼表是LLR表,並且初始變量是與目標碼字的那些資料位元值對應的LLR。每個LLR表示相應資料位元值的可靠度(可靠值)。每個LLR的值可以由多個位元設置,並且一個LLR的值的位元數目可由預設精細度來被預先決定。例如,假設預設精細度為5,並且一個LLR的該5位值的範圍可以設置為-16到15(範圍的總大小是32,即25
),其中一個LLR的五個位元值是Ln(PR0 / PR1)的計算結果,其中PR0表示碼字的所述資料位元值為“0”的可能性,PR1表示所述碼字的資料位元值為“1”的可能性。PR0加PR1等於1。換句話說,如果一個資料位元值的LLR是-16,則所述資料位元值最可能是1;如果一個資料位元值的LLR為15,則所述數據位值最可能為0; 如果一個數據位值的LLR為0,則所述資料位元值為1的可能性和所述資料位元值為0的可能性是相同的。In this embodiment, the
根據檢查矩陣的子矩陣的預設維度值(Z),解碼控制器581將多個變量分組為多個變量群組。例如,假設預設維度值為256,並且資料位元值的數目為18432。通過初始化,可獲得對應於18432個資料位元值的18432個變量(初始變量),並且18432個初始變量將被分組至72個初始變量群組 (例如,18432/256 = 72)。According to the preset dimension value (Z) of the sub-matrix of the inspection matrix, the
檢查節點電路583用以對多個變量群組的多個層執行極值搜索操作,以找到對應每個層的多個最小值(極值)。更具體地,在初始化之後,解碼控制器581將初始變量群組發送到置換電路585,以根據檢查矩陣對這些初始變量群組執行移位操作,以獲得多個已移位變量群組。在移位操作之後,檢查節點電路583對多個已移位變量群組的多個層執行極值搜索操作,以找到與已移位變量群組的每個層相對應的多個最小值(極值)。The
變量節點電路584用以將多個最小值加到移位變量群組的各層,以獲得多個檢查變量群組。The
置換電路585用以對每個變量群組的多個輸入變量執行移位操作,以根據檢查矩陣輸出每個已移位變量群組的多個已移位變量。The
校驗子計算電路586用以根據檢查矩陣分別對檢查變量群組依次進行校驗子計算操作,以得到多個臨時校驗子和對應目標碼字的最終校驗子。The
終止電路587,用以根據對應目標碼字的最新獲得的最終校驗子來確定是否結束對當前目標碼字所執行的解碼過程。更具體地,終止電路587判斷最終校驗子中的多個值是否皆為零(即,“0”)。如果最終校驗子中的值全部為零,則終止電路587將目標碼字判定為正確,並且終止電路587指示解碼控制器581終止整個解碼過程並輸出最終所解碼的目標碼字(解碼過程的當前迭代操作結束,並且不會執行下一個迭代操作);如果最終校驗子中的值不全為零(即,包括一個或多個“1”),則終止電路587將目標碼字判定為不正確,並且終止電路587指示解碼控制器581結束解碼過程的當前迭代操作,並執行下一個迭代操作。換句話說,終止電路587可以根據每次獲得的最新的最終校驗子來判斷是否終止整個解碼操作。另一方面,終止電路587可以響應於所執行的迭代解碼操作的數量(次數)超過預設閾值而終止整個解碼操作。The
奇偶檢查矩陣是由M*N個奇偶檢查子矩陣(也稱為子矩陣)組成的矩陣。Z是奇偶檢查矩陣的奇偶檢查子矩陣的矩陣大小(預設維度值)(例如,奇偶檢查子矩陣是大小為ZⅹZ的矩陣),並且資料位元值組中的資料位元值的總數目是Z。資料位元值包括位元值“0”和位元值“1”。The parity check matrix is a matrix composed of M*N parity check sub-matrices (also called sub-matrices). Z is the matrix size (preset dimension value) of the parity check sub-matrix of the parity check matrix (for example, the parity check sub-matrix is a matrix of size ZⅹZ), and the total number of data bit values in the data bit value group is Z. The data bit value includes a bit value "0" and a bit value "1".
圖5D是根據本發明的一實施例所繪示的解碼器設計方法的流程圖。請參照圖5D,在步驟S511中,將可複寫式非揮發性記憶體模組的實體頁面的大小辨識為頁面大小,其中實體頁面用以儲存多個碼字。接著,在步驟S512中,根據實體頁面中的多個碼字的數量和所述頁面大小,獲取每個碼字的長度作為碼字長度。例如,假設每個實體頁面的大小是18432位元組,並且每個實體頁面用以儲存8個碼字。因此,碼字長度將是2304(即,18432/8)位元組。換句話說,所讀取的目標碼字的碼字長度為18432個位元(2304*8=18432)。5D is a flowchart of a decoder design method according to an embodiment of the invention. Referring to FIG. 5D, in step S511, the size of the physical page of the rewritable non-volatile memory module is recognized as the page size, where the physical page is used to store multiple codewords. Next, in step S512, according to the number of multiple codewords in the physical page and the page size, the length of each codeword is acquired as the codeword length. For example, suppose that the size of each physical page is 18432 bytes, and each physical page is used to store 8 codewords. Therefore, the codeword length will be 2304 (ie, 18432/8) bytes. In other words, the codeword length of the read target codeword is 18432 bits (2304*8=18432).
接著,在步驟S513中,辨識QC-LDPC解碼器的預定檢查矩陣,其中檢查矩陣包括MⅹN個子矩陣,其中每個子矩陣是ZⅹZ矩陣,其中Z是預設維度值,每個子矩陣的預設維度值是經由將碼字長度除以N所獲得的商值。M是由QC-LDPC解碼器的製造商設置的預定值(正整數)。繼續前述示例,進一步假設檢查矩陣是8×72矩陣(即,M = 8,並且N = 72)。 因此,校驗矩陣的每個子矩陣的預設維度值是256(即,Z = 18432/72 = 256)。Next, in step S513, a predetermined check matrix of the QC-LDPC decoder is identified, where the check matrix includes MⅹN sub-matrices, where each sub-matrix is a ZⅹZ matrix, where Z is a preset dimension value, and a preset dimension value of each sub-matrix Is the quotient obtained by dividing the codeword length by N. M is a predetermined value (positive integer) set by the manufacturer of the QC-LDPC decoder. Continuing the foregoing example, it is further assumed that the check matrix is an 8×72 matrix (ie, M=8, and N=72). Therefore, the preset dimension value of each sub-matrix of the check matrix is 256 (ie, Z = 18432/72 = 256).
接著,在步驟S514中,根據所述預設維度值來計算一第一數值,並且根據所述第一數值、所述預設維度值和所述檢查矩陣的移位類型識別第一置換網路,其中所述第一置換網路包括依序排列的多個第一置換層,所述第一置換層中的每一個第一置換層具有相同數量的第一節點,其中第一置換層的數量由第一數值所設置,並且每個第一置換層的第一節點的數量由預設維度值所設置,其中所述多個第一置換層中的一個第一置換層的每一個第一節點連接至下一個第一置換層的一對第一節點。Next, in step S514, a first value is calculated according to the preset dimension value, and a first permutation network is identified according to the first value, the preset dimension value and the shift type of the check matrix , Wherein the first replacement network includes a plurality of first replacement layers arranged in sequence, each of the first replacement layers in the first replacement layer has the same number of first nodes, wherein the number of first replacement layers Set by a first numerical value, and the number of first nodes of each first replacement layer is set by a preset dimension value, wherein each first node of a first replacement layer of the plurality of first replacement layers A pair of first nodes connected to the next first replacement layer.
更具體地,第一數值(在爾後的計算公式中也表示為“A”)是Log2 (Z)的計算結果(例如,前述示例的第一數值將是Log2 (256)= 8)。在一實施例中,第二數值(在下文中計算公式中也稱為“B”)是經由對第一數值減去1來獲得的(如,8-1=7)。爾後,所述第二數值可用以表示第二置換網路中的所有的第二置換層的總數量。More specifically, the first value (also expressed as "A" in the subsequent calculation formula) is the calculation result of Log 2 (Z) (for example, the first value of the foregoing example will be Log 2 (256) = 8). In one embodiment, the second value (also referred to as "B" in the calculation formula below) is obtained by subtracting 1 from the first value (eg, 8-1=7). Thereafter, the second value can be used to represent the total number of all second replacement layers in the second replacement network.
圖5E是根據本發明的一實施例所繪示的解碼器的置換電路的第一置換網路的示意圖。參考圖5E,為了便於說明第一置換網路的體系結構,假設圖5E中的例子的檢查矩陣具有128個子矩陣的4×36矩陣(例如,M = 4且N = 36),碼字長度是288位元,並且預設維度值是8(例如,288/36 = 8)(步驟S513)。因此,第一數值將是3(Log2 (8)= 3)(步驟S514)。 第一置換網路中的多個第一置換層的數量由第一數值(等於第一數值)來決定,並且每個第一置換層的多個節點的數量是相同的,並且所述多個節點的所述數量將由預設維度值所設置(等於預設維度值)。5E is a schematic diagram of a first replacement network of the replacement circuit of the decoder according to an embodiment of the invention. Referring to FIG. 5E, to facilitate the description of the architecture of the first permutation network, it is assumed that the check matrix of the example in FIG. 5E has a 4×36 matrix of 128 sub-matrices (for example, M=4 and N=36), and the codeword length is 288 bits, and the preset dimension value is 8 (for example, 288/36 = 8) (step S513). Therefore, the first value will be 3 (Log 2 (8)=3) (step S514). The number of multiple first replacement layers in the first replacement network is determined by a first value (equal to the first value), and the number of multiple nodes of each first replacement layer is the same, and the multiple The number of nodes will be set by the preset dimension value (equal to the preset dimension value).
舉例來說,第一置換網路5851'具有3個第一置換層5851'(0)至5851'(2),並且第一置換層5851'(0)至5851'(2)中的每一個第一置換層皆具有8個第一節點(例如,第一置換層5851'(0)具有8個第一節點590'(1)至590'(8);第一置換層5851'(1)具有8個第一節點591'(1)至591'( 8);第一置換層5851'(2)具有8個第一節點592'(1)至592'(8))。應當注意的是,一個第一置換層的一個節點與下一個第一置換層的節點之間的連接關係被設置用於連接輸入節點(與輸入端相連接的節點)至多個輸出節點(與輸出端相連接的節點),其中輸入節點的順序和所連接的輸出節點之一的順序之間的差異可以被表示為三種移位類型中的一種。所述三種移位類型包括一般移位類型,偶數移位類型和奇數移位類型。例如,以第一節點590'(1)為例,第一節點590'(1)是第一置換網路中的輸入節點,輸入節點590'(1)的順序為“1”,第一節點590'(1)連接到4個輸出節點592'(1),592'(3),592'(5)和592'(7),其中輸出節點592'(1)的順序是“1“; 輸出節點592'(3)的順序為“3”; 輸出節點592'(5)的順序為“5”; 輸出節點592'(7)的順序是“7”。 輸入節點590'(1)的順序與輸出節點592'(1)的順序之間的差值為0; 輸入節點590'(1)的順序與輸出節點592'(3)的順序之間的差值為2; 輸入節點590'(1)的順序與輸出節點592'(5)的順序之間的差值為4; 輸入節點590'(1)的順序與輸出節點592'(7)的順序之間的差異是6。For example, the first replacement network 5851' has three first replacement layers 5851'(0) to 5851'(2), and each of the first replacement layers 5851'(0) to 5851'(2) The first replacement layer has 8 first nodes (for example, the first replacement layer 5851'(0) has 8 first nodes 590'(1) to 590'(8); the first replacement layer 5851'(1) There are 8 first nodes 591'(1) to 591'(8); the first replacement layer 5851'(2) has 8 first nodes 592'(1) to 592'(8)). It should be noted that the connection relationship between a node of a first replacement layer and a node of the next first replacement layer is set to connect an input node (a node connected to an input terminal) to multiple output nodes (and output End-connected node), where the difference between the order of the input nodes and the order of one of the connected output nodes can be expressed as one of the three shift types. The three types of shifts include general shift types, even shift types, and odd shift types. For example, taking the first node 590'(1) as an example, the first node 590'(1) is the input node in the first replacement network, the order of the input node 590'(1) is "1", the first node 590'(1) is connected to 4 output nodes 592'(1), 592'(3), 592'(5) and 592'(7), where the order of output nodes 592'(1) is "1"; The order of output node 592'(3) is "3"; the order of output node 592'(5) is "5"; the order of output node 592'(7) is "7". The difference between the order of input node 590'(1) and the order of output node 592'(1) is 0; the difference between the order of input node 590'(1) and the order of output node 592'(3) The value is 2; the difference between the order of input node 590' (1) and the order of output node 592' (5) is 4; the order of input node 590' (1) and the order of output node 592' (7) The difference between them is 6.
換句話說,一個輸入節點590'(1)的順序與連接的輸出節點592'(1),592'(3),592'(5)和592'(7)的順序之間的差異都是偶數值(即:0,2,4,6),因此,在這個例子中,輸入節點的順序和連接的輸出節點之一的順序之間的差異可以被表徵(歸類)為偶數移位類型。因此,第一置換網路5851'將被識別為對應於QC-LDPC解碼器的偶數移位類型校驗矩陣的第一置換網路。此外,第一置換網路將以類似的方式被識別為對應於“奇數”移位類型校驗矩陣,辨識的細節相似於上述方法,省略於此。另外,在另一個第一置換網路中,如果一個輸入節點的順序與所連接的輸出節點的順序之間的差異可以形成諸如“0,1,2,...,Z”的序列,則將識別該第一置換網路為對應於一般移位類型校驗矩陣。關於不同移位類型校驗矩陣的細節將下面的圖14A和14B進行解釋。In other words, the difference between the order of an input node 590'(1) and the order of connected output nodes 592'(1), 592'(3), 592'(5), and 592'(7) Even values (ie: 0, 2, 4, 6), therefore, in this example, the difference between the order of the input nodes and the order of one of the connected output nodes can be characterized (categorized) as an even shift type . Therefore, the first permutation network 5851' will be recognized as the first permutation network corresponding to the even shift type check matrix of the QC-LDPC decoder. In addition, the first permutation network will be identified in a similar manner as corresponding to the "odd" shift type check matrix, and the details of the identification are similar to the above-mentioned methods and are omitted here. In addition, in another first replacement network, if the difference between the order of one input node and the order of connected output nodes can form a sequence such as "0,1,2,...,Z", then The first permutation network will be identified as a check matrix corresponding to the general shift type. Details about the check matrix of different shift types will be explained below in FIGS. 14A and 14B.
此外,應當注意的是,如圖5E所示,第一置換層之一的每個第一節點連接到下一個第一置換層中的一對第一節點。例如,由於第一置換層5851'(1)佈置在第一置換層5851'(0)之後(多個第一置換層中的第一置換層5851'(1)是第一置換層5851'(0)的下一個置換層),第一節點590'(1)連接到一對第一節點591'(1)和591'(5);第一節點590'(2)連接到一對第一節點591'(2)和591'(6);第一節點590'(3)連接到一對第一節點591'(3)和591'(7);第一節點590'(4)連接到一對第一節點591'(4)和591'(8);第一節點590'(5)連接到一對第一節點591'(1)和591'(5);第一節點590'(6)連接到一對第一節點591'(2)和591'(6);第一節點590'(7)連接到一對第一節點591'(3)和591'(7);第一節點590'(8)連接到一對第一節點591'(4)和591'(8)。輸入到一個第一置換層的第一節點的變量的位元值將被輸入(發送)到連接到所述一個第一置換層的下一個置換層中的所述第一節點對中的被選擇的一個第一節點。例如,根據解碼控制器581對設置於第一節點590'(1)上的選擇器所發出的選擇指令,輸入到第一節點590'(1)的位元值將被發送到第一節點591'(1)或第一節點591'(5)。Furthermore, it should be noted that, as shown in FIG. 5E, each first node of one of the first replacement layers is connected to a pair of first nodes in the next first replacement layer. For example, since the first replacement layer 5851'(1) is arranged after the first replacement layer 5851'(0) (the first replacement layer 5851'(1) among the plurality of first replacement layers is the first replacement layer 5851'( 0) The next replacement layer), the first node 590' (1) is connected to a pair of first nodes 591' (1) and 591' (5); the first node 590' (2) is connected to a pair of first Nodes 591'(2) and 591'(6); the first node 590'(3) is connected to a pair of first nodes 591'(3) and 591'(7); the first node 590'(4) is connected to A pair of first nodes 591'(4) and 591'(8); a first node 590'(5) is connected to a pair of first nodes 591'(1) and 591'(5); a first node 590'( 6) Connected to a pair of first nodes 591'(2) and 591'(6); the first node 590'(7) is connected to a pair of first nodes 591'(3) and 591'(7); the first Node 590'(8) is connected to a pair of first nodes 591'(4) and 591'(8). The bit value of the variable input to the first node of a first permutation layer will be input (sent) to the selected one of the first node pairs in the next permutation layer connected to the one first permutation layer One of the first nodes. For example, according to the selection instruction issued by the
接著,在步驟S515中,根據所述檢查矩陣的所述移位類型辨識所述第一置換網路的所述多個第一置換層中的目標第一置換層,並經由從所述第一置換網路中去除所述目標第一置換層來建構第二置換網路。Next, in step S515, the target first replacement layer among the plurality of first replacement layers of the first replacement network is identified according to the shift type of the check matrix, and the The target first replacement layer is removed from the replacement network to construct a second replacement network.
例如,參考圖5E,在本實施例中,將根據校驗矩陣的移位類型識別第一置換網路的所有第一置換層中的目標層(也稱為目標第一置換層)。更詳細地,假設在檢查矩陣是偶數類型的情況下,所述多個第一置換層的最後一個第一置換層5851'(2)將被識別為目標第一置換層。然後,為了建構第二置換網路,將從第一置換網路中移除所識別的目標第一置換層。換句話說,在從第一置換網路5851'移除目標第一置換層5851'(2)之後,原始第一置換網路5851'的剩餘第一置換層5851'(0)至5851'(1)將變為第二置換層5851(0)和5851(1),以形成第二置換網路5851(如圖5F所示)。並且,在包含第二置換網路5851的置換電路585中,根據第一置換層5851'(1)中的第一節點和目標第一置換層5851'(2)中的第一節點的連接關係,將輸出端Y1至Y8替換所述目標第一置換層5851'(2)以連接到第二置換層5851(1)。For example, referring to FIG. 5E, in this embodiment, a target layer (also referred to as a target first replacement layer) among all first replacement layers of the first replacement network will be identified according to the shift type of the check matrix. In more detail, it is assumed that in the case where the check matrix is an even type, the last first replacement layer 5851'(2) of the plurality of first replacement layers will be identified as the target first replacement layer. Then, in order to construct the second replacement network, the identified target first replacement layer will be removed from the first replacement network. In other words, after removing the target first replacement layer 5851'(2) from the first replacement network 5851', the remaining first replacement layers 5851'(0) to 5851' of the original first replacement network 5851'( 1) The second replacement layers 5851(0) and 5851(1) will become the second replacement network 5851 (as shown in FIG. 5F). In addition, in the
圖5F是根據本發明的一實施例所繪示的解碼器的置換電路的第二置換網路的示意圖。參考圖5F,所建構的第二置換網路5851包括2個(如,第二數值(B)是2)第二置換層5851(0)(從第一置換層5851'(0)所轉換)和5851(1)(從第一置換層5851'(1)所轉換),其中8個(例如,預設維度值為8)第二節點590(1)至590(8)(從第一節點590'(1)至590'(8)所轉換)被設置在第二置換層5851(0)上,並且另外的8個第二節點591(1)至591(8)(從第一節點591'(1)至591'(8)所轉換)被設置在第二置換層5851(1)上。5F is a schematic diagram of a second replacement network of the replacement circuit of the decoder according to an embodiment of the invention. Referring to FIG. 5F, the constructed
請回到圖5D,在步驟S516中,設置多個選擇器於所述置換電路的所述第二置換網路的多個第二節點上,並且根據所述第二置換網路將多條路由線設置到所述置換電路中以連接所述多個選擇器,其中所述多個選擇器更分別連接至所述QC-LDPC解碼器的解碼控制器,其中所述解碼控制器用以控制所述選擇器來將對應一目標碼字的多個第一變量群組移位成為多個第二變量群組,其中所述多個第二變量群組根據對應所述多個第一變量群組與所述多個第二變量群組的多個目標偏移量分別被移位,其中所述多個目標偏移量是根據所述檢查矩陣所辨識的。Please return to FIG. 5D. In step S516, multiple selectors are provided on multiple second nodes of the second replacement network of the replacement circuit, and multiple routes are routed according to the second replacement network A line is provided in the replacement circuit to connect the plurality of selectors, wherein the plurality of selectors are respectively connected to a decoding controller of the QC-LDPC decoder, wherein the decoding controller is used to control the A selector to shift a plurality of first variable groups corresponding to a target codeword into a plurality of second variable groups, wherein the plurality of second variable groups correspond to the plurality of first variable groups and The multiple target offsets of the multiple second variable groups are respectively shifted, wherein the multiple target offsets are identified according to the inspection matrix.
具體來說,所提供的置換電路由所建構的第二置換網路所形成,而不是由第一置換網路所形成。所建構的第二置換網路將被設置在置換電路中的多個輸入端和多個輸出端之間。更詳細地,第二置換網路的多個第二置換層中的第一個第二置換層中的每個第二節點連接到置換電路的多個輸入端,並且多個第二置換層中的最後一個第二置換層中的每個第二節點連接至置換電路的多個輸出端中的兩個。Specifically, the provided replacement circuit is formed by the constructed second replacement network instead of the first replacement network. The constructed second replacement network will be placed between multiple input terminals and multiple output terminals in the replacement circuit. In more detail, each second node in the first second replacement layer of the plurality of second replacement layers of the second replacement network is connected to a plurality of input terminals of the replacement circuit, and in the plurality of second replacement layers Each second node in the last second permutation layer of is connected to two of the multiple output terminals of the permutation circuit.
圖5G是根據本發明的一實施例所繪示的解碼器的置換電路的示意圖。請參考圖5G,繼續圖5F中的例子。如圖5G所示,第二置換網路5851佈置在多個輸入端X1至X8與多個輸出端Y1至Y8之間。例如,如圖5G所示,第二置換層5851(0)是置換網路5851的多個第二置換層5851(0)至5851(1)中的第一個置換層,第二置換層5851(1)是置換網路5851的多個第二置換層5851(0)至5851(1)中的最後一個置換層。第二節點590(1)至590(8)分別連接到輸入端X1至X8,第二節點591(1)連接到輸出端Y1和Y3; 第二節點591(2)連接到輸出端Y2和Y4; 第二節點591(3)連接到輸出端Y1和Y3; 第二節點591(4)連接到輸出端Y2和Y4; 第二節點591(5)連接到輸出端Y5和Y7; 第二節點591(6)連接到輸出端Y6和Y8; 第二節點591(7)連接到輸出端Y7和Y5; 第二節點591(8)連接到輸出端Y6和Y8。5G is a schematic diagram of a replacement circuit of a decoder according to an embodiment of the invention. Please refer to FIG. 5G to continue the example in FIG. 5F. As shown in FIG. 5G, the
此外,在本實施例中,根據所建構的置換網路的架構,置換電路的主要硬件元件,選擇器,將被設置於置換電路中。首先,將根據變量的特徵來決定一個節點上的一組選擇器的數量。更具體地,一組選擇器設置在置換網路的每個節點上,並且每個節點上的每組選擇器的數量由與變量相關的預設精細度決定。如前所述,預設精細度用於設置與變量對應的位元值的數量。當變量輸入到一個節點時,該一個節點上的一組選擇器將所述被輸入的變量的每個位元值發送(移位)到下一個置換層的另一個節點上的另一組選擇器,因此,一個節點上的一組選擇器的數量需要等於一個變量的位元值的數量(即,一個節點上的多個選擇器的數量被設定為等於預設精細度)。因此,可以根據預設維度值,預設精細度和第二數值來確定置換電路的置換網路的全部的節點中的全部的選擇器的總數目。更詳細地,置換電路的置換網路的全部節點中的全部的選擇器的總數量是經由(Z*B*F)的計算結果來設定的,其中Z是預設維度值,B是第二數值,F是預設精細度。In addition, in this embodiment, according to the structure of the constructed replacement network, the main hardware components of the replacement circuit, the selector, will be set in the replacement circuit. First, the number of selectors on a node will be determined according to the characteristics of the variables. More specifically, a group of selectors is provided on each node of the replacement network, and the number of selectors in each group on each node is determined by the preset fineness associated with the variables. As mentioned before, the preset fineness is used to set the number of bit values corresponding to the variables. When a variable is input to a node, a set of selectors on the one node sends (shifts) each bit value of the input variable to another set of selections on another node in the next replacement layer Therefore, the number of selectors on a node needs to be equal to the number of bit values of a variable (that is, the number of multiple selectors on a node is set equal to the preset fineness). Therefore, the total number of all selectors in all the nodes of the replacement network of the replacement circuit can be determined according to the preset dimension value, the preset fineness, and the second value. In more detail, the total number of all selectors in all nodes of the replacement network of the replacement circuit is set via the calculation result of (Z*B*F), where Z is the default dimension value and B is the second Numerical value, F is preset fineness.
另一方面,配置為連接到置換電路中的硬件元件的路由線也是另一個重要的硬體元件,並且路由線的數量將由置換網路的每個置換層中的選擇器的數量來決定。On the other hand, the routing line configured to connect to the hardware element in the replacement circuit is another important hardware component, and the number of routing lines will be determined by the number of selectors in each replacement layer of the replacement network.
圖17是根據本發明的一實施例所繪示的在所提供的置換電路的第二置換網路中的多個選擇器與連接至所述多個選擇器的路由線的連接關係的示意圖。17 is a schematic diagram illustrating a connection relationship between a plurality of selectors in the second replacement network of the provided replacement circuit and a routing line connected to the plurality of selectors according to an embodiment of the present invention.
請參照圖17,以第二置換網路的一部分為例,對於第二置換網路5851的第二個置換層5851(0)的節點上的每個選擇器,第一個第二置換層中的一個選擇器(例如,節點590(1)上的選擇器)總共需要四條路由線,包括:(1)一條路由線(例如,路由線IW_590(1)),用於連接輸入端X1和在所述第一個第二置換層的節點590(1)上的所述選擇器; (2)一條路由線(例如,路由線CW_590(1)),用於連接解碼控制器581和第一個第二置換層的節點590(1)上的所述選擇器; (3)兩條路由線(例如,路由線OW1_590(1)和OW2_590(1)),用於分別將第一個第二置換層的節點590(1)上的所述選擇器連接到兩個節點上的兩個選擇器591(1)和591(5)。Referring to FIG. 17, taking a part of the second replacement network as an example, for each selector on the node of the second replacement layer 5851(0) of the
此外,對於第二置換網路5851的第一個第二置換層之外的其餘第二置換層(例如,第二置換層5851(1))的第二節點上的每個選擇器,所述另一個第二置換層5851(1)的選擇器(例如,第二節點591(1)上的選擇器)總共需要三條路由線,包括:(1)一條路由線(例如,路由線CW_591(1)),用於連接解碼控制器581與第二置換層5851(1)的節點591(1)上的所述選擇器;(2)兩條路由線(例如,路由線OW1_591(1)和OW2_591(1)),用於分別將第二置換層5851(1)的節點591(1)上的所述選擇器連接到置換電路的兩個輸出端Y1與Y3(注意:如果在第二置換層5851(1)之後存在一個第二置換層,則分別連接至第二置換層5851(1)的所述下一個第二置換層的兩個節點上的兩個選擇器)。In addition, for each selector on the second node of the remaining second replacement layer (for example, the second replacement layer 5851(1)) other than the first second replacement layer of the
簡而言之,連接到第二置換網路的第一個第二置換層中的每個選擇器的路由線的數量是4,連接到第二置換網路的其餘第二置換層中的每個選擇器的路由線的數量是3。在本實施例中,根據第一個第二置換層中的選擇器的數量和其他第二置換層中的選擇器的數量以決定用於連接置換電路中的全部選擇器的全部路由線的數量。換句話說,根據預設維度值,預設精細度和第二數值計算對應第二置換網路的全部選擇器的全部路由線的總數量。更詳細地,所有路由線的總數量可經由(Z*F+3*T)的計算結果來設定,並且T是第二置換網路的所有選擇器的數量(即,T = Z*B*F)。In short, the number of routing lines connected to each selector in the first second replacement layer of the second replacement network is 4, and each of the remaining second replacement layers connected to the second replacement network The number of routing lines for each selector is 3. In this embodiment, the number of all routing lines for connecting all selectors in the replacement circuit is determined according to the number of selectors in the first second replacement layer and the number of selectors in other second replacement layers . In other words, according to the preset dimension value, the preset fineness and the second value, the total number of all routing lines corresponding to all the selectors of the second replacement network is calculated. In more detail, the total number of all routing lines can be set via the calculation result of (Z*F+3*T), and T is the number of all selectors of the second replacement network (ie, T = Z*B* F).
採用圖5G中的整個置換電路585為例子,其中所輸入的變量的位元總量(Preset Fineness value,F)等於5;子矩陣的預設維度值(Z)等於8; 置換層的數量(第二數值,B)等於2。置換網路的全部選擇器的數量將由(Z*B*F)來決定,其結果為80(即,T=80); 以及全部選擇器的全部路由線的總數量(以下也稱為“W”)將由(Z*F+3*T)來決定,其結果為280。Taking the
在本實施例中,在置換電路的所有選擇器的量(T),置換電路的所有相應路由線的量(W)以及選擇器,解碼控制器,輸入端和輸出端之間的連接關係(如,經由路由線所實施的連接關係)被決定之後,T個選擇器和W個路由線將根據所建構的第二置換網路被設置到置換電路中,從而完成置換電路的設計。In this embodiment, the amount (T) of all selectors in the replacement circuit, the amount (W) of all corresponding routing lines in the replacement circuit, and the connection relationship between the selector, decoding controller, input terminal and output terminal ( For example, after the connection relationship implemented via the routing line is determined, T selectors and W routing lines will be set into the replacement circuit according to the constructed second replacement network, thereby completing the design of the replacement circuit.
應該提到的是,選擇器例如是具有一個輸入端子,兩個輸出端子和一個控制端子的基本開關。控制端子電電性連接至解碼控制器,以便從解碼控制器接收選擇指令(也稱為選擇信號),其中選擇器可以根據選擇指令將輸入端子連接到兩個輸出端子之一,以使輸入到輸入端的位元值將經由被選擇指令所選擇的兩個輸出端的其中之一輸出。選擇器的輸入端子經由路由線電性連接至置換電路的輸入端,或者經由路由線電性連接至選擇器所屬的置換層之前的另一置換層中的選擇器的輸出端子。選擇器的兩個輸出端子通過路由線電性連接至置換電路的兩個輸出端,或者通過路由線分別電性連接至下一個置換層中不同節點上的兩個選擇器的輸入端子。It should be mentioned that the selector is, for example, a basic switch having one input terminal, two output terminals and one control terminal. The control terminal is electrically connected to the decoding controller to receive a selection command (also called a selection signal) from the decoding controller, where the selector can connect the input terminal to one of the two output terminals according to the selection command, so that the input to the input The bit value of the terminal will be output via one of the two output terminals selected by the selection instruction. The input terminal of the selector is electrically connected to the input terminal of the replacement circuit via a routing line, or is electrically connected to the output terminal of the selector in another replacement layer before the replacement layer to which the selector belongs via a routing line. The two output terminals of the selector are electrically connected to the two output terminals of the replacement circuit through a routing line, or are respectively electrically connected to the input terminals of two selectors on different nodes in the next replacement layer through the routing line.
此外,如上所述,解碼控制器581還被配置為通過向選擇器發出選擇指令來控制選擇器將對應於目標碼字的多個第一變量群組移位為多個第二變量群組,並且“將對應所述目標碼字的多個第一變量群組移位為多個第二變量群組”的步驟包括以下步驟(1)至(3)。In addition, as described above, the
步驟(1),解碼控制器分別將第一變量群組之一的所有變量輸入到不同的輸入端,其中所有輸入的變量分別經由所有的輸入端被傳輸至第一個置換層的所有節點。In step (1), the decoding controller inputs all variables of one of the first variable groups to different input terminals, where all input variables are transmitted to all nodes of the first replacement layer via all input terminals, respectively.
接著,在步驟(2)中,由置換網路中的選擇器經由對應多個第一變量群組的其中之一的一個移位差值對所有輸入的變量進行移位。Next, in step (2), the selector in the replacement network shifts all input variables via a shift difference corresponding to one of the plurality of first variable groups.
接著,在步驟(3)中,分別輸出來自不同輸出端的所有移位變量作為對應於第一變量群組之一的第二變量群組,其中所有移位變量分別由選擇器在最後一個置換層的所有節點上傳輸到輸出端,其中所述一個移位差值由對應於所述第一變量群組之一的第一目標偏移量和對應於所述第二變量群組的第二目標偏移量之間的差值來決定,其中第一目標偏移量是根據預定檢查矩陣的多個子矩陣中對應所述第一變量群組之一的第一子矩陣來被辨識的,並且所述第二目標偏移量是根據預定檢查矩陣的多個子矩陣中對應所述第二變量群組的第二子矩陣來被辨識的。Next, in step (3), all shift variables from different output terminals are output as the second variable group corresponding to one of the first variable groups, where all shift variables are respectively replaced by the selector in the last replacement layer Is transmitted to the output end on all nodes of, where the one shift difference is determined by the first target offset corresponding to one of the first variable groups and the second target corresponding to the second variable group The difference between the offsets is determined, where the first target offset is identified according to a first sub-matrix corresponding to one of the first variable groups among a plurality of sub-matrices of the predetermined inspection matrix, and the The second target offset is identified according to a second sub-matrix corresponding to the second variable group among a plurality of sub-matrices of a predetermined inspection matrix.
舉例來說,請再參考圖5G,例如,在本實施例中,由解碼控制器輸入到置換電路585的輸入端X1至X8的變量群組V(1)被稱為第一變量群組,第一變量群組V(1)的變量V(1)_1到V(1)_8按預定順序排列(例如,如圖5G所示,變量V(1)_1是第一個變量,變量V(1)_8是最後一個變量)。變量V(1)_1至V(1)_8根據其預定順序分別輸入到輸入端X1至X8(步驟(1))。輸入端X1至X8將變量V(1)_1至V(1)_8傳送到置換電路585的第一個第二置換層5851(1)。此外,由置換電路585根據移位差“2”對所輸入的第一變量群組V(1)進行移位而獲得已移位變量群組V(1)'(步驟2),並將變量群組V(1)'從輸出端Y1至Y8輸出,其中利用預定順序(也是X1至X8,或Y1至Y8的順序),從輸出端Y1至Y8輸出已移位變量群組V(1)'的變量V(1)_7至V(1)_6(步驟3)。已移位變量組V1(1)'可以被稱為具有根據預定順序排列的變量V(2)_1至V(2)_8的第二變量組V(2),其中變量V(2)_1到V(2)_8實際上等於已移位變量組V(1)'的變量V(1)_7到V(1)_6。應當注意,輸入到具有預定順序“1”的輸入端X1的V(1)_1從具有預定順序“3”的輸出端Y3被輸出。換句話說,位元V(1)_1從順序“1”移位到順序“3”,即,位元V(1)被移位了“2”(3-1=2)移位差值。下面將利用圖14A和14B解釋關於檢查矩陣的移位差值和移位類型的更多細節。For example, please refer to FIG. 5G again. For example, in this embodiment, the variable group V(1) input by the decoding controller to the input terminals X1 to X8 of the
圖14是根據本發明的一實施例所繪示的經由具有對應偶數移位類型檢查矩陣的所提供的第二置換網路的置換電路所執行的變量群組的移位操作的示意圖。圖14B是根據本發明的一實施例所繪示的經由具有對應一般移位類型檢查矩陣的傳統置換網路的置換電路所執行的變量群組的移位操作的示意圖。14 is a schematic diagram of a shift operation of a variable group performed by a replacement circuit of a second replacement network provided with a check matrix corresponding to an even shift type according to an embodiment of the present invention. 14B is a schematic diagram of a shift operation of a variable group performed by a replacement circuit of a conventional replacement network with a check matrix corresponding to a general shift type according to an embodiment of the invention.
請參照圖14,假設經由解碼控制器581通過根據目標碼字的資料位元值查找解碼表來獲得初始變量組IV(1)至IV(N)中的所有變量。然而,本發明不限於此,例如,在一實施例中,目標碼字的資料位元值中的全部的“1”被轉換為“-Q”作為變量,並且目標碼字的資料位元值中的全部的“0”被轉換為“Q”作為變量。其中,Q是預定參數值。如此一來,可獲得多個轉換後的資料位元值作為變量。Referring to FIG. 14, it is assumed that all variables in the initial variable groups IV(1) to IV(N) are obtained through the
此外,假設檢查矩陣1400(其是M×N矩陣)包括子矩陣組(也稱為子矩陣層)1410(1)至1410(M)。每個子矩陣組1410(1)至1410(M)包括N個子矩陣。 在圖14A中,每個塊表示子矩陣,並且每個子矩陣的默認維度值是256(即,每個子矩陣是256×256的矩陣)。在圖14A中,每個子矩陣(即,每個塊)中的值是指對應於每個子矩陣的變量群組的目標偏移量。例如,在子矩陣組1410(1)的所標記的值108,118,28,......和118用以表示從多個初始第一變量群組IV(1)至IV(N)通過置換電路585所偏移的多個第二變量群組的目標偏移量。檢查矩陣的相同行的目標偏移量指示對應於同一列中的子矩陣的已移位變量群組從相同列的相同初始變量群組移位的偏移量。例如,具有目標偏移量“216”的變量群組是通過將初始變量組IV(2)移位偏移量“216”而獲得的變量群組(目標偏移量“216”是與IV(2)的偏移量)。此外,具有目標偏移量“216”的變量群組可以經由對具有目標偏移量“118”的已移位變量組移位一個移位差值“98” (216-118 = 98)來獲得的。因為,具有目標偏移量“118”的已移位變量組已經從初始變數群組被偏移了移位差值“118”。In addition, it is assumed that the inspection matrix 1400 (which is an M×N matrix) includes sub-matrix groups (also referred to as sub-matrix layers) 1410(1) to 1410(M). Each sub-matrix group 1410(1) to 1410(M) includes N sub-matrices. In FIG. 14A, each block represents a sub-matrix, and the default dimension value of each sub-matrix is 256 (that is, each sub-matrix is a 256×256 matrix). In FIG. 14A, the value in each sub-matrix (ie, each block) refers to the target offset of the variable group corresponding to each sub-matrix. For example, the labeled
換句話說,校驗矩陣的相同行的多個目標偏移量指示對應於同一行中的多個子矩陣的多個已移位變量群組從相同行的相同初始變量群組所移位的偏移量。 例如,目標偏移“108”,“120”,......,“240”的已移位變量群組可視為經由從檢查矩陣的第一行的相同的初始變量組IV(1)移位“108”, “120”,......,“240”移位差值所獲得的已移位變量群組。In other words, the multiple target offsets of the same row of the check matrix indicate the offsets of the shifted variable groups corresponding to the multiple sub-matrices in the same row from the same initial variable group of the same row Displacement. For example, the shifted variable group of target offsets "108", "120", ..., "240" can be viewed as the same initial variable group IV(1) from the first row of the check matrix Shifted by "108", "120", ..., "240" shifted variable group obtained by shifting the difference.
在本實施例中,初始變量群組的目標偏移量被預設為0。移位差值是對差值進行與置換網路大小(也稱為預設維度值,即Z)的模運算所獲得的值。所述差值是經由對第二變量群組的目標偏移(也稱為第二目標偏移量)減去第一變量群組的目標偏移(也稱為第一目標偏移量)所獲得的。例如,“(124)”是經由對差值進行與“256”的模運算(運算符號“mod”)所獲得的。所述差值是經由對“108”減去“240”得到的,即,“-132”。對“-132”進行與“256”的模運算的結果為“124”(-132 mod 256=124)。In this embodiment, the target offset of the initial variable group is preset to 0. The shift difference is the value obtained by performing a modular operation on the difference and replacing the size of the network (also called the default dimension value, or Z). The difference is obtained by subtracting the target offset of the first variable group (also called the first target offset) from the target offset of the second variable group (also called the second target offset) acquired. For example, “(124)” is obtained by performing a modulo operation (operation symbol “mod”) with “256” on the difference. The difference is obtained by subtracting "240" from "108", that is, "-132". The result of the modular operation of "-132" and "256" is "124" (-132
圖14A中的箭頭標記“à”表示移位的方向,箭頭標記處的標記“()”中的數字表示第一目標偏移量和第二目標偏移量之間的移位差值。例如,“IV(1)à108”表示初始變量群組中的所有變量被移位一個移位差值“108”(初始變量群組的目標偏移量為0),成為第二目標偏移量為“108”的第二變量群組;“108→120”表示第一目標偏移量為“108”的變量群組中的所有變量被移位一個移位差“12”(120-108=12),以變為第二目標偏移量為“120”的第二變量群組。應該提到的是,解碼控制器581根據由相應子矩陣的目標偏移量所確定的移位差值向選擇器發出選擇指令(選擇信號),使得置換電路585中的整個選擇器可以經由移位差值來移位所輸入的第一變量群組以輸出第二變量群組。The arrow mark “à” in FIG. 14A indicates the direction of shift, and the number in the mark “()” at the arrow mark indicates the shift difference between the first target offset and the second target offset. For example, "IV(1)à108" means that all variables in the initial variable group are shifted by a shift difference of "108" (the target offset of the initial variable group is 0), becoming the second target offset Is the second variable group of "108"; "108→120" means that all variables in the variable group with the first target offset of "108" are shifted by a shift difference of "12" (120-108= 12) to become the second variable group whose second target offset is "120". It should be mentioned that the
在本實施例中,通過預先確定(設計)QC-LDPC解碼器使用的檢查矩陣來設置與檢查矩陣的每個子矩陣相對應的所有的目標偏移量的值。具體來說,每個目標偏移量被設置在置換網路大小範圍內,其中置換網路大小範圍被設置為0到Z-1。此外,對應兩個目標偏移量之間的移位差值的值被設置在置換網路移位範圍內,並且移位差值會依據檢查矩陣的移位類型來被決定。In the present embodiment, the values of all target offsets corresponding to each sub-matrix of the inspection matrix are set by determining (designing) the inspection matrix used by the QC-LDPC decoder in advance. Specifically, each target offset is set within the replacement network size range, where the replacement network size range is set to 0 to Z-1. In addition, the value corresponding to the shift difference between the two target offsets is set within the shift range of the replacement network, and the shift difference will be determined according to the shift type of the check matrix.
更詳細地,如果校驗矩陣是偶數移位類型檢查矩陣,則將所有移位差中的每一個設置為0到(Z-1)範圍內的偶數值。例如,參考圖14A,對應於檢查矩陣的所有子矩陣的每個目標偏移量是在置換網路大小範圍內(即,0到255)的值,並且每個相應的移位差值是在置換網路大小範圍內的“偶數”值(置換網路移位範圍)。 然而,用於設計校驗矩陣的其他特徵不是本公開的主要概念,並且在此省略相應的細節。 在一些實施例中,對應於校驗矩陣的所有子矩陣中的若干子矩陣的目標偏移將被設置為空值(例如,對應的移位差將為0)。In more detail, if the check matrix is an even-shift type check matrix, each of all shift differences is set to an even value in the range of 0 to (Z-1). For example, referring to FIG. 14A, each target offset corresponding to all sub-matrices of the check matrix is a value within the size range of the replacement network (ie, 0 to 255), and each corresponding shift difference is Replace the "even" value within the range of the network size (replace the network shift range). However, other features for designing the check matrix are not the main concept of the present disclosure, and the corresponding details are omitted here. In some embodiments, the target offset of several sub-matrices corresponding to all the sub-matrices of the check matrix will be set to a null value (eg, the corresponding shift difference will be 0).
類似地,如果檢查矩陣是奇數移位類型檢查矩陣,則對應於檢查矩陣的所有子矩陣的每個目標偏移量是置換網路大小範圍內的值(即,0到Z-1), 並且每個相應的移位差值是置換網路大小範圍內的“奇數”值(即,0到(Z-1)內的奇數值)。Similarly, if the check matrix is an odd-shift type check matrix, then each target offset corresponding to all sub-matrices of the check matrix is a value within the range of the replacement network size (ie, 0 to Z-1), and Each corresponding shift difference is an "odd" value within the range of the replacement network size (ie, an odd value from 0 to (Z-1)).
應該提到的是,若對應於檢查矩陣的所有移位差是偶數,則檢查矩陣的移位類型是偶數移位類型,並且目標第一置換層是對應於偶數移位類型校驗矩陣的所識別的第一置換網路的多個第一置換層中的最後一個; 如果對應於檢查矩陣的所有移位差是奇數,則檢查矩陣的移位類型是奇數移位類型,並且目標第一置換層是對應於奇數移位類型校驗矩陣的所識別的第一置換網路的多個第一置換層中的最後一個。It should be mentioned that if all the shift differences corresponding to the check matrix are even, then the shift type of the check matrix is the even shift type, and the target first permutation layer is the position corresponding to the check matrix of the even shift type. The last one of the multiple first permutation layers of the identified first permutation network; if all the shift differences corresponding to the check matrix are odd, then the shift type of the check matrix is the odd shift type, and the target first permutation The layer is the last of the plurality of first replacement layers of the identified first replacement network corresponding to the odd-shift type check matrix.
參見圖14B,如果檢查矩陣是由現有技術設計的傳統檢查矩陣的一般移位類型矩陣,則對應於檢查矩陣的所有子矩陣的每個目標偏移量可以是置換網路大小範圍內的任意值(即, 如圖14B所示,每個相應的移位差值是置換網路大小範圍內的值(任何整數)(即,0到(Z-1)內的任意數值)。在此例子中,移位差值不會僅是偶數值(偶數移位類型)或僅是奇數值(奇數移位類型)。Referring to FIG. 14B, if the inspection matrix is a general shift type matrix of a conventional inspection matrix designed by the prior art, each target offset corresponding to all sub-matrices of the inspection matrix may be any value within the range of the replacement network size (That is, as shown in FIG. 14B, each corresponding shift difference is a value within the range of the replacement network (any integer) (ie, any value from 0 to (Z-1)). In this example , The shift difference will not be only even value (even shift type) or only odd value (odd shift type).
另外,參考圖14A,移位順序是從左到右,從上到下。例如,根據移位差值“109”,通過置換電路對初始變量群組IV(1)進行第一組移位操作,以獲得具有第二目標偏移量“108”的相應第二變量群組;接下來,根據移位差值“118”通過置換電路來移位初始變量群組IV(2),以便獲得具有第二目標偏移“118”的相應第二變量群組,依此類推,可從具有目標偏移0,0,0,...,0的(第一)初始變量組中獲得得具有對應於子矩陣組1410(1)的目標偏移108,118,28,...,118的第二變量群組。對應於子矩陣組1410(2)的變量群組將以相同的方式從對應於子矩陣組1410(1)的變量群組被移位,依此類推,可獲得對應於所有子矩陣的所有變量群組。在另一方面,對應於檢查矩陣的第一行子矩陣的變量群組皆是從第一行的初始變量組IV(1)被移位的,對應於檢查矩陣的第二行子矩陣的變量群組皆是從第二行的初始變量組IV(2)被移位的,以此類推。In addition, referring to FIG. 14A, the shift order is from left to right and from top to bottom. For example, according to the shift difference value "109", a first group shift operation is performed on the initial variable group IV(1) through a replacement circuit to obtain a corresponding second variable group having a second target offset "108" Next, the initial variable group IV(2) is shifted by the replacement circuit according to the shift difference value "118", so as to obtain the corresponding second variable group with the second target offset "118", and so on, The target offset 108,118,28,..., which corresponds to the sub-matrix group 1410(1), can be obtained from the (first) initial variable group with the target offset 0,0,0,...,0 118's second variable group. The variable group corresponding to the sub-matrix group 1410(2) will be shifted from the variable group corresponding to the sub-matrix group 1410(1) in the same way, and so on, all variables corresponding to all sub-matrices can be obtained Group. On the other hand, the variable groups corresponding to the sub-matrix of the first row of the inspection matrix are all shifted from the initial variable group IV(1) of the first row, corresponding to the variables of the sub-matrix of the second row of the inspection matrix The groups are all shifted from the initial variable group IV(2) in the second row, and so on.
以下將利用圖15,16A,16B與16C來說明所提供的解碼器設計方法和使用所述解碼器設計方法的解碼器的置換電路的改進。The improvement of the provided decoder design method and the replacement circuit of the decoder using the decoder design method will be described below using FIGS. 15, 16A, 16B, and 16C.
圖15是根據先前技術所繪示的解碼器的置換電路的傳統的置換網路的示意圖。圖16A是根據先前技術所繪示的對應一般移位類型檢查矩陣的傳統的置換網路移位範圍的示意圖。圖16B是根據本發明的一實施例所繪示的對應偶數移位類型檢查矩陣的所提供的置換網路移位範圍的示意圖。圖16C是根據本發明的一實施例所繪示的對應奇數移位類型檢查矩陣的所提供的置換網路移位範圍的示意圖。15 is a schematic diagram of a conventional replacement network of a replacement circuit of a decoder according to the prior art. FIG. 16A is a schematic diagram of a conventional displacement network shift range corresponding to a general shift type check matrix according to the prior art. 16B is a schematic diagram illustrating the displacement range of the replacement network provided by the check matrix corresponding to the even-shift type according to an embodiment of the invention. 16C is a schematic diagram illustrating the displacement range of the replacement network provided by the check matrix corresponding to the odd shift type according to an embodiment of the invention.
請參照圖15,圖5G中的所提供的置換電路585與圖15中的傳統的置換電路585'的差異在於其中的置換網路的架構是不同的。例如,如圖15所示,傳統置換電路的置換網路是不移除目標第一置換層的第一置換網路。例如,置換層5851'(0)是置換網路5851'的第一個置換層,置換層5851'(3)是置換網路5851'的最後一個置換層。節點590'(1)至590'(8)分別連接到輸入端X1到X8,節點592'(1)連接到輸出端Y1和Y2; 節點592'(2)連接到輸出端Y1和Y2; 節點592'(3)連接到輸出端Y3和Y4; 節點592'(4)連接到輸出端Y3和Y4; 節點592'(5)連接到輸出端Y5和Y6; 節點592'(6)連接到輸出端Y5和Y6; 節點592'(7)連接到輸出端Y7和Y8; 節點592'(8)連接到輸出端Y7和Y8。Please refer to FIG. 15. The difference between the
換句話說,置換網路架構5851和5851'之間的差異是置換層的量。在現有技術中,傳統置換網路5851'的置換層的數量由第一數值所設定。但是,所提供的置換電路的置換網路的置換層的數量是由第二數值(如,第一數值減1)所設定。換句話說,置換網路5851的置換層的總數量會小於為第一數值的置換網路5851'的置換層的總數量(相差一)。In other words, the difference between the
由於本實施例所提供的置換網路具有較少數量的置換層,所以所有置換層的節點上的所有選擇器的數量將相應地減少,並且連接到所有選擇器的相應路由線也將減少。因此,所有選擇器和路由線的硬件成本將大大降低,並且設置路由線的難度也會隨著路由線的減少而降低(而且,置換電路的整個硬件尺寸也會相應地減小)。此外,功耗也會降低,因為用於執行移位操作的選擇器減少並且所有路由線的總路由路徑也減少,需要提供的用於執行整個移位操作的功率將減少,使得置換電路的功耗相應地降低。此外,隨著置換電路的功耗降低,置換電路相應的發熱會減少,從而降低置換電路的處理溫度。Since the replacement network provided by this embodiment has a smaller number of replacement layers, the number of all selectors on the nodes of all replacement layers will be reduced accordingly, and the corresponding routing lines connected to all selectors will also be reduced. Therefore, the hardware cost of all selectors and routing lines will be greatly reduced, and the difficulty of setting routing lines will be reduced as routing lines are reduced (and the entire hardware size of the replacement circuit will be reduced accordingly). In addition, power consumption is also reduced because the number of selectors used to perform the shift operation is reduced and the total routing paths of all routing lines are also reduced. The power required to perform the entire shift operation will be reduced, making the power of the replacement circuit The consumption is reduced accordingly. In addition, as the power consumption of the replacement circuit decreases, the corresponding heat generation of the replacement circuit will decrease, thereby reducing the processing temperature of the replacement circuit.
參考圖16A和16B,對於現有技術的置換網路5851',輸入到端部X1的位元值可以被移位且從端部Y1到Y8被輸出,Y1到Y8的範圍是傳統的置換移位範圍。傳統的置換移位範圍也等於置換網路大小,使得傳統置換網路可以稱為全範圍置換網路。此外,由於傳統置換網路的移位差是置換網路移位範圍的任何值,因此置換網路移位範圍對應於“一般”移位類型檢查矩陣。16A and 16B, for the prior art permutation network 5851', the bit value input to the end X1 can be shifted and output from the end Y1 to Y8, the range of Y1 to Y8 is the traditional permutation shift range. The traditional replacement shift range is also equal to the replacement network size, so that the traditional replacement network can be called a full-range replacement network. In addition, since the shift difference of the conventional permutation network is any value of the permutation range of the permutation network, the permutation range of the permutation network corresponds to the "normal" shift type check matrix.
另一方面,關於所提供的置換網路,若輸入到末端X1的位元可以從一端Y1、Y3、Y5和Y7被移位和輸出(移位差值被設定為在置換網路大小範圍內的“偶數”,即,0、2、4、6),置換網路移位範圍對應於“偶數”移位類型檢查矩陣(如,圖16B所示)。On the other hand, regarding the provided replacement network, if the bits input to the end X1 can be shifted and output from one end Y1, Y3, Y5, and Y7 (the shift difference is set to be within the size of the replacement network "Even", ie, 0, 2, 4, 6), the displacement range of the replacement network corresponds to the "even" shift type check matrix (as shown in Fig. 16B).
此外,參照圖16C,關於所提供的置換網路,若輸入到末端X1的位元可以從一端Y2、Y4、Y6和Y8被移位和輸出(移位差值被設定為在置換網路大小範圍內的“奇數”,即,1、3、5、7),置換網路移位範圍對應於“奇數”移位類型檢查矩陣。In addition, referring to FIG. 16C, regarding the provided replacement network, if the bit input to the end X1 can be shifted and output from one end Y2, Y4, Y6, and Y8 (the shift difference is set to the size of the replacement network "Odd" in the range, ie, 1, 3, 5, 7), the displacement range of the replacement network corresponds to the "odd" shift type check matrix.
應當注意,檢查矩陣的移位類型還可以包括P倍數移位類型,其中“P”表示P倍數移位類型的所有移位差值是P的倍數(P可以設定為正整數),並且將移位差值設定為置換網路大小範圍0到Z-1內的P的倍數。並且,以與上述相同的方式根據P倍數移位類型檢查矩陣識別對應的第一置換網路及其連接關係。例如,假設Z = 8,P = 3,則輸入至輸入端X1的一個位元值將由所建構的第二置換網路從輸出端Y1,Y4和Y7之一被輸出(對應的移位差值為0、3與6)。換句話說,若對應於檢查矩陣的所有移位差是P的倍數,則檢查矩陣的移位類型是P倍數移位類型。此外,目標第一置換層是對應於P倍數移位類型校驗矩陣的所識別的第一置換網路的多個第一置換層中的最後一個。It should be noted that the shift type of the check matrix may also include a P multiple shift type, where "P" indicates that all shift differences of the P multiple shift type are multiples of P (P can be set to a positive integer), and the shift The bit difference value is set to a multiple of P in the replacement
以下根據圖6至13來描述關於在本公開的實施例中使用的LDPC算法的細節。 應該提到的是,標記,例如,“k ”,“n ”,“M ”,“P ”,“G ”,“H ”等僅用於下面的實施例和相應的圖中,僅具有解釋的目的,本發明不限於此。The details regarding the LDPC algorithm used in the embodiments of the present disclosure are described below according to FIGS. 6 to 13. It should be mentioned that the labels, for example, " k ", " n ", " M ", " P ", " G ", " H ", etc. are only used in the following embodiments and the corresponding figures, with explanation only The purpose of the present invention is not limited to this.
在本實施例中,錯誤檢查與校正電路508會根據低密度奇偶檢查碼來編碼與解碼。在低密度奇偶檢查碼中,是用一個檢查矩陣(亦稱為奇偶檢查矩陣)來定義有效的碼字。以下將奇偶檢查矩陣標記為矩陣H
,並且一碼字標記為CW
。依照以下方程式(1),若奇偶檢查矩陣H
與碼字CW
的相乘是零向量,表示碼字CW
為有效的碼字。其中運算子表示模2(mod 2)的矩陣相乘。換言之,矩陣H
的零空間(null space)便包含了所有的有效碼字(valid codeword)。然而,本發明並不限制碼字CW
的內容。例如,碼字CW
也可以包括用任意演算法所產生的錯誤更正碼或是錯誤檢查碼。In this embodiment, the error check and
…(1) …(1)
其中矩陣H 的維度是k -乘-n (k-by-n ),碼字CW 的維度是1-乘-n 。k 與n 為正整數。碼字CW 中包括了訊息位元與奇偶位元,即碼字CW 可以表示成[M P ],其中向量M 是由訊息位元所組成,向量P 是由奇偶位元所組成。向量M 的維度是1-乘-(n-k ),而向量P 的維度是1-乘-k 。以下將訊息位元與奇偶位元統稱為資料位元。換言之,碼字CW 中具有n 個資料位元,其中訊息位元的長度為(n-k )位元,並且奇偶位元的長度是k 位元,即碼字CW 的碼率(code rate)為(n-k)/n 。The dimension of the matrix H is k -by- n ( k-by-n ), and the dimension of the codeword CW is 1-by- n . k and n are positive integers. Codeword CW is included in the message bits and the parity bits, i.e., the code word CW can be expressed as [P M], where M is the vector composed by the message bits, the parity bits by the vector P is composed. The dimension of the vector M is 1-multiply-( nk ), and the dimension of the vector P is 1-multiply- k . Hereinafter, the information bits and the parity bits are collectively referred to as data bits. In other words, there are n data bits in the code word CW , where the length of the information bit is ( nk ) bits, and the length of the parity bit is k bits, that is, the code rate of the code word CW is ( nk)/n .
一般來說在編碼時會使用一個產生矩陣(以下標記為G ),使得對於任意的向量M 都可滿足以下方程式(2)。其中產生矩陣G 的維度是(n-k )-乘-n 。Generally speaking, a generating matrix (hereinafter referred to as G ) is used when encoding, so that the following equation (2) can be satisfied for any vector M. The dimension of the generating matrix G is ( nk )-multiply- n .
…(2) …(2)
由方程式(2)所產生的碼字CW 為有效的碼字。因此可將方程式(2)代入方程式(1),藉此得到以下方程式(3)。The code word CW generated by equation (2) is a valid code word. Therefore, equation (2) can be substituted into equation (1), thereby obtaining the following equation (3).
…(3) …(3)
由於向量M 可以是任意的向量,因此以下方程式(4)必定會滿足。也就是說,在決定奇偶檢查矩陣H 以後,對應的產生矩陣G 也可被決定。Since the vector M can be any vector, the following equation (4) must be satisfied. That is, after determining the parity check matrix H , the corresponding generation matrix G can also be determined.
…(4) …(4)
在解碼一個碼字CW 時,會先對碼字中的資料位元執行一個奇偶檢查程序,例如將奇偶檢查矩陣H 與碼字CW 相乘以產生一個向量(以下標記為S , 如以下方程式(5)所示)。若向量S 是零向量,則可直接輸出碼字CW 。若向量S 不是零向量,則表示碼字CW 中存在至少一個錯誤並且碼字CW 不是有效的碼字。When decoding a code word CW , a parity check procedure is first performed on the data bits in the code word, for example, the parity check matrix H is multiplied by the code word CW to generate a vector (labeled S below , as in the following equation ( 5) shown). If the vector S is a zero vector, the code word CW can be output directly. If the vector S is not zero vector, then the codeword representing at least one error exists in CW and the code word CW is not a valid codeword.
…(5) …(5)
向量S
的維度是k
-乘-1
,其中每一個元素亦稱為校驗子(syndrome)。向量S
亦稱為校驗子向量(或校驗子集合)。若碼字CW
不是有效的碼字,則錯誤檢查與校正電路508會執行一個解碼程序,以嘗試更正碼字CW
中的錯誤。The dimension of the vector S is k -multiplication- 1 , and each element is also called a syndrome. The vector S is also called a syndrome vector (or syndrome set). If the code word CW is not a valid code word, the error check and
圖6是根據本發明的一實施例所繪示的低密度奇偶檢查碼之置信傳播(belief propagation)的示意圖。FIG. 6 is a schematic diagram of belief propagation of a low-density parity check code according to an embodiment of the invention.
請參照圖6,一般來說,奇耦檢查矩陣H 可以表示為置信傳播圖610,其中包括奇偶節點601(1)~601(k)與訊息節點602(1)~602(n)。每一個奇偶節點601(1)~601(k)是對應到一個校驗子,而每一個訊息節點602(1)~602(n)是對應一個資料位元。資料位元與校驗子之間的對應關係(即,訊息節點602(1)~602(n)與奇偶節點601(1)~601(k)之間的連結關係)是根據奇偶檢查矩陣H 所產生。具體來說,若奇偶檢查矩陣H 中第i 列(row)第j 行(column)的元素為1,則第i個奇偶節點601(i)便會連接到第j 個訊息節點602(j),其中i 與j 為正整數。Referring to FIG. 6, in general, the odd-coupling check matrix H can be represented as a confidence propagation graph 610, which includes parity nodes 601(1)~601(k) and message nodes 602(1)~602(n). Each parity node 601(1)~601(k) corresponds to a syndrome, and each message node 602(1)~602(n) corresponds to a data bit. The correspondence between data bits and syndromes (ie, the connection between message nodes 602(1)~602(n) and parity nodes 601(1)~601(k)) is based on the parity check matrix H Produced. Specifically, if the element of the i-th row (row) and j- th column (column) in the parity check matrix H is 1, the i-th parity node 601(i) will be connected to the j- th message node 602(j) , Where i and j are positive integers.
當記憶體管理電路502從可複寫式非揮發性記憶體模組106中讀取n
個資料位元(形成一個碼字)時,記憶體管理電路502(或錯誤檢查與校正電路508)也會取得每一個資料位元的可靠度資訊(亦稱為通道可靠度資訊)。此可靠度資訊是用以表示對應的資料位元被解碼為位元”1”或是”0”的機率(或稱信心度)。例如,在圖610中,訊息節點602(1)~602(n)會接收到對應的可靠度資訊L1
~Ln
。其中,訊息節點602(1)會接收第1個資料位元的可靠度資訊L1
,而訊息節點602(j)會接收第j
個資料位元的可靠度資訊Lj
。When the
錯誤檢查與校正電路508會根據圖610的結構與通道可靠度資訊L1
~Ln
來執行解碼程序。在本實施例中,錯誤檢查與校正電路508所執行的解碼程序為一迭代解碼(iterative decoding)程序。在迭代解碼程序中,訊息節點602(1)~602(n)會計算出可靠度資訊給奇偶節點601(1)~601(k),並且奇偶節點601(1)~601(k)也會計算出可靠度資訊給訊息節點602(1)~602(n)。計算出來的可靠度資訊會沿著這些圖610中的邊(edge)來傳送。例如,奇偶節點601(i)傳送給訊息節點602(j)的是可靠度資訊,而訊息節點602(j)傳送給奇偶節點601(i)是可靠度資訊。這些可靠度資訊是用來表示一個節點認為某一個資料位元被解碼為“1”或是“0”的機率(或上述信心度)有多少。舉例來說,可靠度資訊表示訊息節點602(j)認為第j個資料位元被解碼為“1”或是“0”的信心度(可為正或是負),而可靠度資訊表示奇偶節點601(i)認為第j個資料位元被解碼為“1”或是“0”的信心度。而訊息節點602(1)~602(n)與奇偶節點601(1)~601(k)會根據輸入的可靠度資訊來計算輸出的可靠度資訊,其近似於計算一個資料位元被解碼為“1”或是“0”的條件機率。因此,上述傳送可靠度資訊的過程又被稱為置信傳播。The error checking and correcting
當採用不同的演算法,訊息節點602(1)~602(n)及/或奇偶節點601(1)~601(k)會計算出不同的可靠度資訊。例如,錯誤檢查與校正電路508可以採用總和-乘積演算法(Sum-Product Algorithm)、最小值-總和演算法(Min-Sum Algorithm)、或是位元翻轉(bit-flipping Algorithm),本發明並不限制採用何種演算法。When different algorithms are used, the message nodes 602(1)~602(n) and/or the parity nodes 601(1)~601(k) will calculate different reliability information. For example, the error checking and
在本實施例中,迭代解碼程序中的迭代(iteration)會不斷的重覆執行,以更新至少部份資料位元的可靠度資訊,直到成功地獲得有效碼字或執行迭代的次數到達一預定門檻值為止。例如,在迭代解碼程序的每一次迭代中,訊息節點602(1)~602(n)會傳遞可靠度資訊給奇偶節點601(1)~601(k),並且奇偶節點601(1)~601(k)會傳遞可靠度資訊給訊息節點602(1)~602(n)。In this embodiment, the iteration in the iterative decoding process will be repeated repeatedly to update the reliability information of at least part of the data bits until a valid codeword is successfully obtained or the number of execution iterations reaches a predetermined number Threshold. For example, in each iteration of the iterative decoding process, the message nodes 602(1)~602(n) will pass the reliability information to the parity nodes 601(1)~601(k), and the parity nodes 601(1)~601 (k) will transmit reliability information to the message nodes 602(1)~602(n).
在每一次迭代過後,錯誤檢查與校正電路508會根據目前的可靠度資訊計算出每一個資料位元應該被解碼為位元“1”或是“0”並且對這些計算出的資料位元進行驗證。例如,錯誤檢查與校正電路508會執行奇偶檢查程序以驗證計算出的資料位元。在奇偶檢查程序中,錯誤檢查與校正電路508會將資料位元所形成的碼字與相對應的奇偶檢查矩陣相乘,藉此判斷該碼字是否為有效的碼字。若所產生的碼字為有效的碼字,表示解碼成功,並且迭代解碼程序會停止。若所產生的碼字不是有效的碼字,則會進行下一次的迭代。此外,若迭代解碼程序中的迭代次數超過一個預設值,則迭代解碼也會停止,表示解碼失敗。After each iteration, the error checking and
圖7是根據本發明的一實施例所繪示的奇偶檢查矩陣的示意圖。7 is a schematic diagram of a parity check matrix according to an embodiment of the invention.
請參照圖7,奇偶檢查矩陣700的維度是6-乘-9,但本發明並不限制正整數k
與n
為多少。奇偶檢查矩陣700的每一列(row)亦代表了一個限制(constraint)。以奇偶檢查矩陣700的第一列為例,若某一個碼字是有效碼字,則將此碼字中第2、6及7個位元做模2(modulo-2)的加法之後,會得到位元“0”。在此領域有通常知識者應能理解如何用奇偶檢查矩陣700來編碼,在此便不再贅述。此外,奇偶檢查矩陣700僅為一個範例矩陣,而非用以限制本發明。Referring to FIG. 7, the dimension of the
當記憶體管理電路502要將多個位元寫入至可複寫式非揮發性記憶體模組406時,錯誤檢查與校正電路508會對每(n
-k
)個欲被寫入的位元(即,訊息位元)都產生對應的k
個位元(即,奇偶位元)。記憶體管理電路502會把這n
個位元(即,資料位元)作為一個碼字寫入至可複寫式非揮發性記憶體模組406。When the
記憶體管理電路502會接收來自主機系統11的一讀取指令。根據此讀取指令,記憶體管理電路502會發送一讀取指令序列至可複寫式非揮發性記憶體模組406。此讀取指令序列會指示可複寫式非揮發性記憶體模組406讀取至少一實體單元。根據此讀取指令序列,可複寫式非揮發性記憶體模組406會執行相對應的讀取操作(例如,施予讀取電壓至某一實體單元以讀取至少一記憶胞所儲存之資料)並回傳一回應資料給記憶體管理電路502。記憶體管理電路502會接收來自可複寫式非揮發性記憶體模組406的回應資料,並且錯誤檢查與校正電路508會對此回應資料執行一迭代解碼程序。The
在本實施例中,記憶體管理電路502會決定一個偏移臨界值。根據所決定的偏移臨界值,記憶體管理電路502會決定一個檢查矩陣(例如,圖7中的奇偶檢查矩陣700)。錯誤檢查與校正電路508會根據此檢查矩陣來執行上述編碼與解碼程序。相關的編碼與解碼程序已詳述於上,在此便不贅述。In this embodiment, the
在本實施例中,所決定的檢查矩陣會包括多個子矩陣。此些子矩陣會被分組為至少一個子矩陣群組。每一個子矩陣會具有一個預設維度。特別是,所決定的偏移臨界值會小於對應於此預設維度的一個預設維度值。例如,若每一個子矩陣的預設維度皆為3-乘-3,則對應於此預設維度的預設維度值為“3”。In this embodiment, the determined inspection matrix will include multiple sub-matrices. These sub-matrices will be grouped into at least one sub-matrix group. Each sub-matrix will have a preset dimension. In particular, the determined offset threshold value will be smaller than a preset dimension value corresponding to this preset dimension. For example, if the preset dimension of each sub-matrix is 3-by-3, the preset dimension value corresponding to this preset dimension is "3".
在迭代解碼程序中,錯誤檢查與校正電路508會產生對應於所接收之回應資料的一個資料集合。此資料集合會包括多個群組。錯誤檢查與校正電路508會根據所決定的偏移臨界值與所決定的檢查矩陣中不同的子矩陣群組來移動(shift)此些資料集合中的群組以獲得多個偏移群組(已偏移群組),使得資料集合中的每一個群組對應於每一次的移位(以下亦稱為群組移動)的一偏移量(如,移位差值)都不會超過所決定的偏移臨界值。值得一提的是,在此提及的群組移動是指以群組為單位來移動各個群組中的位元。例如,假設某一個群組包括依序排列的元素“A1
”、“A2
”及“A3
”,則在對於此群組執行位移量為“1”(即,offset=1)的群組移動之後,此群組中的元素排列順序改變為元素“A3
”、“A1
”及“A2
”;而依序排列的元素“A3
”、“A1
”及“A2
”可視為相對於依序排列的元素“A3
”、“A1
”及“A2
”之偏移群組,並且依序排列的元素“A3
”、“A1
”及“A2
”相對於依序排列的元素“A3
”、“A1
”及“A2
”的偏移量為“1”。然後,錯誤檢查與校正電路508會根據此些偏移群組來產生解碼參考資料。此解碼參考資料會在迭代解碼程序中被使用。In the iterative decoding process, the error checking and
在一實施例中,所產生的解碼參考資料是對應於一個奇偶檢查程序的校驗子集合(亦稱為校驗子向量)並且可被用來驗證某一碼字是否為有效碼字(或,解碼是否成功)。在一實施例中,所產生的解碼參考資料是對應於一個位元翻轉演算法的校驗權重集合(亦稱為校驗權重向量)並且可被用來決定要被翻轉的資料位元。在一實施例中,所產生的解碼參考資料則是對應於一個最小值-總和演算法的最小值集合(亦稱為最小值向量)並且可被用來決定至少部份資料位元的可靠度資訊。以下基於多個實施例來說明如何在迭代解碼程序中對資料集合執行移動群組並產生相對應的解碼參考資料。In one embodiment, the generated decoded reference data is a set of syndromes (also called syndrome vectors) corresponding to a parity check procedure and can be used to verify whether a codeword is a valid codeword (or , Whether the decoding is successful). In one embodiment, the generated decoding reference data is a set of check weights (also called check weight vectors) corresponding to a bit flip algorithm and can be used to determine the data bits to be flipped. In one embodiment, the generated decoded reference data corresponds to a minimum set (also called minimum vector) of a minimum-sum algorithm and can be used to determine the reliability of at least some data bits News. The following is based on multiple embodiments to explain how to perform a moving group on a data set in an iterative decoding process and generate corresponding decoding reference data.
圖8是根據本發明的一實施例所繪示的奇偶檢查程序的示意圖。在本實施例中,資料集合與解碼參考資料皆是用於低密度奇偶檢查碼的奇偶檢查程序。例如,資料集合是指奇偶檢查程序中待驗證之碼字,而解碼參考資料則是奇偶檢查程序中產生的校驗子集合。FIG. 8 is a schematic diagram of a parity check procedure according to an embodiment of the invention. In this embodiment, both the data set and the decoded reference data are parity check procedures for low density parity check codes. For example, the data set refers to the codeword to be verified in the parity check procedure, and the decoded reference data is the checksum set generated in the parity check procedure.
請參照圖8,記憶體管理電路502會決定一個偏移臨界值。在本實施例中,所決定的偏移臨界值為“2”。對應於所決定的偏移臨界值,記憶體管理電路502會決定一個奇偶檢查矩陣800。奇偶檢查矩陣800會被用來執行儲存資料時的編碼與讀取資料時的解碼。Referring to FIG. 8, the
在本實施例中,奇偶檢查矩陣800包括子矩陣群組830與840。子矩陣群組830與840分別包括以列(row)方向排列的子矩陣831~833以及841~843。子矩陣831~833以及841~843中的每一者皆為一個方陣,並且子矩陣831~833以及841~843中的每一者皆具有一個預設維度。例如,子矩陣831~833以及841~843中的每一者之預設維度皆為3-乘-3,並且對應於此預設維度的預設維度值為“3”。記憶體管理電路502會限制所決定的奇偶檢查矩陣800中,對應於子矩陣831~833以及841~843中的每一者之預設維度的預設維度值(即,“3”)大於事先決定的偏移臨界值(即,“2”)。然而,對應於不同的偏移臨界值,所決定的奇偶檢查矩陣也可以不同,只要滿足所決定的奇偶檢查矩陣中各個子矩陣的預設維度值大於事先決定的偏移臨界值即可。例如,在另一實施例中,奇偶檢查矩陣中的子矩陣群組的數目可以是更多或更少、每一個子矩陣群組中的子矩陣的數目可以是更多或更少,並且每一個子矩陣的預設維度可以是更大或更小。In this embodiment, the
在本實施例中,在記憶體管理電路502發送上述讀取指令序列並接收對應於此讀取指令序列的回應資料之後,錯誤檢查與校正電路508會對此回應資料執行迭代解碼程序。在迭代解碼程序的某一迭代中,碼字810會被決定並且在對應的奇偶檢查程序中被驗証是否為有效碼字。In this embodiment, after the
具體而言,在對於碼字810的奇偶檢查程序中,錯誤檢查與校正電路508會獲得奇偶檢查矩陣800與碼字810之矩陣相乘的結果並將此結果作為校驗子集合820。例如,對應於奇偶檢查矩陣800的第一列中的多個元素1的位置,對碼字810中的位元A2
、B3
及C1
執行模2加法可獲得校驗子集合820中的校驗子S1
;對應於奇偶檢查矩陣800的第二列中的多個元素1的位置,對碼字810中的位元A3
、B1
及C2
執行模2加法可獲得校驗子集合820中的校驗子S2
;對應於奇偶檢查矩陣800的第四列中的多個元素1的位置,對碼字810中的位元A3
、B1
及C2
執行模2加法可獲得校驗子集合820中的校驗子S4
。以此類推,校驗子集合820中的校驗子S1
~S6
會被獲得。然後,錯誤檢查與校正電路508會根據校驗子集合820是否為零向量(即,校驗子S1
~S6
皆為“0”)來判斷碼字810中是否存在錯誤。例如,若校驗子S1
~S6
皆為“0”,則錯誤檢查與校正電路508會判定碼字810中不存在任何錯誤(即,碼字810為有效碼字)並且根據碼字810輸出解碼資料;然而,若校驗子S1
~S6
的至少其中之一為“1”,則錯誤檢查與校正電路508會判定碼字810中存在錯誤。若錯誤檢查與校正電路508判定碼字810中存在錯誤且已執行之迭代的次數尚未達到預定門檻值,則錯誤檢查與校正電路508會對於碼字810執行下一次迭代並且再次執行一個奇偶檢查程序來對產生的碼字進行驗證。此外,在一實施例中,亦可以搭配改變讀取電壓準位來再次讀取相同的實體單元或改變解碼方式等機制來加強解碼效率,在此便不贅述。Specifically, in the parity check procedure for the
在本實施例中,錯誤檢查與校正電路508並不會真正地執行如圖8所繪示的矩陣相乘。取而代之的是,錯誤檢查與校正電路508會對應於奇偶檢查矩陣800中的子矩陣群組830與840來對碼字810執行群組移動以及矩陣加法來獲得校驗子集合820。原因在於,在多數的情況下,執行矩陣加法相對於執行矩陣乘法具有運算複雜度較低及/或運算速度較快之優勢。換言之,錯誤檢查與校正電路508會以層(layer)為單位來逐漸產生校驗子集合820。例如,子矩陣群組830為第一層並且用以計算校驗子集合820中的校驗子S1
~S3
;子矩陣群組840為第二層並且用以計算校驗子集合820中的校驗子S4
~S6
。In this embodiment, the error check and
在本實施例中,對應於奇偶檢查矩陣800中每一個子矩陣的預設維度,錯誤檢查與校正電路508會將碼字810中的位元分組為多個群組(以下亦稱為預設群組)。例如,對應於子矩陣的預設維度為3-乘3,碼字810中的位元A1
、A2
、A3
被分組至同一個預設群組(以下亦稱為第一預設群組),碼字810中的位元B1
、B2
、B3
被分組至同一個預設群組(以下亦稱為第二預設群組),並且碼字810中的位元C1
、C2
、C3
被分組至同一個預設群組(以下亦稱為第三預設群組)。在對應的群組移動中,碼字810中的每一個位元皆是以其所屬的群組作為一個統一移動單位。換言之,屬於同一個群組的多個位元對應於一次的群組移動之偏移量會相同,而屬於不同群組的多個位元對應於一次的群組移動之偏移量可能相同或不同。例如,在對應於某一個層的群組移動中,同屬於第一預設群組的位元A1
、A2
及A3
的偏移量相同,但分別屬於第一預設群組與第二預設群組的位元A1
與B1
的偏移量可能相同或不同。In this embodiment, corresponding to the preset dimension of each sub-matrix in the
圖9是根據本發明的一實施例所繪示的獲得對應於奇偶檢查程序之校驗子集合的示意圖。FIG. 9 is a schematic diagram of obtaining a parity set corresponding to a parity check procedure according to an embodiment of the invention.
請參照圖8與圖9,對應於子矩陣群組830(即,第一層)的群組移動會先被執行。例如,對應於子矩陣群組830中元素1的位置,碼字810中的位元A1
、A2
、A3
會被移動為位元A2
、A3
、A1
,碼字810中的位元B1
、B2
、B3
會被移動為位元B3
、B1
、B2
,並且碼字810中的位元C1
、C2
、C3
不被移動。因此,圖9中包含依序排列的位元A2
、A3
、A1
、B3
、B1
、B2
、C1
、C2
、C3
的碼字910會被獲得。8 and 9, the group movement corresponding to the sub-matrix group 830 (ie, the first layer) will be performed first. For example, corresponding to the position of
在本實施例中,碼字910中的位元A2
、A3
、A1
被視為屬於對應於第一預設群組的偏移群組911,碼字910中的位元B3
、B1
、B2
被視為屬於對應於第二預設群組的偏移群組912,並且碼字910中的位元C1
、C2
、C3
被視為屬於對應於第三預設群組的偏移群組913。其中,偏移群組911相對於第一預設群組的偏移量為“1”(即,offset=1),偏移群組912相對於第二預設群組的偏移量為“2”(即,offset=2),並且偏移群組913相對於第三預設群組的偏移量為“0”(即,offset=0)。然後,錯誤檢查與校正電路508會根據偏移群組911~913來產生校驗子集合820中的一部份校驗子。例如,錯誤檢查與校正電路508會對偏移群組911~913執行矩陣加法以獲得校驗子向量1020中的校驗子S1
~S3
。In this embodiment, the bits A 2 , A 3 , and A 1 in the
在獲得偏移群組911~913之後,對應於子矩陣群組840(即,第二層)的群組移動會被執行。例如,對應於子矩陣群組840中元素1的位置,偏移群組911中的位元A2
、A3
、A1
會被移動為位元A3
、A1
、A2
,偏移群組912中的位元B3
、B1
、B2
會被移動為位元B1
、B2
、B3
,並且偏移群組913中的位元C1
、C2
、C3
會被移動為位元C2
、C3
、C1
。因此,圖9中包含依序排列的位元A3
、A1
、A2
、B1
、B2
、B3
、C2
、C3
、C1
的碼字920會被獲得。After obtaining the offset groups 911-913, the group movement corresponding to the sub-matrix group 840 (ie, the second layer) will be performed. For example, corresponding to the position of
在本實施例中,碼字920中的位元A3
、A1
、A2
被視為屬於對應於偏移群組911的偏移群組921,碼字920中的位元B1
、B2
、B3
被視為屬於對應於偏移群組912的偏移群組922,並且碼字920中的位元C2
、C3
、C1
被視為屬於對應於偏移群組913的偏移群組923。其中,偏移群組921相對於偏移群組911的偏移量為“1”(即,offset=1),偏移群組922相對於偏移群組912的偏移量為“1”(即,offset=1),並且偏移群組923相對於偏移群組913的偏移量為“1”(即,offset=1)。然後,錯誤檢查與校正電路508會根據偏移群組921~923來產生校驗子集合820中的另一部份的校驗子。例如,錯誤檢查與校正電路508會對偏移群組921~923執行矩陣加法以獲得校驗子集合820中的校驗子S4
~S6
。In this embodiment, the bits A 3 , A 1 , and A 2 in the
記憶體管理電路502(或,錯誤檢查與校正電路508)會限制對應於每一個子矩陣群組(即,層)所執行的群組移動之偏移量皆不超過所決定的偏移臨界值。例如,在圖8與圖9的實施例中,偏移臨界值被設定為“2”,因此,偏移群組911~913中的每一者相對於其在碼字810中的一個對應群組的偏移量皆不超過“2”;而偏移群組921~923分別相對於偏移群組911~913的偏移量也不超過“2”。例如,在執行對應於子矩陣群組830(即,第一層)的群組移動而產生偏移群組911~913的操作中,碼字810中每一個位元的偏移量可以是“0”、“1”或“2”,視其所屬的群組而定;而在執行對應於子矩陣群組840(即,第二層)的群組移動而產生偏移群組921~923的操作中,碼字920中每一個位元的偏移量也可以是“0”、“1”或“2”,視其所屬的群組而定。此外,在圖8與圖9的另一實施例中,若偏移臨界值被設定為“1”,則在後續每一次的群組移動中每一個偏移群組中的位元之偏移量皆不超過“1”。The memory management circuit 502 (or, the error checking and correction circuit 508) restricts the offset of the group movement performed for each sub-matrix group (ie, layer) to not exceed the determined offset threshold . For example, in the embodiments of FIGS. 8 and 9, the offset threshold is set to “2”, therefore, each of the offset groups 911-913 is relative to its corresponding group in the
在一實施例中,若奇偶檢查程序中產生的校驗子集合不是零向量(例如,圖8中校驗子S1 ~S6 的至少其中之一為“1”),表示當前驗證的碼字中存在錯誤。因此,一個位元翻轉演算法可以被用來快速地決定要翻轉(flip)碼字中的哪一個位元,例如,將某一個位元的值從“0”改變為“1”或者從“1”改變為“0”,以嘗試更正碼字中的錯誤。在位元翻轉演算法中,需要計算對應於校驗子集合的一個校驗權重(syndrome weight)集合並且碼字中的至少一個位元會基於此校驗權重集合而被翻轉。在一實施例中,藉由對資料集合中的多個群組執行群組移動來獲得相對應的解碼參考資料,則可降低計算校驗權重集合的運算複雜度及/或提高運算速度。然而,在另一實施例中,若判定當前驗證碼字中存在錯誤,其他的解碼演算法也可以被用來更正碼字中的錯誤。In an embodiment, if the set of syndromes generated in the parity check procedure is not a zero vector (for example, at least one of the syndromes S 1 to S 6 in FIG. 8 is “1”), it represents the currently verified code There is an error in the word. Therefore, a bit flip algorithm can be used to quickly determine which bit in a codeword to flip, for example, to change the value of a bit from "0" to "1" or from "1" changed to "0" to try to correct the error in the codeword. In the bit flip algorithm, it is necessary to calculate a syndrome weight set corresponding to the syndrome set and at least one bit in the codeword will be flipped based on this syndrome weight set. In one embodiment, by performing group movement on multiple groups in the data set to obtain corresponding decoded reference data, the calculation complexity and/or the calculation speed of calculating the check weight set can be reduced. However, in another embodiment, if it is determined that there is an error in the current verification codeword, other decoding algorithms can also be used to correct the error in the codeword.
圖10與圖11是根據本發明的另一實施例所繪示的獲得對應於位元翻轉演算法之校驗權重的示意圖。在本實施例中,資料集合與解碼參考資料皆是用於位元翻轉演算法。例如,資料集合是指位元翻轉演算法中待更新之校驗權重集合,而解碼參考資料則是位元翻轉演算法中更新後的校驗權重集合。10 and 11 are schematic diagrams of obtaining check weights corresponding to a bit flip algorithm according to another embodiment of the invention. In this embodiment, both the data set and the decoding reference data are used for the bit flip algorithm. For example, the data set refers to the set of check weights to be updated in the bit flip algorithm, and the decoding reference data is the updated set of check weights in the bit flip algorithm.
請參照圖10,在獲得校驗子集合820之後,在位元翻轉演算法中,一個校驗權重集合1001會被決定。例如,校驗權重集合1001會包括依序排列的校驗權重EA1
、EA2
、EA3
、EB1
、EB2
、EB3
、EC1
、EC2
及EC3
。其中,校驗權重EA1
、EA2
、EA3
、EB1
、EB2
、EB3
、EC1
、EC2
及EC3
分別對應於碼字810中的位元A1
、A2
、A3
、B1
、B2
、B3
、C1
、C2
及C3
。校驗權重集合1001可用來表示碼字810中每一個位元對於碼字810中的錯誤之參與程度。例如,根據奇偶檢查矩陣800,位元A1
參與了校驗子S3
與S5
的計算,故可根據校驗子S3
與S5
來計算對應於位元A1
的校驗權重EA1
。例如,可將校驗子S3
與S5
相加以獲得校驗權重EA1
。又例如,根據奇偶檢查矩陣800,位元A2
參與了校驗子S1
與S6
的計算,故可根據校驗子S1
與S6
來計算對應於位元A2
的校驗權重EA2
。例如,可將校驗子S1
與S6
相加以獲得校驗權重EA2
。特別是,在此用來計算校驗權重之加法是指一般加法,並非模2加法。例如,若校驗子S3
與S5
皆為“1”,則將校驗子S3
與S5
相加可獲得校驗權重EA1
為“2”。以此類推,根據奇偶檢查矩陣800與校驗子集合820,校驗權重集合1001可被獲得。Referring to FIG. 10, after obtaining the parity set 820, in the bit flip algorithm, a parity set 1001 is determined. For example, the check weight set 1001 may include the check weights EA 1 , EA 2 , EA 3 , EB 1 , EB 2 , EB 3 , EC 1 , EC 2, and EC 3 arranged in this order. Among them, the verification weights EA 1 , EA 2 , EA 3 , EB 1 , EB 2 , EB 3 , EC 1 , EC 2 and EC 3 correspond to the bits A 1 , A 2 , A 3 , and 3 in the
在位元翻轉演算法中,若碼字中的某一個位元所對應的校驗權重很大,表示此位元有較大的機率為錯誤位元,因此翻轉此位元有較高的機率可以更正錯誤。反之,若碼字中的某一個位元所對應的校驗權重很小,則表示此位元為錯誤位元的機率不高,因此翻轉此位元可以更正錯誤的機率也不高。一般來說,根據奇偶檢查矩陣800與校驗子集合820來獲得校驗權重集合1001的操作可以等效於將向量1002加上向量1003來獲得校驗權重集合1001。其中,向量1002中的元素僅包括校驗子S1
~S3
,而向量1003中的元素則僅包括校驗子S4
~S6
。校驗子S1
~S3
在向量1002中的位置是根據奇偶檢查矩陣800來決定,並且校驗子S4
~S6
在向量1003中的位置也是根據奇偶檢查矩陣800來決定。In the bit flip algorithm, if the check weight corresponding to a bit in the codeword is very large, it means that this bit has a greater probability of being an erroneous bit, so flipping this bit has a higher probability The error can be corrected. Conversely, if the check weight corresponding to a bit in the codeword is very small, the probability that this bit is an erroneous bit is not high, so the probability of correcting an error by flipping this bit is not high. In general, the operation of obtaining the check weight set 1001 according to the
在本實施例中,錯誤檢查與校正電路508同樣是以層為單位來逐漸產生校驗權重集合1001。例如,子矩陣群組830為第一層並且用以執行校驗權重集合的第一更新操作;子矩陣群組840為第二層並且用以執行校驗權重集合的第二更新操作。在本實施例中,錯誤檢查與校正電路508會將向量1001中的多個校驗權重分組為多個預設群組。例如,校驗權重EA1
、EA2
、EA3
屬於第一預設群組,校驗權重EB1
、EB2
、EB3
屬於第二預設群組,並且校驗權重EC1
、EC2
、EC3
屬於第三預設群組。In this embodiment, the error check and
請參照圖11,對應於子矩陣群組830(即,第一層)的群組移動會先被執行。例如,對應於子矩陣群組830中元素1的位置,屬於第一預設群組的校驗權重EA1
、EA2
、EA3
會被移動為校驗權重EA2
、EA3
、EA1
,屬於第二預設群組的校驗權重EB1
、EB2
、EB3
會被移動為位元EB3
、EB1
、EB2
,而屬於第三預設群組的校驗權重EC1
、EC2
、EC3
不被移動。因此,圖11中包含依序排列的校驗權重EA2
、EA3
、EA1
、EB3
、EB1
、EB2
、EC1
、EC2
、EC3
的向量1101會被獲得。例如,向量1101中的校驗權重EA2
、EA3
、EA1
屬於相對於第一預設群組的一個偏移群組;向量1101中的校驗權重EB3
、EB1
、EB2
屬於相對於第二預設群組的一個偏移群組;並且向量1101中的校驗權重EC1
、EC2
、EC3
屬於相對於第三預設群組的一個偏移群組。Referring to FIG. 11, the group movement corresponding to the sub-matrix group 830 (ie, the first layer) will be performed first. For example, corresponding to the position of
然後,錯誤檢查與校正電路508會利用向量1103與1104來產生向量1102。其中,向量1101~1103中所有元素的排序皆一致,如圖11所示。此外,向量1103中所有元素的初始值皆被設為“0”。在本實施例中,產生向量1102的操作亦可視為將向量1103更新為向量1102之操作。例如,在將向量1103更新為向量1102之操作中,向量1103中的校驗權重EA2
、EA3
、EA1
會被分別加上向量1104中的校驗子S1
、S2
、S3
以獲得向量1102中更新後的校驗權重EA2
、EA3
、EA1
;向量1103中的EB3
、EB1
、EB2
會分別被加上向量1104中的校驗子S1
、S2
、S3
來獲得向量1102中更新後的校驗權重EB3
、EB1
、EB2
;並且向量1103中的EC1
、EC2
、EC3
也會分別被加上向量1104中的校驗子S1
、S2
、S3
來獲得向量1102中更新後的校驗權重EC1
、EC2
、EC3
。Then, the error checking and correcting
在獲得向量1102之後,對應於子矩陣群組840(即,第二層)的群組移動會被執行。例如,對應於子矩陣群組840中元素1的位置,向量1102中的校驗權重EA2
、EA3
、EA1
會被移動為校驗權重EA3
、EA1
、EA2
,向量1102中的校驗權重EB3
、EB1
、EB2
會被移動為校驗權重EB1
、EB2
、EB3
,並且向量1102中的校驗權重EC1
、EC2
、EC3
會被移動為校驗權重EC2
、EC3
、EC1
。因此,圖11中包含依序排列的校驗權重EA3
、EA1
、EA2
、EB1
、EB2
、EB3
、EC2
、EC3
、EC1
的向量1105會被獲得。After obtaining the
然後,錯誤檢查與校正電路508會利用向量1107與向量1108來產生向量1106。其中,向量1105~1107中所有元素的排序皆一致,如圖11所示。此外,產生向量1106的操作亦可視為將向量1107更新為向量1106之操作。例如,在將向量1107更新為向量1106之操作中,向量1107中的校驗權重EA3
、EA1
、EA2
會分別被加上向量1108中的校驗子S4
、S5
、S6
來獲得向量1106中更新後的校驗權重EA3
、EA1
、EA2
;向量1107中的EB1
、EB2
、EB3
會分別被加上向量1108中的校驗子S4
、S5
、S6
來獲得向量1106中更新後的校驗權重EB1
、EB2
、EB3
;並且向量1107中的EC2
、EC3
、EC1
也會分別被加上向量1108中的校驗子S4
、S5
、S6
來獲得向量1106中更新後的校驗權重EC2
、EC3
、EC1
。所產生的向量1106即包含了對應於圖10的碼字810中每一個位元的校驗權重。換言之,利用圖11的實施例中依序更新向量1102與1106的操作來取代圖10中將向量1102加上1003的操作,可提升在位元翻轉演算法中計算校驗權重集合之效率。Then, the error check and
在一實施例中,若錯誤檢查與校正電路508是採用總和-乘積演算法來更新迭代解碼程序中使用的可靠度資訊,則藉由對資料集合中的多個群組執行群組移動來獲得相對應的解碼參考資料之操作,同樣可用於降低執行最小值-總和演算法的運算複雜度及/或提高運算速度。In one embodiment, if the error checking and
圖12與圖13是根據本發明的另一實施例所繪示的獲得對應於最小值-總和演算法之最小值集合的示意圖。在本實施例中,資料集合與解碼參考資料皆是用於最小值-總和演算法。例如,資料集合是指待解碼之碼字,而解碼參考資料則是最小值-總和演算法中產生的最小值集合。12 and 13 are schematic diagrams of obtaining a minimum value set corresponding to the minimum value-sum algorithm according to another embodiment of the present invention. In this embodiment, both the data set and the decoding reference data are used for the minimum-sum algorithm. For example, the data set refers to the codeword to be decoded, and the decoded reference data is the minimum set generated in the minimum-sum algorithm.
請參照圖12,在採用最小值-總和演算法的迭代解碼程序中,錯誤檢查與校正電路508會根據奇偶檢查矩陣800來對碼字810中的不同位元進行多次比較以產生最小值集合1201。例如,最小值集合1201包括最小值m1~m6。其中,最小值m1
是取碼字810中的位元A2
、B3
及C1
之最小者;最小值m2
是取碼字810中的位元A3
、B1
及C2
之最小者;最小值m3
是取碼字810中的位元A1
、B2
及C3
之最小者;最小值m4
是取碼字810中的位元A3
、B1
及C2
之最小者;最小值m5
是取碼字810中的位元A1
、B2
及C3
之最小者;最小值m6
是取碼字810中的位元A2
、B3
及C1
之最小者。Referring to FIG. 12, in the iterative decoding process using the minimum-sum algorithm, the error checking and
在本實施例中,錯誤檢查與校正電路508同樣會以層為單位來逐漸產生最小值集合1201。例如,子矩陣群組830為第一層並且用以計算最小值集合1201中的校驗子m1
~m3
;子矩陣群組840為第二層並且用以計算最小值集合1201中的校驗子m4
~m6
。在本實施例中,錯誤檢查與校正電路508會將碼字810中的位元分組為多個預設群組。例如,碼字810中的位元A1
、A2
、A3
屬於第一預設群組,碼字810中的位元B1
、B2
、B3
屬於第二預設群組,並且碼字810中的位元C1
、C2
、C3
屬於第三預設群組。In this embodiment, the error checking and correcting
請參照圖13,對應於子矩陣群組830(即,第一層)的群組移動會先被執行。例如,對應於子矩陣群組830中元素1的位置,碼字810中的位元A1
、A2
、A3
會被移動為位元A2
、A3
、A1
,碼字810中的位元B1
、B2
、B3
會被移動為位元B3
、B1
、B2
,而碼字810中的位元C1
、C2
、C3
不被移動。因此,圖13中包含依序排列之位元A2
、A3
、A1
、B3
、B1
、B2
、C1
、C2
、C3
的碼字910會被獲得。例如,碼字910中的位元A2
、A3
、A1
屬於相對於第一預設群組的偏移群組911;碼字910中的位元B3
、B1
、B2
屬於相對於第二預設群組的偏移群組912;並且碼字910中的位元C1
、C2
、C3
屬於相對於第三預設群組的偏移群組913。Referring to FIG. 13, the group movement corresponding to the sub-matrix group 830 (ie, the first layer) will be performed first. For example, corresponding to the position of
然後,錯誤檢查與校正電路508會對偏移群組911~913中位於的特定位置的位元取最小值以產生最小值集合1201中的校驗子m1
~m3
。例如,錯誤檢查與校正電路508會對偏移群組911~913中位於每一個群組中第一個位置的位元A2
、B3
、C1
取最小值作為m1
;對偏移群組911~913中位於每一個群組中第二個位置的位元A3
、B1
、C2
取最小值作為m2
;並且對偏移群組911~913中位於每一個群組中第三個位置的位元A1
、B2
、C3
取最小值作為m3
。Then, the error checking and correcting
在獲得偏移群組911~913之後,對應於子矩陣群組840(即,第二層)的群組移動會被執行。例如,對應於子矩陣群組840中元素1的位置,偏移群組911中的位元A2
、A3
、A1
會被移動為位元A3
、A1
、A2
,偏移群組912中的位元B3
、B1
、B2
會被移動為位元B1
、B2
、B3
,並且偏移群組913中的位元C1
、C2
、C3
會被移動為位元C2
、C3
、C1
。因此,圖13中包含位元A3
、A1
、A2
、B1
、B2
、B3
、C2
、C3
、C1
的碼字920會被獲得。例如,碼字920中的位元A3
、A1
、A2
被視為屬於對應於偏移群組911的偏移群組921,碼字920中的位元B1
、B2
、B3
被視為屬於對應於偏移群組912的偏移群組922,並且碼字920中的位元C2
、C3
、C1
被視為屬於對應於偏移群組913的偏移群組923。After obtaining the offset groups 911-913, the group movement corresponding to the sub-matrix group 840 (ie, the second layer) will be performed. For example, corresponding to the position of
然後,錯誤檢查與校正電路508會對偏移群組921~923中位於特定位置的位元取最小值以產生最小值集合1201中的校驗子m4
~m6
。例如,錯誤檢查與校正電路508會對偏移群組921~923中位於每一個群組中第一個位置的位元A3
、B1
、C2
取最小值作為m4
;對偏移群組921~923中位於每一個群組中第二個位置的位元A1
、B2
、C3
取最小值作為m5
;並且對偏移群組921~923中位於每一個群組中第三個位置的位元A2
、B3
、C1
取最小值作為m6
。藉此,可獲得最小值-總和演算法中使用的最小值集合1201並可提升計算效率。Then, the error checking and correcting
综上所述,在上述多個實施例中,即使所提及的操作分別是應用於迭代解碼程序中的不同階段及/或對應於不同的解碼演算法,但是對於預設臨界值之設定、奇偶檢查矩陣之設定、資料集合中群組之設定,以及資料集合對於每一個層的群組移動之操作都是相同或相似的。換言之,對應於迭代解碼程序中的不同階段及/或不同的解碼演算法,只要對應地決定要將什麼資料作為資料集合以及根據移動後的群組要執行何種操作來產生解碼參考資料則可。In summary, in the above-mentioned embodiments, even though the mentioned operations are applied to different stages in the iterative decoding process and/or correspond to different decoding algorithms, for the setting of the preset threshold, The setting of the parity check matrix, the setting of the group in the data set, and the operation of the data set for the group movement of each layer are the same or similar. In other words, corresponding to different stages and/or different decoding algorithms in the iterative decoding process, as long as correspondingly decide what data is to be used as a data set and what operation to perform according to the moved group to generate decoded reference data, .
在一實施例中,所決定的偏移臨界值會負相關(negatively correlated)於相對應採用的奇偶檢查矩陣的行權重值(column weight)。其中,奇偶檢查矩陣的行權重值對應於奇偶檢查矩陣中的某一個行所包含的元素1之數目。例如,若偏移臨界值越大,則對應採用的奇偶檢查矩陣的某一個行所包含的元素1之數目可能越小;若偏移臨界值越小,則對應採用的奇偶檢查矩陣的某一個行所包含的元素1之數目可能越多。在一實施例中,奇偶檢查矩陣的行權重值是對應於奇偶檢查矩陣中的包含最多的元素1之行所包含的元素1之數目。例如,在某一奇偶檢查矩陣中,某一個行包含二個元素1,而另一個行包含三個元素1,則此奇偶檢查矩陣的行權重值可被決定為“3”。In one embodiment, the determined offset threshold value is negatively correlated with the corresponding column weight of the parity check matrix. The row weight value of the parity check matrix corresponds to the number of
綜上所述,本發明的實施例所提供的解碼器設計方法與儲存控制器,可以經由根據QC-LDPC解碼器的檢查矩陣的移位類型從第一置換網路中移除目標第一置換層,以構建改進的第二置換網路,所述第二置換網路用於在QC-LDPC解碼器的置換電路中佈置較少的選擇器和路由線。如此一來,可使置換電路的硬件成本降低,並且相應地降低功耗和產生的熱量。In summary, the decoder design method and the storage controller provided by the embodiments of the present invention can remove the target first permutation from the first permutation network through the shift type according to the check matrix of the QC-LDPC decoder Layer to construct an improved second replacement network for arranging fewer selectors and routing lines in the replacement circuit of the QC-LDPC decoder. In this way, the hardware cost of the replacement circuit can be reduced, and the power consumption and heat generated can be reduced accordingly.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.
10:記憶體儲存裝置 11:主機系統 110:系統匯流排 111:處理器 112:隨機存取記憶體 113:唯讀記憶體 114:資料傳輸介面 12:輸入/輸出(I/O)裝置 20:主機板 201:隨身碟 202:記憶卡 203:固態硬碟 204:無線記憶體儲存裝置 205:全球定位系統模組 206:網路介面卡 207:無線傳輸裝置 208:鍵盤 209:螢幕 210:喇叭 32:SD卡 33:CF卡 34:嵌入式儲存裝置 341:嵌入式多媒體卡 342:嵌入式多晶片封裝儲存裝置 402:連接介面單元 404:記憶體控制電路單元 406:可複寫式非揮發性記憶體模組 502:記憶體管理電路 504:主機介面 506:記憶體介面 508:錯誤檢查與校正電路 510:緩衝記憶體 512:電源管理電路 5081:解碼器 5082:編碼器 581:解碼控制器 582:緩衝器 583:檢查節點電路 584:變量節點電路 585、585’:置換電路 586:校驗子計算電路 587:終止電路 S511、S512、S513、S514、S515、S516:解碼器設計方法的流程步驟 X1~X8:輸入端 Y1~Y8:輸出端 5851、5851’:置換路 5851’(0)~5851’(2)、5851(1)~5851(2):置換層 590’(1)~590’(8)、591(1)~591(8)、592(1)~592(8)、591’(1)~591’(8)、592’(1)~592’(8):節點 V(1)~V(N)、IV(1)~IV(N):初始變量群組 1410(1)~1410(M):子矩陣組 IW_591(1)、CW_591(1)、OW1_591(1)、OW2_591(1)、CW_592(1)、OW1_592(1)、OW2_592(1):路由線 601(1)~601(k):奇偶節點 602(1)~602(n):訊息節點 610:置信傳播圖 700、800、1200:奇偶檢查矩陣 810、910、920:碼字 820:校驗子集合 830、840、1210、1220、1230:子矩陣群組 831~833、841~843:子矩陣 911~913、921~923:偏移群組 1001:校驗權重集合 1002、1003、1101~1108:向量 1201:最小值集合10: Memory storage device 11: Host system 110: system bus 111: processor 112: random access memory 113: read-only memory 114: Data transfer interface 12: Input/output (I/O) device 20: motherboard 201: pen drive 202: memory card 203: Solid State Drive 204: Wireless memory storage device 205: Global Positioning System Module 206: network interface card 207: wireless transmission device 208: keyboard 209: Screen 210: Horn 32: SD card 33: CF card 34: Embedded storage device 341: Embedded multimedia card 342: Embedded multi-chip package storage device 402: Connect the interface unit 404: Memory control circuit unit 406: rewritable non-volatile memory module 502: Memory management circuit 504: Host interface 506: Memory interface 508: Error checking and correcting circuit 510: Buffer memory 512: Power management circuit 5081: decoder 5082: encoder 581: Decoding controller 582: Buffer 583: Check the node circuit 584: Variable node circuit 585, 585’: replacement circuit 586: syndrome calculation circuit 587: Terminate circuit S511, S512, S513, S514, S515, S516: flow steps of the decoder design method X1~X8: input terminal Y1~Y8: output terminal 5851, 5851’: replacement road 5851’(0)~5851’(2), 5851(1)~5851(2): replacement layer 590'(1)~590'(8), 591(1)~591(8), 592(1)~592(8), 591'(1)~591'(8), 592'(1)~ 592'(8): Node V(1)~V(N), IV(1)~IV(N): initial variable group 1410(1)~1410(M): Sub-matrix group IW_591(1), CW_591(1), OW1_591(1), OW2_591(1), CW_592(1), OW1_592(1), OW2_592(1): routing line 601(1)~601(k): parity node 602(1)~602(n): message node 610: Confidence map 700, 800, 1200: parity check matrix 810, 910, 920: codeword 820: syndrome set 830, 840, 1210, 1220, 1230: Sub-matrix group 831~833, 841~843: Sub-matrix 911~913, 921~923: Offset group 1001: Check weight set 1002, 1003, 1101~1108: vector 1201: minimum set
圖1是根據本發明的一實施例所繪示的主機系統、記憶體儲存裝置及輸入/輸出(I/O)裝置的示意圖。 圖2是根據本發明的另一實施例所繪示的主機系統、記憶體儲存裝置及I/O裝置的示意圖。 圖3是根據本發明的另一實施例所繪示的主機系統與記憶體儲存裝置的示意圖。 圖4是根據本發明的一實施例所繪示的記憶體儲存裝置的概要方塊圖。 圖5A是根據本發明的一實施例所繪示的記憶體控制電路單元的概要方塊圖。 圖5B是根據本發明的一實施例所繪示的記憶體控制電路單元的錯誤檢查與校正電路的方塊示意圖。 圖5C是根據本發明的一實施例所繪示的錯誤檢查與校正電路的解碼器的方塊示意圖。 圖5D是根據本發明的一實施例所繪示的解碼器設計方法的流程圖。 圖5E是根據本發明的一實施例所繪示的解碼器的置換電路的第一置換網路的示意圖。 圖5F是根據本發明的一實施例所繪示的解碼器的置換電路的第二置換網路的示意圖。 圖5G是根據本發明的一實施例所繪示的解碼器的置換電路的示意圖。 圖6是根據本發明的一實施例所繪示的低密度奇偶檢查碼之置信傳播(belief propagation)的示意圖。 圖7是根據本發明的一實施例所繪示的奇耦檢查矩陣的示意圖。 圖8是根據本發明的一實施例所繪示的奇偶檢查程序的示意圖。 圖9是根據本發明的一實施例所繪示的獲得對應於奇偶檢查程序之校驗子集合的示意圖。 圖10與圖11是根據本發明的另一實施例所繪示的獲得對應於位元翻轉演算法之校驗權重的示意圖。 圖12與圖13是根據本發明的另一實施例所繪示的獲得對應於最小值-總和演算法之最小值集合的示意圖。 圖14A是根據本發明的一實施例所繪示的經由具有對應偶數移位類型檢查矩陣的所提供的第二置換網路的置換電路所執行的變量群組的移位操作的示意圖。 圖14B是根據本發明的一實施例所繪示的經由具有對應一般移位類型檢查矩陣的傳統置換網路的置換電路所執行的變量群組的移位操作的示意圖。 圖15是根據先前技術所繪示的解碼器的置換電路的傳統的置換網路的示意圖。 圖16A是根據先前技術所繪示的對應一般移位類型檢查矩陣的傳統的置換網路移位範圍的示意圖。 圖16B是根據本發明的一實施例所繪示的對應偶數移位類型檢查矩陣的所提供的置換網路移位範圍的示意圖。 圖16C是根據本發明的一實施例所繪示的對應奇數移位類型檢查矩陣的所提供的置換網路移位範圍的示意圖。 圖17是根據本發明的一實施例所繪示的在所提供的置換電路的第二置換網路中的多個選擇器與連接至所述多個選擇器的路由線的連接關係的示意圖。FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an embodiment of the invention. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another embodiment of the invention. FIG. 3 is a schematic diagram of a host system and a memory storage device according to another embodiment of the invention. 4 is a schematic block diagram of a memory storage device according to an embodiment of the invention. 5A is a schematic block diagram of a memory control circuit unit according to an embodiment of the invention. 5B is a block diagram of an error checking and correcting circuit of a memory control circuit unit according to an embodiment of the invention. 5C is a block diagram of a decoder of an error checking and correcting circuit according to an embodiment of the invention. 5D is a flowchart of a decoder design method according to an embodiment of the invention. 5E is a schematic diagram of a first replacement network of the replacement circuit of the decoder according to an embodiment of the invention. 5F is a schematic diagram of a second replacement network of the replacement circuit of the decoder according to an embodiment of the invention. 5G is a schematic diagram of a replacement circuit of a decoder according to an embodiment of the invention. FIG. 6 is a schematic diagram of belief propagation of a low-density parity check code according to an embodiment of the invention. 7 is a schematic diagram of the odd-coupling check matrix according to an embodiment of the invention. 8 is a schematic diagram of a parity check procedure according to an embodiment of the invention. FIG. 9 is a schematic diagram of obtaining a parity set corresponding to a parity check procedure according to an embodiment of the invention. 10 and 11 are schematic diagrams of obtaining check weights corresponding to a bit flip algorithm according to another embodiment of the invention. 12 and 13 are schematic diagrams of obtaining a minimum value set corresponding to the minimum value-sum algorithm according to another embodiment of the present invention. 14A is a schematic diagram of a shift operation of a variable group performed by a replacement circuit of a second replacement network provided with a check matrix corresponding to an even shift type according to an embodiment of the present invention. 14B is a schematic diagram of a shift operation of a variable group performed by a replacement circuit of a conventional replacement network with a check matrix corresponding to a general shift type according to an embodiment of the invention. 15 is a schematic diagram of a conventional replacement network of a replacement circuit of a decoder according to the prior art. FIG. 16A is a schematic diagram of a conventional displacement network shift range corresponding to a general shift type check matrix according to the prior art. 16B is a schematic diagram illustrating the displacement range of the replacement network provided by the check matrix corresponding to the even-shift type according to an embodiment of the invention. 16C is a schematic diagram illustrating the displacement range of the replacement network provided by the check matrix corresponding to the odd shift type according to an embodiment of the invention. 17 is a schematic diagram illustrating a connection relationship between a plurality of selectors in the second replacement network of the provided replacement circuit and a routing line connected to the plurality of selectors according to an embodiment of the present invention.
S511、S512、S513、S514、S515、S516:解碼器設計方法的流程步驟 S511, S512, S513, S514, S515, S516: flow steps of the decoder design method
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