CN109657360A - A kind of modeling method and view system towards GPU chip hardware framework - Google Patents
A kind of modeling method and view system towards GPU chip hardware framework Download PDFInfo
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- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The embodiment of the invention provides the modeling methods and view system of a kind of Graphics-oriented processing unit GPU chip architecture top layer hardware.The modeling method includes modeling TLM method according to unitive search and transaction-level, carries out transaction-level modeling to the hardware structure top layer of the GPU chip.The view system includes: host interface unit, graphics pipeline unit, frame buffering cache unit, texture cache unit, display control unit, AXI bus crossbar switch, the first DDR controller and the second DDR controller.
Description
Technical field
The present invention relates to computer hardware modeling technique field more particularly to a kind of building towards GPU chip hardware framework
Mould method and view system.
Background technique
As that graphically applies is continuously increased, central processing unit (Central Processing is depended merely in early days
Unit, CPU) solution that carries out graphic plotting has been difficult to meet the graphics process demand that achievement and technology increase, figure
Processor (Graphic Processing Unit, GPU) comes into being.From Nvidia in 1999 issue first item GPU product to
The present, the development of GPU technology mainly experienced fixed function flow line stage, separation stainer framework stage, unified stainer frame
Structure stage, graphics capability are constantly promoted, and application field also gradually expands to general-purpose computations neck from initial graphic plotting
Domain.GPU assembly line high speed, parallel feature and flexible programmability, provide for graphics process and universal parallel calculating
Good operation platform.
For be similar to GPU as VLSI chip software/hardware framework, design, how to complete from
The leap that traditional description document is realized to hardware RTL circuit, become during engineering practice one it is important, anxious to
It solves the problems, such as.
Summary of the invention
The problem of based on background technique, it is provided by the invention it is a kind of based on UML towards GPU chip architecture top layer
The view system of hardware is able to solve the IC system framework stage quick representation function, structure the problem of.
In a first aspect, the present invention provides a kind of modeling method of Graphics-oriented processing unit GPU chip hardware framework, root
TLM method is modeled according to unitive search and transaction-level, transaction-level modeling is carried out to the hardware structure top layer of GPU chip.
Optionally, method is applied to the view system towards GPU chip hardware framework, and view system includes host interface
Unit 1, graphics pipeline unit 2, frame buffering cache unit 3, texture cache unit 4, display control unit 5, AXI bus are intersected
Switch 6, the first DDR controller 7 and the second DDR controller 8, method further include:
The OpenGL function command that 1 receiving host of host interface unit is sent, by being solved to OpenGL function command
Analysis obtains graph command, and graph command is sent to graphics pipeline unit 2；
Graphics pipeline unit 2 calculates graph data according to graph command, and the figure that will need to show on the screen
Graphic data is sent to AXI bus crossbar switch 6；
AXI bus crossbar switch 6 is by the AXI from display control unit 5, host interface unit 1 and graphics pipeline unit 2
Bus access is converted into register configuration and data channel access to the first DDR controller 7, the second DDR controller 8；
Display control unit 5 obtains screen data to be shown by access AXI bus crossbar switch 6, and to data into
Row display；
First DDR controller 7 and the second DDR controller 8 are by the register configuration sum number from AXI bus crossbar switch 6
According to channel access, it is converted into the interface read and write access of DDR memory.
Optionally, graph command includes at least:
Graphic drawing commands, graphing capability order and graphic register resource visit order.
Second aspect includes host interface list the present invention provides a kind of view system towards GPU chip hardware framework
Member 1, graphics pipeline unit 2, frame buffering cache unit 3, texture cache unit 4, display control unit 5, AXI bus intersection are opened
Close the 6, first DDR controller 7 and the second DDR controller 8；
Host interface unit 1 obtains graph command, and by figure for parsing the OpenGL function command of host transmission
Order is sent to graphics pipeline unit 2；
Graphics pipeline unit 2 for calculating graph data according to graph command, and will need to show on the screen
Graph data be sent to AXI bus crossbar switch 6；
AXI bus crossbar switch 6, for display control unit 5, host interface unit 1 and graphics pipeline unit 2 will to be come from
AXI bus access, be converted into the visit of the register configuration and data channel of the first DDR controller 7, the second DDR controller 8
It asks；
Display control unit 5, for obtaining screen data to be shown, and logarithm by access AXI bus crossbar switch 6
According to being shown；
First DDR controller 7 and the second DDR controller 8, for by from AXI bus register configuration and data lead to
Road access, is converted into the interface read and write access of DDR memory；
Frame buffers cache unit 3, for storing the mirror image of DDR0 frame interior buffer data；
Texture cache unit 4, for storing the mirror image of DDR0 inner vein buffer data.
Optionally, host interface unit 1 includes the port host2PcieCfgExport, the port and Host's
The port host2PcieCfgPort carries out connected, is communicated between port by PcieCfgIf interface；
Host interface unit 1 includes the port pcie2HostMemPort, the port and Host's
The port pcie2HostMemExport carries out connected, is communicated between port by Pcie2HostIf interface；
Host interface unit 1 includes the port cmd2RomPort, the port the cmd2RomExport progress of the port and ROM
It is connected, is communicated between port by RomReadIf interface；
Host interface unit 1 includes the port cmd2SguGraphPort, the port and graphics pipeline unit 2
The port cmd2SguGraphExport carries out connected, is communicated between port by Cmd2SguGraphIf interface；
Host interface unit 1 include the port rou2PcieIntExport, the port spmu2PcieIntExport,
The port jsu2PcieIntExport, the port geu2PcieIntExport, respectively successively with graphics pipeline unit 2
The port rou2PcieIntPort, the port spmu2PcieIntPort, the port jsu2PcieIntPort, geu2PcieIntPort
Port carries out connected, is communicated between above-mentioned port by PcieBackendIntIf interface；
Host interface unit 1 includes the port archRegPort, the port and graphics pipeline unit 2
The port archRegExport carries out connected, is communicated between port by PcieBackendRegIf interface；
Host interface unit 1 includes the port dma2AxiPort, the port cmd2AxiPort, cmdIcache2AxiPort
The successively dma2AxiExport with AXI bus crossbar switch 6 is distinguished in port, the port cmdDcache2AxiPort, above-mentioned port
Port, the port cmd2AxiExport, the port cmdIcache2AxiExport, the port cmdDcache2AxiExport carry out phase
Even, it is communicated between port by AxiMasterIf interface；
Host interface unit 1 includes the port dcArchRegPort, the port and display control unit 5
The port dcArchRegExport carries out connected, is communicated between port by PcieBackendRegIf interface.
Optionally, graphics pipeline unit 2 includes the port usa2AxiPort, the port and AXI bus crossbar switch 6
The port usa2AxiExport is connected, and is communicated between port by AxiMasterIf interface；
Graphics pipeline unit 2 includes the port frameCachePort, and the port and frame buffer cache unit 3
The port frameCacheExport is connected, and is communicated between port by FrameCacheIf interface；
Graphics pipeline unit 2 includes the port texCachePort, and the port and texture buffer cache unit
The port texCacheExport is connected, and is communicated between port by TextureCacheIf interface.
Optionally, display control unit 5 includes the port dc2AxiPort, the port and AXI bus crossbar switch 6
The port dc2AxiExport is connected, and is communicated between port by AxiMasterIf interface；
Display control unit 5 includes the port displayPort, the port displayExport of the port and Display
It is connected, is communicated between port by DisplayIf interface.
Optionally, frame buffering cache unit 3 includes the port pCache2AxiPort, which intersects out with AXI bus
The port pCache2AxiExport for closing 6 carries out connected, is communicated between above-mentioned port by AxiMasterIf interface.
Optionally, texture buffering cache unit includes the port tCache2AxiPort, which intersects with AXI bus
The port tCache2AxiExport of switch 6 carries out connected, is communicated between port by AxiMasterIf interface.
Optionally, the first DDR controller 7 includes the port axiSlaveExport, the port and AXI bus crossbar switch
6 [0] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface；
First DDR controller 7 includes the port ddrPort, which is connected with the port ddrExport of DDR0, port
Between communicated by DdrAccessIf interface.
Optionally, the second DDR controller 8 includes the port axiSlaveExport, the port and AXI bus crossbar switch
6 [1] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface；
Second DDR controller 8 includes the port ddrPort, which is connected with the port ddrExport of DDR1, port
Between communicated by DdrAccessIf interface.
Technical solution provided in an embodiment of the present invention be able to solve IC system framework stage quick representation function,
The problem of structure, compensates for the huge wide gap between system specification specification and the realization of hardware RTL circuit, certainly convenient for system architecture
Constantly refinement forms hardware RTL circuit downwards on top, is convenient for software and hardware personnel co-ordination, reduces unnecessary iteration.Based on UML
GPU chip architecture top layer hardware TLM model, can also be according to graphics view automatic code generating frame.As it can be seen that the present invention can
The technical effect reached includes:
1, using UML Unified Modeling Language, can be got rid of by view conventional text describe document inaccuracy and
Ambiguity, convenient for the exchange of technology between project team member；
2, it is modeled using the function call communication mode transaction-level of TLM, avoids letter cumbersome between hardware circuit module
Number connection description, can quickly to model carry out adaptation；
3, model through the invention can be suitable for rapid discovery, assessment GPU large scale integrated circuit hardware structure
The system-level architecture of integrated circuit early stage is designed and developed；
4, model through the invention can provide exploitation input for the TLM modelling of project later period.
Detailed description of the invention
Fig. 1 is the GPU chip architecture top layer hardware TLM model structure block diagram the present invention is based on UML.
Specific embodiment
In the following with reference to the drawings and specific embodiments, technical solution of the present invention is clearly and completely stated.Obviously,
The embodiment stated is only a part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention,
Those skilled in the art are not making creative work premise every other embodiment obtained, belong to guarantor of the invention
Protect range.
In the present invention, in order to shorten from system architecture document to hardware register transmitting stage (Register Transfer
Level, RTL) circuit realize between huge wide gap, it is necessary between the two stages use a kind of advanced modeling language pair
The function of entire circuit system, framework are described, at the same cannot fall into again many and diverse signal sequence of hardware circuit, gate circuit it
In.
It should be noted that transaction-level model (Transaction Level Models, TLM) is more higher than RTL level
Abstraction level, this rank can quickly be established according to the Elementary Function specification of system hardware executable specification, quickly creation
System model.By the way that timing details is added wherein, it can be estimated that performance, the structure of searching system of system.
You need to add is that UML (Unified Modeling Language) is also known as Unified Modeling Language or standard modeling
Language begins at OMG standard in 1997, it is the graphical language of a support model and software system development, is
All stages of software development provide modelling and visualization is supported.
Embodiment one
A kind of modeling method of Graphics-oriented processing unit GPU chip hardware framework, it is characterised in that:
TLM method is modeled according to unitive search and transaction-level, thing is carried out to the hardware structure top layer of GPU chip
Grade of being engaged in modeling.
Preferably, method is applied to the view system towards GPU chip hardware framework, and view system includes host interface
Unit 1, graphics pipeline unit 2, frame buffering cache unit 3, texture cache unit 4, display control unit 5, AXI bus are intersected
Switch 6, the first DDR controller 7 and the second DDR controller 8, method further include:
The OpenGL function command that 1 receiving host of host interface unit is sent, by being solved to OpenGL function command
Analysis obtains graph command, and graph command is sent to graphics pipeline unit 2；
Graphics pipeline unit 2 calculates graph data according to graph command, and the figure that will need to show on the screen
Graphic data is sent to AXI bus crossbar switch 6；
AXI bus crossbar switch 6 is by the AXI from display control unit 5, host interface unit 1 and graphics pipeline unit 2
Bus access is converted into register configuration and data channel access to the first DDR controller 7, the second DDR controller 8；
Display control unit 5 obtains screen data to be shown by access AXI bus crossbar switch 6, and to data into
Row display；
First DDR controller 7 and the second DDR controller 8 are by the register configuration sum number from AXI bus crossbar switch 6
According to channel access, it is converted into the interface read and write access of DDR memory.
Preferably, graph command includes at least: Graphic drawing commands, graphing capability order and the access of graphic register resource
Order.
Embodiment two
As shown in Figure 1, the embodiment of the invention provides a kind of view system towards GPU chip hardware framework, view system
System includes that host interface unit 1, graphics pipeline unit 2, frame buffer cache unit 3, texture cache unit 4, display control list
Member 5, AXI bus crossbar switch 6, the first DDR controller 7 and the second DDR controller 8；
The specific structure and function of each module is described in detail below:
Host interface unit 1 obtains graph command, and by figure for parsing the OpenGL function command of host transmission
Order is sent to graphics pipeline unit 2；
Graphics pipeline unit 2 for calculating graph data according to graph command, and will need to show on the screen
Graph data be sent to AXI bus crossbar switch 6；
AXI bus crossbar switch 6, for display control unit 5, host interface unit 1 and graphics pipeline unit 2 will to be come from
AXI bus access, be converted into the visit of the register configuration and data channel of the first DDR controller 7, the second DDR controller 8
It asks；
Display control unit 5, for obtaining screen data to be shown, and logarithm by access AXI bus crossbar switch 6
According to being shown；
First DDR controller 7 and the second DDR controller 8, for by from AXI bus register configuration and data lead to
Road access, is converted into the interface read and write access of DDR memory；
Frame buffers cache unit 3, for storing the mirror image of DDR0 frame interior buffer data；
Texture cache unit 4, for storing the mirror image of DDR0 inner vein buffer data.
Preferably, host interface unit 1 includes the port host2PcieCfgExport, the port and Host's
The port host2PcieCfgPort carries out connected, is communicated between port by PcieCfgIf interface；
Host interface unit 1 includes the port pcie2HostMemPort, the port and Host's
The port pcie2HostMemExport carries out connected, is communicated between port by Pcie2HostIf interface；
Host interface unit 1 includes the port cmd2RomPort, the port the cmd2RomExport progress of the port and ROM
It is connected, is communicated between port by RomReadIf interface；
Host interface unit 1 includes the port cmd2SguGraphPort, the port and graphics pipeline unit 2
The port cmd2SguGraphExport carries out connected, is communicated between port by Cmd2SguGraphIf interface；
Host interface unit 1 include the port rou2PcieIntExport, the port spmu2PcieIntExport,
The port jsu2PcieIntExport, the port geu2PcieIntExport, respectively successively with graphics pipeline unit 2
The port rou2PcieIntPort, the port spmu2PcieIntPort, the port jsu2PcieIntPort, geu2PcieIntPort
Port carries out connected, is communicated between above-mentioned port by PcieBackendIntIf interface；
Host interface unit 1 includes the port archRegPort, the port and graphics pipeline unit 2
The port archRegExport carries out connected, is communicated between port by PcieBackendRegIf interface；
Host interface unit 1 includes the port dma2AxiPort, the port cmd2AxiPort, cmdIcache2AxiPort
The successively dma2AxiExport with AXI bus crossbar switch 6 is distinguished in port, the port cmdDcache2AxiPort, above-mentioned port
Port, the port cmd2AxiExport, the port cmdIcache2AxiExport, the port cmdDcache2AxiExport carry out phase
Even, it is communicated between port by AxiMasterIf interface；
Host interface unit 1 includes the port dcArchRegPort, the port and display control unit 5
The port dcArchRegExport carries out connected, is communicated between port by PcieBackendRegIf interface.
Preferably, graphics pipeline unit 2 includes the port usa2AxiPort, the port and AXI bus crossbar switch 6
The port usa2AxiExport is connected, and is communicated between port by AxiMasterIf interface；
Graphics pipeline unit 2 includes the port frameCachePort, and the port and frame buffer cache unit 3
The port frameCacheExport is connected, and is communicated between port by FrameCacheIf interface；
Graphics pipeline unit 2 includes the port texCachePort, and the port and texture buffer cache unit
The port texCacheExport is connected, and is communicated between port by TextureCacheIf interface.
Preferably, display control unit 5 includes the port dc2AxiPort, the port and AXI bus crossbar switch 6
The port dc2AxiExport is connected, and is communicated between port by AxiMasterIf interface；
Display control unit 5 includes the port displayPort, the port displayExport of the port and Display
It is connected, is communicated between port by DisplayIf interface.
Preferably, frame buffering cache unit 3 includes the port pCache2AxiPort, which intersects out with AXI bus
The port pCache2AxiExport for closing 6 carries out connected, is communicated between above-mentioned port by AxiMasterIf interface.
Preferably, texture buffering cache unit includes the port tCache2AxiPort, which intersects with AXI bus
The port tCache2AxiExport of switch 6 carries out connected, is communicated between port by AxiMasterIf interface.
Preferably, the first DDR controller 7 includes the port axiSlaveExport, the port and AXI bus crossbar switch
6 [0] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface；
First DDR controller 7 includes the port ddrPort, which is connected with the port ddrExport of DDR0, port
Between communicated by DdrAccessIf interface.
Preferably, the second DDR controller 8 includes the port axiSlaveExport, the port and AXI bus crossbar switch
6 [1] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface；
Second DDR controller 8 includes the port ddrPort, which is connected with the port ddrExport of DDR1, port
Between communicated by DdrAccessIf interface.
Technical solution provided in an embodiment of the present invention be able to solve IC system framework stage quick representation function,
The problem of structure, compensates for the huge wide gap between system specification specification and the realization of hardware RTL circuit, certainly convenient for system architecture
Constantly refinement forms hardware RTL circuit downwards on top, is convenient for software and hardware personnel co-ordination, reduces unnecessary iteration.Based on UML
GPU chip architecture top layer hardware TLM model, can also be according to graphics view automatic code generating frame.As it can be seen that the present invention can
The technical effect reached includes:
1, using UML Unified Modeling Language, can be got rid of by view conventional text describe document inaccuracy and
Ambiguity, convenient for the exchange of technology between project team member；
2, it is modeled using the function call communication mode transaction-level of TLM, avoids letter cumbersome between hardware circuit module
Number connection description, can quickly to model carry out adaptation；
3, model through the invention can be suitable for rapid discovery, assessment GPU large scale integrated circuit hardware structure
The system-level architecture of integrated circuit early stage is designed and developed；
4, model through the invention can provide exploitation input for the TLM modelling of project later period.
The OpenGL function command parsing from host Host is classified as in conclusion host interface unit 1 is realized
Graphic drawing commands, graphing capability order and graphic register resource visit order, and these three types order is sent to figure tube
Line unit 2；Host interface unit 1, which is realized, passes to graphics pipeline unit 2 for the graph data from host Host or AXI is total
Line crossbar switch 6；
Graphics pipeline unit 2, which is realized, counts graph data according to the graph command from host interface unit 1
It calculates, and the graph data for needing to show on the screen is sent to AXI bus crossbar switch 6；
AXI bus crossbar switch 6 realizes will be from AXI main equipment (including display control unit 5, host interface unit 1
With graphics pipeline unit 2) AXI bus access, be converted into AXI from equipment (including the first DDR controller 7, the 2nd DDR control
Device 8 processed) register space or mem space access；
Display control unit 5, which is realized, obtains screen data to be shown by access AXI bus crossbar switch 6, and will
Data are sent to Display and are shown；
First DDR controller 7, the second DDR controller 8, which realize, to be accessed from the read-write operation of AXI bus, are converted into
The interface read and write access of DDR memory；
It should be noted that the interface service that intermodule communication is included is described as follows:
Host interface unit 1 includes the port host2PcieCfgExport, and PcieCfgIf interface provides Write_
Architect_Register, Read_Architect_Register service；
Host interface unit 1 includes the port pcie2HostMemPort, and Pcie2HostIf interface provides Write_
Host_Mem, Read_Host_Mem service；
Host interface unit 1 includes the port cmd2RomPort, and RomReadIf interface provides Read service；
Host interface unit 1 includes the port cmd2SguGraphPort, and cmd2SguGraphIf interface provides Get_
Graph_Draw_Service、Get_Graph_Func_Service、Get_Graph_Reg_Service、Put_Graph_
Draw_Command, Put_Graph_Function_Code, Put_Graph_Reg_Access, Set_Cmd_Status service；
Host interface unit 1 includes the port cmd2SpmuPort, and cmd2SpmuIf interface provides Report_
Exception service；
Host interface unit 1 include the port rou2PcieIntExport, the port spmu2PcieIntExport,
The port jsu2PcieIntExport, the port geu2PcieIntExport, wherein PcieBackendIntIf interface provides
Report_Interrupt service；
Host interface unit 1 includes the port archRegPort, and PcieBackendRegIf interface provides Arch_
Reg_Read, Arch_Reg_Write service；
Host interface unit 1 includes the port dma2AxiPort, the port cmd2AxiPort, cmdIcache2AxiPort
Port, the port cmdDcache2AxiPort, AxiMasterIf interface provide Request_Bus, Release_Bus, Read_
Bus, Write_Bus service；
Host interface unit 1 includes the port dcArchRegPort, and PcieBackendRegIf interface provides Arch_
Reg_Read, Arch_Reg_Write service；
The AxiMasterIf interface of graphics pipeline unit 2 provide Request_Bus, Release_Bus, Read_Bus,
Write_Bus service；
Display control unit 5 includes the port dc2AxiPort, AxiMasterIf interface provide Request_Bus,
Release_Bus, Read_Bus, Write_Bus service；
Display control unit 5 includes the port displayPort, the port the displayExport phase with Display
Even, it is communicated between port by DisplayIf interface.Wherein, DisplayIf interface provides Refresh_Screen clothes
Business；
First DDR controller 7 includes the port axiSlaveExport, with AXI bus crossbar switch 6
[0] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface.Wherein, AxiSlaveIf connects
Mouth provides Read_Slave, Write_Slave service；
First DDR controller 7 includes the port ddrPort, is connected with the port ddrExport of DDR0, between port
It is communicated by DdrAccessIf interface.Wherein, DdrAccessIf interface provides Read, Write service；
Second DDR controller 8 includes the port axiSlaveExport, with AXI bus crossbar switch 6
[1] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface.Wherein, AxiSlaveIf connects
Mouth provides Read_Slave, Write_Slave service；
Second DDR controller 8 includes the port ddrPort, is connected with the port ddrExport of DDR1, between port
It is communicated by DdrAccessIf interface.Wherein, DdrAccessIf interface provides Read, Write service；
Finally it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that；It still may be used
To modify to the technical solution that foregoing embodiments are recorded or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit and model of technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution
It encloses.
The method that the present invention uses is to carry out transaction-level modeling to GPU top layer hardware structure using UML view language, is avoided
Hardware structure is described using traditional documents form to be easy to cause the inaccuracy of verbal description and ambiguity while also avoiding hardware
The cumbersome circuit signal design of bottom, can be with the framework of the extensive hardware system of rapid evaluation, suitable for integrated circuit early stage
System-level architecture is designed and developed.
Claims (10)
1. a kind of modeling method of Graphics-oriented processing unit GPU chip hardware framework, it is characterised in that:
TLM method is modeled according to unitive search and transaction-level, thing is carried out to the hardware structure top layer of the GPU chip
Grade of being engaged in modeling.
2. the method according to claim 1, wherein the method is applied to towards GPU chip hardware framework
View system, the view system include, host interface unit (1), graphics pipeline unit (2), frame buffering cache unit (3),
Texture cache unit (4), display control unit (5), AXI bus crossbar switch (6), the first DDR controller (7) and the 2nd DDR
Controller (8), the method also includes:
The OpenGL function command that host interface unit (1) receiving host is sent, by the OpenGL function command
It carries out parsing and obtains graph command, the graph command is sent to the graphics pipeline unit (2)；
The graphics pipeline unit (2) calculates graph data according to the graph command, and will need to show on the screen
The graph data shown is sent to the AXI bus crossbar switch (6)；
The AXI bus crossbar switch (6) will be from the display control unit (5), the host interface unit (1) and described
The AXI bus access of graphics pipeline unit (2) is converted into first DDR controller (7), second DDR controller
(8) register configuration and data channel access；
The display control unit (5) obtains screen data to be shown by the access AXI bus crossbar switch (6), and
The data are shown；
First DDR controller (7) and the second DDR controller (8) will be from the described of the AXI bus crossbar switch (6)
Register configuration and data channel access are converted into the interface read and write access of DDR memory.
3. according to the method described in claim 2, it is characterized in that, the graph command includes at least:
Graphic drawing commands, graphing capability order and graphic register resource visit order.
4. a kind of view system towards GPU chip hardware framework, it is characterised in that: the view system includes host interface
Unit (1), graphics pipeline unit (2), frame buffering cache unit (3), texture cache unit (4), display control unit (5),
AXI bus crossbar switch (6), the first DDR controller (7) and the second DDR controller (8)；
The host interface unit (1) obtains graph command, and by institute for parsing the OpenGL function command of host transmission
It states graph command and is sent to the graphics pipeline unit (2)；
The graphics pipeline unit (2) for being calculated according to the graph command graph data, and will need in screen
The graph data of upper display is sent to the AXI bus crossbar switch (6)；
The AXI bus crossbar switch (6), for the display control unit (5), the host interface unit (1) will to be come from
With the AXI bus access of the graphics pipeline unit (2), it is converted into first DDR controller (7), the 2nd DDR control
The register configuration and data channel access of device (8) processed；
The display control unit (5), for obtaining screen number to be shown by accessing the AXI bus crossbar switch (6)
According to, and the data are shown；
First DDR controller (7) and second DDR controller (8), for will be from the register configuration of AXI bus
With data channel access, it is converted into the interface read and write access of DDR memory；
The frame buffers cache unit (3), for storing the mirror image of the DDR0 frame interior buffer data；
The texture cache unit (4), for storing the mirror image of DDR0 inner vein buffer data.
5. view system according to claim 4, it is characterised in that:
The host interface unit (1) includes the port host2PcieCfgExport, the port and Host's
The port host2PcieCfgPort carries out connected, is communicated between port by PcieCfgIf interface；
The host interface unit (1) includes the port pcie2HostMemPort, the port and Host's
The port pcie2HostMemExport carries out connected, is communicated between port by Pcie2HostIf interface；
The host interface unit (1) includes the port cmd2RomPort, the port cmd2RomExport of the port and ROM into
Row is connected, and is communicated between port by RomReadIf interface；
The host interface unit (1) includes the port cmd2SguGraphPort, the port and the graphics pipeline unit (2)
The port cmd2SguGraphExport carry out connected, communicated between port by Cmd2SguGraphIf interface；
The host interface unit (1) include the port rou2PcieIntExport, the port spmu2PcieIntExport,
The port jsu2PcieIntExport, the port geu2PcieIntExport, respectively successively with the graphics pipeline unit (2)
The port rou2PcieIntPort, the port spmu2PcieIntPort, the port jsu2PcieIntPort, geu2PcieIntPort
Port carries out connected, is communicated between above-mentioned port by PcieBackendIntIf interface；
The host interface unit (1) includes the port archRegPort, the port and the graphics pipeline unit (2)
The port archRegExport carries out connected, is communicated between port by PcieBackendRegIf interface；
The host interface unit (1) include the port dma2AxiPort, the port cmd2AxiPort,
The port cmdIcache2AxiPort, the port cmdDcache2AxiPort, above-mentioned port respectively successively with AXI bus crossbar switch
(6) the port dma2AxiExport, the port cmd2AxiExport, the port cmdIcache2AxiExport,
The port cmdDcache2AxiExport carries out connected, is communicated between port by AxiMasterIf interface；
The host interface unit (1) includes the port dcArchRegPort, the port and display control unit 5
The port dcArchRegExport carries out connected, is communicated between port by PcieBackendRegIf interface.
6. view system according to claim 4, it is characterised in that:
The graphics pipeline unit (2) includes the port usa2AxiPort, the port and AXI bus crossbar switch (6)
The port usa2AxiExport is connected, and is communicated between port by AxiMasterIf interface；
The graphics pipeline unit (2) includes the port frameCachePort, and the port and frame buffer cache unit (3)
The port frameCacheExport is connected, and is communicated between port by FrameCacheIf interface；
The graphics pipeline unit (2) includes the port texCachePort, and the port and texture buffer cache unit
The port texCacheExport is connected, and is communicated between port by TextureCacheIf interface.
7. view system according to claim 4, it is characterised in that:
The graphics pipeline unit (2) includes the port dc2AxiPort, the port and AXI bus crossbar switch (6)
The port dc2AxiExport is connected, and is communicated between port by AxiMasterIf interface；
The graphics pipeline unit (2) includes the port displayPort, the end displayExport of the port and Display
Mouth is connected, and is communicated between port by DisplayIf interface.
8. view system according to claim 4, it is characterised in that:
Frame buffering cache unit (3) includes the port pCache2AxiPort, the port and AXI bus crossbar switch (6)
The port pCache2AxiExport carry out connected, communicated between above-mentioned port by AxiMasterIf interface.
9. view system according to claim 4, it is characterised in that:
The texture cache unit (4) includes the port tCache2AxiPort, the port and AXI bus crossbar switch (6)
The port tCache2AxiExport carries out connected, is communicated between port by AxiMasterIf interface.
10. view system according to claim 4, it is characterised in that:
First DDR controller (7) includes the port axiSlaveExport, the port and AXI bus crossbar switch (6)
[0] port axiSlavePort is connected, and is communicated between port by AxiSlaveIf interface；
First DDR controller (7) includes the port ddrPort, which is connected with the port ddrExport of DDR0, end
It is communicated between mouthful by DdrAccessIf interface.
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