CN109639241B - Non-inductance down-conversion frequency mixer - Google Patents
Non-inductance down-conversion frequency mixer Download PDFInfo
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- CN109639241B CN109639241B CN201811344489.9A CN201811344489A CN109639241B CN 109639241 B CN109639241 B CN 109639241B CN 201811344489 A CN201811344489 A CN 201811344489A CN 109639241 B CN109639241 B CN 109639241B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1441—Balanced arrangements with transistors using field-effect transistors
Abstract
The invention relates to an inductance-free down-conversion mixer, comprising: the device is provided with an input transconductance unit, a cross-coupling capacitor unit, a switch unit and a resistance load unit, wherein the input transconductance unit adopts different substrate voltage structures; the cross coupling capacitor unit forms a negative resistance at the source electrode of the switch unit so as to improve the linearity; the radio frequency input signal is amplified by the input transconductance unit, the parasitic capacitance is counteracted through the cross coupling capacitance unit, the radio frequency input signal is output to the switch unit to be mixed with the local oscillation signal, the output of the switch unit is connected with the resistance load unit, and the differential intermediate frequency output signal is output between the switch unit and the resistance load unit.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to an inductance-free down-conversion mixer.
Background
The mixer is one of the core circuits of the rf front end, and its circuit performance directly determines the overall performance of the rf front end. Linearity and conversion gain are important indicators for measuring the performance of a mixer. In the receiver, the mixer has a certain conversion gain, so that the difficulty of designing modules at all stages behind the mixer can be reduced, and the noise performance and the sensitivity of a system can be improved. The linearity determines the maximum signal strength that the mixer can handle. An active mixer can provide gain, and a typical structure is a Gilbert double balanced mixer, which has better port isolation and smaller area compared with a passive mixer followed by a transimpedance amplifier, but has the disadvantage of poor linearity.
The gain and linearity of the double-balanced mixer are mainly determined by the transconductance stage and the switching stage, and conventionally, an LC filter is added between the transconductance stage and the switching stage, but a large amount of chip area is consumed, and how to realize a mixer with high gain and high linearity by using fewer components and less area as much as possible is a hot spot of research in the industry.
Disclosure of Invention
The invention aims to provide an inductance-free down-conversion mixer which does not adopt an inductor and reduces the chip area as much as possible. The gain is high, and simultaneously, the linearity, the low noise and the reasonable power consumption are considered. The technical scheme of the invention is as follows:
an inductance-free downconversion mixer comprising: the circuit is provided with an input transconductance unit, a cross-coupling capacitor unit, a switch unit and a resistance load unit, and is characterized in that the input transconductance unit adopts different substrate voltage structures; the cross coupling capacitor unit forms a negative resistance at the source electrode of the switch unit so as to improve the linearity; the radio frequency input signal is amplified by the input transconductance unit, the parasitic capacitance is counteracted through the cross coupling capacitance unit, the radio frequency input signal is output to the switch unit to be mixed with the local oscillation signal, the output of the switch unit is connected with the resistance load unit, and the differential intermediate frequency output signal is output between the switch unit and the resistance load unit.
The input transconductance unit includes: a first transistor (M1), a second transistor (M2), a third transistor (M3), and a fourth transistor (M4);
wherein the gate of the first transistor (M1) is connected to the gate of the second transistor (M2), the first terminal of the first resistor (R1) and the radio frequency input (RF +);
the source of the second transistor (M2) is connected with the source of the first transistor (M1), the source of the third transistor (M3) and the source of the fourth transistor (M4);
the substrate of the second transistor (M2) is connected with the substrate of the third transistor (M3) and the first end of the third resistor (R3);
the gate of the third transistor (M3) is connected to the gate of the fourth transistor (M4), the first terminal of the second resistor (R2) and the radio frequency input (RF-).
The cross-coupling capacitance unit includes: a first capacitance (C1) and a second capacitance (C2);
wherein a first terminal of the first capacitor (C1) is connected to a radio frequency input terminal (RF +);
a second end of the first capacitor (C1) is connected with the drain of the third transistor (M3) and the drain of the fourth transistor (M4);
a first terminal of the second capacitance (C2) is connected to a radio frequency input (RF-);
the second terminal of the second capacitor (C2) is connected to the drain of the first transistor (M1) and the drain of the second transistor (M2).
The switching unit includes: a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), and an eighth transistor (M8);
wherein a gate of the fifth transistor (M5) is connected to the local oscillator input signal (LO +), a gate of the eighth transistor (M8), and a first end of the fifth resistor (R5);
the source of the fifth transistor (M5) is connected with the source of the sixth transistor (M6) and the second end of the second capacitor (C2);
the grid electrode of the sixth transistor (M6) is connected with the grid electrode of the seventh transistor (M7), the first end of a fourth resistor (R4) and the local oscillation signal (LO-);
the source of the seventh transistor (M7) is connected to the source of the eighth transistor (M8) and the second terminal of the first capacitor (C1).
The resistive load unit includes: a sixth resistor (R6) and a seventh resistor (R7);
wherein a first terminal of the sixth resistor (R6) is connected with a first terminal of the third capacitor (C3), a drain of the seventh transistor (M7) and a drain of the eighth transistor (M8);
a first terminal of the seventh resistor (R7) is connected to a first terminal of the fourth capacitor (C4), a drain of the fifth transistor (M5), and a drain of the sixth transistor (M6).
The second end of the first resistor (R1) and the second end of the second resistor (R2) are both connected with a first voltage source (V1);
a second terminal of the third resistor (R3) is connected to a second voltage source (V2);
a second terminal of the fourth resistor (R4) and a second terminal of the fifth resistor (R5) are both connected to a third voltage source (V3);
a second end of the sixth resistor (R6) and a second end of the seventh resistor (R7) are both connected to a fourth voltage source (V4);
the source of the second transistor (M2), the source of the third transistor (M3), the substrate of the first transistor (M1), the substrate of the fourth transistor (M4), the substrate of the fifth transistor (M5), the substrate of the sixth transistor (M6), the substrate of the seventh transistor (M7) and the substrate of the eighth transistor (M8) are all connected to ground;
a second end of the third capacitor (C3) is connected with an intermediate frequency output signal (IF +); the second terminal of the fourth capacitor (C4) is connected to the intermediate frequency output signal (IF-).
The first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), the fifth transistor (M5), the sixth transistor (M6), the seventh transistor (M7), and the eighth transistor (M8) are all NMOS transistors.
The fourth voltage source (V4) provides a DC bias voltage with a voltage value of 1.8V.
Compared with the prior art, the technical scheme of the embodiment of the invention has the beneficial effects that:
(1) the invention adopts the input transconductance units with different substrate voltages and combines the current injection and derivative superposition technology, thereby optimizing the noise and the linearity without increasing the power consumption;
(2) according to the invention, the cross-coupling capacitor unit is adopted, and the negative resistance is formed on the source electrode of the switch unit, so that the nonlinear influence of parasitic capacitance is counteracted, and the linearity is further improved;
(3) the invention does not adopt an inductor, and consumes small chip area.
(4) The invention adopts mainstream CMOS process, can be integrated with digital baseband circuit of CMOS process on the same chip, and is easy to realize system-on-chip integration.
(5) The invention is realized by adopting a deep submicron 0.18umCMOS process, is powered by 1.8V low power supply voltage and has lower power consumption.
Drawings
FIG. 1 is a circuit schematic of a down conversion mixer of the present invention;
FIG. 2 is a graph of simulation results of the conversion gain of the downconversion mixer of the present invention;
FIG. 3 is a graph of simulation results of the noise figure of the down conversion mixer of the present invention;
fig. 4 is a graph of simulation results of the linearity of the down-conversion mixer of the present invention.
Detailed Description
The embodiment of the utility model provides a through providing a no inductance down conversion mixer, solved the problem that exists among the prior art, how under the condition that does not use the inductance, simultaneously good gain and linearity performance. In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
The input transconductance unit includes: a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; wherein, the gate of the first transistor M1 is connected with the gate of the second transistor M2, the first end of the first resistor R1 and the radio frequency input terminal RF +; the source of the second transistor M2 is connected with the source of the first transistor M1, the source of the third transistor M3 and the source of the fourth transistor M4; the substrate of the second transistor M2 is connected with the substrate of the third transistor M3 and the first end of the third resistor R3; the gate of the third transistor M3 is connected to the gate of the fourth transistor M4, to the first terminal of the second resistor R2 and to the radio frequency input RF-.
In the embodiment of the present invention, the rf signal is applied to the gates of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, respectively, and the voltage signal is converted into the current signal. The substrates of the first transistor M1 and the fourth transistor M4 are grounded, the substrates of the second transistor M2 and the third transistor M3 are grounded at a voltage V2, and the gate voltages are both V1. The transconductance stage adopts double MOS tubes with different substrate voltages, combines the current injection and derivative superposition technology, and optimizes noise and linearity without increasing power consumption.
The cross-coupling capacitance unit includes: a first capacitor C1 and a second capacitor C2; wherein a first terminal of the first capacitor C1 is connected to a radio frequency input terminal RF +; a second end of the first capacitor C1 is connected to the drain of the third transistor M3 and the drain of the fourth transistor M4; a first terminal of the second capacitor C2 is RF-connected to a radio frequency input terminal; a second terminal of the second capacitor C2 is connected to the drain of the first transistor M1 and the drain of the second transistor M2.
In the embodiment of the invention, a second capacitor C2 is added to the drains of the first transistor M1 and the second transistor M2 and the gates of the third transistor M3 and the fourth transistor M4. A first capacitor C1 is added to the drains of the third transistor M3 and the fourth transistor M4 and the gates of the first transistor M1 and the second transistor M2. The first capacitor C1 and the second capacitor C2 constitute a cross-coupling capacitor. Negative impedance is formed at the insertion node, so that the influence of parasitic capacitance is counteracted, and nonlinearity of a cross conduit is improved, thereby improving the gain and the linearity of the mixer.
The switching unit includes: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the grid of the fifth transistor M5 is connected with the local oscillator input signal LO +, the grid of the eighth transistor M8 and the first end of the fifth resistor R5; the source of the fifth transistor M5 is connected with the source of the sixth transistor M6 and the second end of the second capacitor C2; the grid electrode of the sixth transistor M6 is connected with the grid electrode of the seventh transistor M7, the first end of the fourth resistor R4 and the local oscillation signal LO-; the source of the seventh transistor M7 is connected to the source of the eighth transistor M8 and the second terminal of the first capacitor C1.
In the embodiment of the present invention, in order to enable the switching unit to operate in a desired switching mode under a proper local oscillator signal, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are biased at the edge of the cut-off region, that is, the gate-source voltage is close to the threshold voltage. The switch pairs are alternately switched on under the control of the local oscillator signal, and the current generated by the input transconductance stage is periodically switched from one side to the other side.
The resistive load unit includes: a sixth resistor R6 and a seventh resistor R7; a first end of the sixth resistor R6 is connected to the first end of the third capacitor C3, the drain of the seventh transistor M7 and the drain of the eighth transistor M8; a first end of the seventh resistor R7 is connected to the first end of the fourth capacitor C4, the drain of the fifth transistor M5 and the drain of the sixth transistor M6.
In the embodiment of the invention, the sixth resistor R6 and the seventh resistor R7 are used as load units, and the resistors are used as loads, so that the structure is simple, and nonlinearity is not introduced. And has a wide bandwidth and is the most common form of load in a mixer.
Claims (3)
1. An inductance-free downconversion mixer comprising: the circuit is provided with an input transconductance unit, a cross-coupling capacitor unit, a switch unit and a resistance load unit, and is characterized in that the input transconductance unit adopts different substrate voltage structures; the cross coupling capacitor unit forms a negative resistance at the source electrode of the switch unit so as to improve the linearity; the radio frequency input signal is amplified by the input transconductance unit, the parasitic capacitance is counteracted through the cross coupling capacitance unit, the radio frequency input signal is output to the switch unit to be mixed with the local oscillation signal, the output of the switch unit is connected with the resistance load unit, and the differential intermediate frequency output signal is output between the switch unit and the resistance load unit;
the input transconductance unit includes: a first transistor (M1), a second transistor (M2), a third transistor (M3), and a fourth transistor (M4);
wherein the gate of the first transistor (M1) is connected to the gate of the second transistor (M2), the first terminal of the first resistor (R1) and the radio frequency input (RF +);
the source of the second transistor (M2) is connected with the source of the first transistor (M1), the source of the third transistor (M3) and the source of the fourth transistor (M4);
the substrate of the second transistor (M2) is connected with the substrate of the third transistor (M3) and the first end of the third resistor (R3);
the gate of the third transistor (M3) is connected with the gate of the fourth transistor (M4), the first end of the second resistor (R2) and the radio frequency input end (RF-);
the cross-coupling capacitance unit includes: a first capacitance (C1) and a second capacitance (C2);
wherein a first terminal of the first capacitor (C1) is connected to a radio frequency input terminal (RF +);
a second end of the first capacitor (C1) is connected with the drain of the third transistor (M3) and the drain of the fourth transistor (M4);
a first terminal of the second capacitance (C2) is connected to a radio frequency input (RF-);
a second terminal of the second capacitor (C2) is connected with the drain of the first transistor (M1) and the drain of the second transistor (M2);
the switching unit includes: a fifth transistor (M5), a sixth transistor (M6), a seventh transistor (M7), and an eighth transistor (M8);
wherein a gate of the fifth transistor (M5) is connected to the local oscillator input signal (LO +), a gate of the eighth transistor (M8), and a first end of the fifth resistor (R5);
the source of the fifth transistor (M5) is connected with the source of the sixth transistor (M6) and the second end of the second capacitor (C2);
the grid electrode of the sixth transistor (M6) is connected with the grid electrode of the seventh transistor (M7), the first end of a fourth resistor (R4) and the local oscillation signal (LO-);
a source of the seventh transistor (M7) is connected to a source of an eighth transistor (M8) and a second terminal of the first capacitor (C1);
the resistive load unit includes: a sixth resistor (R6) and a seventh resistor (R7);
wherein a first terminal of the sixth resistor (R6) is connected with a first terminal of the third capacitor (C3), a drain of the seventh transistor (M7) and a drain of the eighth transistor (M8);
a first end of the seventh resistor (R7) is connected with a first end of the fourth capacitor (C4), a drain of the fifth transistor (M5) and a drain of the sixth transistor (M6);
the second end of the first resistor (R1) and the second end of the second resistor (R2) are both connected with a first voltage source (V1);
a second terminal of the third resistor (R3) is connected to a second voltage source (V2);
a second terminal of the fourth resistor (R4) and a second terminal of the fifth resistor (R5) are both connected to a third voltage source (V3);
a second end of the sixth resistor (R6) and a second end of the seventh resistor (R7) are both connected to a fourth voltage source (V4);
the source of the second transistor (M2), the source of the third transistor (M3), the substrate of the first transistor (M1), the substrate of the fourth transistor (M4), the substrate of the fifth transistor (M5), the substrate of the sixth transistor (M6), the substrate of the seventh transistor (M7) and the substrate of the eighth transistor (M8) are all connected to ground;
a second end of the third capacitor (C3) is connected with an intermediate frequency output signal (IF +); the second terminal of the fourth capacitor (C4) is connected to the intermediate frequency output signal (IF-).
2. The mixer of claim 1, wherein the first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), the fifth transistor (M5), the sixth transistor (M6), the seventh transistor (M7), and the eighth transistor (M8) are all NMOS transistors.
3. The mixer of claim 1, wherein the fourth voltage source (V4) provides a dc bias voltage and has a voltage value of 1.8V.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811344489.9A CN109639241B (en) | 2018-11-13 | 2018-11-13 | Non-inductance down-conversion frequency mixer |
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| CN201811344489.9A CN109639241B (en) | 2018-11-13 | 2018-11-13 | Non-inductance down-conversion frequency mixer |
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| CN109639241A CN109639241A (en) | 2019-04-16 |
| CN109639241B true CN109639241B (en) | 2021-03-26 |
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| CN1806333A (en) * | 2003-06-12 | 2006-07-19 | 株式会社丰田自动织机 | Mixer circuit |
| CN103986450A (en) * | 2014-05-12 | 2014-08-13 | 华为技术有限公司 | Switch, tuner of antenna and radio frequency device |
| US9083423B2 (en) * | 2013-02-13 | 2015-07-14 | Kabushiki Kaisha Toshiba | Semiconductor circuit, D/A converter, mixer circuit, radio communication device, method for adjusting threshold voltage, and method for determining quality of transistor |
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| IT1294732B1 (en) * | 1997-09-15 | 1999-04-12 | Italtel Spa | IMAGE REJECTION SUBHARMONIC FREQUENCY CONVERTER MADE IN MICRO-STRIP, PARTICULARLY SUITABLE FOR USE IN |
| US6653885B2 (en) * | 2001-05-03 | 2003-11-25 | Peregrine Semiconductor Corporation | On-chip integrated mixer with balun circuit and method of making the same |
| KR100738394B1 (en) * | 2006-08-14 | 2007-07-12 | 삼성전기주식회사 | Device and method for generating chaotic signal |
| US8045944B2 (en) * | 2007-09-14 | 2011-10-25 | Qualcomm Incorporated | Offset correction for passive mixers |
| US7944298B2 (en) * | 2007-12-18 | 2011-05-17 | Qualcomm, Incorporated | Low noise and low input capacitance differential MDS LNA |
| US7911269B2 (en) * | 2009-01-19 | 2011-03-22 | Qualcomm Incorporated | Ultra low noise high linearity LNA for multi-mode transceiver |
| EP2339744A1 (en) * | 2009-12-16 | 2011-06-29 | The Swatch Group Research and Development Ltd. | Low-voltage mixer circuit for a UWB signal transmission device |
| CN102611392B (en) * | 2012-03-23 | 2014-10-29 | 北京航空航天大学 | Ultralow consumption current multiplexing mixer based on substrate bias |
| CN203278747U (en) * | 2013-01-25 | 2013-11-06 | 东南大学 | Low-consumption high-gain down-conversion mixer |
| CN104124923B (en) * | 2014-06-25 | 2017-04-05 | 中国电子科技集团公司第三十八研究所 | A kind of low-noise mixer circuit |
| EP3142250A1 (en) * | 2015-09-11 | 2017-03-15 | Catena Holding bv | Amplifier linearization |
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2018
- 2018-11-13 CN CN201811344489.9A patent/CN109639241B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1806333A (en) * | 2003-06-12 | 2006-07-19 | 株式会社丰田自动织机 | Mixer circuit |
| US9083423B2 (en) * | 2013-02-13 | 2015-07-14 | Kabushiki Kaisha Toshiba | Semiconductor circuit, D/A converter, mixer circuit, radio communication device, method for adjusting threshold voltage, and method for determining quality of transistor |
| CN103986450A (en) * | 2014-05-12 | 2014-08-13 | 华为技术有限公司 | Switch, tuner of antenna and radio frequency device |
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