CN109617412B - Boost system response speed conversion circuit based on PFM control and control method thereof - Google Patents

Boost system response speed conversion circuit based on PFM control and control method thereof Download PDF

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CN109617412B
CN109617412B CN201910032570.1A CN201910032570A CN109617412B CN 109617412 B CN109617412 B CN 109617412B CN 201910032570 A CN201910032570 A CN 201910032570A CN 109617412 B CN109617412 B CN 109617412B
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comparator
tube
output
output signal
voltage
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CN109617412A (en
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吴玉强
黄朝刚
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QX MICRO DEVICES CO Ltd
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QX MICRO DEVICES CO Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a response speed conversion circuit of a boosting system based on PFM control and a control method thereof, wherein the partial pressure of the voltage of the output end of the circuit is used as sampling voltage to be compared with the reference voltage of a comparator; the output signal of the comparator and the output signal of the on-time control circuit act on the PFM module, and the output signal of the PFM module and the output signal of the current zero-crossing comparator act on the drive circuit to control the on-off of the power tube or the rectifying tube; when the voltage of the output end is lower than the preset voltage, the power tube is conducted, the rectifying tube is cut off, the inductance stores energy, and the conduction time control circuit starts timing; after reaching the preset time, the on-time control circuit resets the PFM module to control the driving circuit, the power tube is cut off, the rectifying tube is conducted, and the inductor releases energy to the output end. Judging whether the load is light load or heavy load according to the duty ratio of the output signal of the current zero-crossing comparator or the output driving signal of the driving circuit, and reducing the bias current of the comparator when the load is light load; and increasing the bias current of the comparator during heavy load.

Description

Boost system response speed conversion circuit based on PFM control and control method thereof
Technical Field
The invention relates to the field of electronic circuits, in particular to a response speed conversion circuit of a boosting system based on PFM control and a control method thereof.
Background
With the continuous improvement of the integration level of the digital processing unit of the system on chip, for example, the DSP and the ARM are integrated into the same chip, the requirements on the load carrying capacity and the efficiency of the power supply system are higher and higher. In developing battery-powered portable electronic devices, low-power consumption products such as mobile phones, MP4, EBOOK, GPS, etc., if the power supply system is unreasonably designed, the architecture of the whole system, the functional combination of the products, the design of software, the power distribution architecture, etc. are affected. The portable products are in most cases powered by batteries, and the power management at the back end of the batteries has two implementations of DC/DC and LDO, and each has advantages and disadvantages. During normal operation, the DC/DC module can provide stable voltage for the system, and keeps high efficiency of self-conversion and low heat generation. LDOs have very low quiescent current, very low noise, and high PSRR (power supply ripple rejection ratio). With the increasing requirements of power supply conversion efficiency, output voltage ripple, on-load response speed, volume and the like, research on low-power consumption and high-speed DC/DC has become a focus of attention. In order to ensure efficient and reliable operation of electronic equipment, a power supply of the electronic equipment is required to have low standby power consumption, high light load efficiency and rapid load transient response speed, and meanwhile, the electronic equipment is small in size. Conventional pulse width modulation (Pulse Width Modulation, PWM) switching converter control techniques, such as voltage-type control and current-type control, fail to meet this requirement. The PFM (Pulse Frequency Modulation, PFM) control technique is a pulse frequency modulation control technique. The power switch tube of the switching converter is conducted in an effective time interval, and the control signal duty ratio is adjusted by controlling the turn-off time so as to maintain the stability of the output voltage. Compared with the traditional PWM control technology, the converter based on PFM control has the advantages of high light load efficiency, high transient response speed, simple control loop and the like, and is widely focused and studied in the industry and academia. However, the switching frequency of the system is always increased and maintained at about 100kHz to 200kHz due to the limitation of low standby power consumption, and if the system works at this frequency, the inductance and capacitance of the output capacitor are required to be increased for some systems requiring low voltage ripple, thus resulting in an increase in the cost of the system. However, in some compact and high-performance electronic products, the power supply is required to have small volume, small ripple wave and high transient response speed, and the integration level of the whole system is strictly limited, so that a small-volume chip ceramic capacitor and a small-volume chip inductor are required to be selected. However, the conventional solutions use large inductance and large capacitance to maintain low output ripple while maintaining low standby current, so that the overall cost of the system is increased and the volume is also large, thereby reducing the competitiveness of the market. Fig. 1 is a block diagram of a boost converter system based on PFM control, which operates according to the following principles: the output voltage VOUT obtains sampling voltage FB after the voltage division of feedback resistors R1 and R2, sampling voltage FB compares with reference voltage VREF, output of the comparator and output signals of the on-time control circuit reach PFM, output frequency of the PFM is changed, and then switching tube M2 and synchronous rectifying tube M1 are respectively controlled to be on and off through a driving circuit driver, so that duty ratio is changed, and accordingly output VOUT of the PFM boost converter achieves the effect of stabilizing voltage. the current through the zero comparator detects whether the current of the synchronous rectifying tube M1 crosses zero, and if so, the synchronous rectifying tube M1 is turned off to prevent the output VOUT from discharging the input VIN through the inductor.
Because the PFM controlled boost system requires extremely low quiescent current under standby or light load, the bias current designs of the comparator and the zero-crossing detection comparator are very small, so that the response speed of the two comparators is very slow, the working frequency of the system is limited, and larger inductance and larger output capacitance are required.
The disadvantages of the conventional technology are: the large inductance and the large capacitance are used for realizing low ripple, low standby current and strong carrying capacity, thus leading to the increase of the cost of the system, and the large volume of the system also limits the application in compact occasions, thereby reducing the competitiveness of the market.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and provides a boost system response speed conversion circuit which utilizes the output of a current zero-crossing comparator to judge the weight of a load, namely, the magnitude of bias current of the comparator can be changed according to the output of the current zero-crossing comparator, so that the response speed of a boost converter based on PFM control can be effectively improved, the high efficiency under the condition of no-load or light load can be maintained, the circuit is simple, the cost of the whole system can be greatly reduced, the working frequency of the system can be effectively improved, and the high efficiency based on PFM control can be maintained during light load. The invention further aims to provide a control method of the response speed conversion circuit of the boosting system, which can effectively improve the working frequency of the system and keep low static current in light load, can keep low ripple of output voltage by using a small inductor and a small output capacitor, and can distinguish whether the load is light load or heavy load by using an output signal of an internal current through a zero comparator, so that the bias current of the comparator is changed, the working frequency of the whole system can be up to 1MHz or higher in heavy load, the low static current and high efficiency can be ensured in light load, and the improvement of the working frequency of the system can be realized by using the small inductor and the small output capacitor, and can still keep the ripple of the small output voltage and be controlled based on PFM.
The technical solution of the invention is that the boost system response speed conversion circuit based on PFM control is characterized in that the circuit comprises: the voltage dividing circuit comprises a voltage input end, an inductor, a current zero-crossing comparator, a rectifying tube, a power tube, a driving circuit, a PFM module, a comparator, a voltage dividing resistor, an output capacitor and a conduction time control circuit, wherein the voltage division of the voltage of the output end of the circuit is used as sampling voltage to act on the comparator and is compared with the reference voltage of the comparator; the output signal of the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM, and the output signal of the PFM and the output signal of the current-through zero comparator jointly act on the driving circuit to control the on or off of the power tube or the rectifying tube; when the voltage of the output end is lower than the preset voltage, the power tube is conducted, the rectifying tube is cut off, the inductance stores energy, and the conduction time control circuit starts timing; after reaching the preset time, the conducting time control circuit resets the PFM module, and then controls the driving circuit to enable the power tube to be cut off, the rectifying tube to be conducted and the inductor to release energy to the output end of the circuit, at the moment, the load is judged to be light load or heavy load according to the output signal of the current zero-crossing comparator or the output driving signal of the driving circuit, and when the load is light load, the current zero-crossing comparator detects that the zero crossing of the inductance current or the duty ratio of the output driving signal of the driving circuit is very low, so that the bias current of the comparator is reduced; when the load is heavy, the zero-crossing of the inductance current is not detected by the current through zero comparator or the output driving signal of the driving circuit increases the bias current of the comparator.
As preferable: the circuit comprises: voltage input end V IN, inductance L, current zero-passing comparator, rectifying tube M 1, power tube M 2, driving circuit driver, PFM module, comparator, voltage dividing resistor R 1、R2, The output capacitor C OUT and the on-time control circuit also comprise an output capacitor internal resistance R ESR, wherein the rectifying tube M 1 is a PMOS tube and the power tube M 2 is an NMOS tube; The voltage input end V IN is grounded after passing through the inductance L, the source electrode and the drain electrode of the rectifying tube M 1, the internal resistance R ESR of the output capacitor and the output capacitor C OUT in sequence, The voltage input end V IN is grounded after passing through the inductor L and the power tube M 2 in sequence, the drain electrode of the power tube M 2 is connected with one end of the inductor L, the source electrode is grounded, the grid electrode is connected with the first output end of the driving circuit driver, the grid of the rectifying tube M 1 is connected with the second output end of the driving circuit driver, the inverting input end of the current zero comparator is connected with the source electrode of the rectifying tube M 1, the common end of the power tube M 2 and the inductance L, the non-inverting input end is connected with the drain electrode of the rectifying tube M 1, The common end of the output capacitor internal resistance R ESR is connected, the output end is simultaneously connected with the first input end of the driving circuit driver and the bias current setting end of the comparator, one end of the divider resistor R 1 is connected with the drain electrode of the rectifying tube M 1 and the common end of the output capacitor internal resistance R ESR, The other end is grounded through a voltage dividing resistor R 2, the inverting input end of the comparator is connected with the common end of the voltage dividing resistor R 1、R2, the normal phase input end is connected with a reference voltage V REF, the output end of the comparator is connected with the first input end of the PFM module, the second input end of the PFM module is connected with the output end of the on-time control circuit, the output end of the PFM module is connected with the second input end of the driving circuit driver;
The output terminal voltage V OUT is the voltage of the common terminal of the drain electrode of the rectifying tube M 1 and the internal resistance R ESR of the output capacitor; the divided voltage of the output voltage V OUT acts on the comparator as a sampling voltage FB, and the sampling voltage FB is compared with the reference voltage V REF of the comparator; The output signal V EA obtained by the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM module; the output signal of the PFM and the output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit to control the on or off of the power tube M 2 or the rectifying tube M 1; When the output voltage V OUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit are all high levels, The power tube M 2 is turned on, the rectifying tube M 1 is turned off, the inductor L stores energy, and the on-time control circuit starts timing; After reaching the preset time, the on-time control circuit resets the PFM module to enable the output signals of the PFM module to be low level, so that the output signals VN and VP of the driving circuit are low level, the power tube M 2 is cut off, the rectifying tube M 1 is conducted, the inductor L releases energy to the output end of the circuit, and meanwhile, the current zero-crossing comparator detects whether the inductor current crosses zero to judge whether the load is heavy load or light load; If the inductance current crosses zero, the output signal V ZERO of the current flowing through the zero comparator is in a high level, and the load is in a light load state, at the moment, the bias current of the comparator is reduced by the output signal V ZERO of the current flowing through the zero comparator, so that the static loss of the circuit is reduced; if the inductance current does not cross zero, the output signal V ZERO of the current flowing through the zero comparator is low level, the load is in a heavy load state, at the moment, the bias current of the comparator is increased by the output signal V ZERO of the current flowing through the zero comparator, the speed of the comparator is increased, and the working frequency of the circuit is increased.
As preferable: the internal circuit of the comparator includes: NOR gate D 1、D2, inverter E 1, PMOS transistor P 1、P2、P3、P4、P5、P6, NMOS transistor N 1、N2、N3、N4、N5, The bias voltage V BP, the output signal VZERO of the current-through zero comparator is connected with the first input end of the NOR gate D 1, the output end of the NOR gate D 2 is connected with the second input end of the NOR gate D 1, The output end of the NOR gate D 1 is connected with the first input end of the NOR gate D 2, the output signal VEA of the comparator is connected with the second input end of the NOR gate D 2, the output end of the NOR gate D 1 is connected with the input end of the inverter E 1, The output end of the inverter E 1 is connected with the grid electrode of the PMOS tube P 2, the source electrode of the PMOS tube P 2 is connected with the drain electrode of the PMOS tube P 1, The drain electrode of the PMOS tube P 2 is connected with the drain electrode of the PMOS tube P 3 and the drain electrode of the NMOS tube N 1 at the same time, the source electrode of the PMOS tube P 1 is connected with the power supply voltage, The grid electrode of the PMOS tube P 1 is connected with the bias voltage V BP, the source electrode of the PMOS tube P 3 is connected with the power supply voltage, the grid electrode of the PMOS tube P 3 is connected with the bias voltage V BP, The drain electrode of the NMOS tube N 1 is connected with a gate wire, the source electrode of the NMOS tube N 1 is grounded, the source electrode of the PMOS tube P 4 is connected with a power supply voltage, the gate electrode of the PMOS tube P 4 is connected with the gate electrode of the PMOS tube P 5, The drain of the PMOS tube P 4 is connected with the drain of the NMOS tube N 2, the grid of the PMOS tube P 4 is connected with a drain wire, the grid of the NMOS tube N 2 is connected with the sampling voltage FB, The source electrode of the NMOS tube N 2 is connected with the drain electrode of the NMOS tube N 3 and the source electrode of the NMOS tube N 4, the grid electrode of the NMOS tube N 3 is connected with the grid electrode of the NMOS tube N 1 and the grid electrode of the NMOS tube N5, The source electrode of the NMOS tube N 3 is grounded, the source electrode of the PMOS tube P 5 is connected with the power supply voltage, the drain electrode of the PMOS tube P 5 is connected with the drain electrode of the NMOS tube N 4, the grid electrode of the NMOS tube N 4 is connected with the reference voltage VREF of the comparator, the source electrode of the PMOS tube P 6 is connected with the power supply voltage, the drain electrode of the PMOS tube P 6 and the drain electrode of the NMOS tube N 5 are connected with the output end of the comparator, The source electrode of the NMOS tube N 5 is grounded;
When the output end voltage V OUT is lower than the preset voltage, the output signal V EA of the comparator is high level, and V EA outputs low level to enable the PMOS tube P 2 to be conducted after passing through the NOR gate D 2、D1 and the inverter E 1, so that the bias current of the comparator is increased, and the response speed of the comparator is improved; at this time, if the load is in heavy load, the output signal V ZERO of the current zero-crossing comparator is low level, the PMOS transistor P 2 is always turned on, and the comparator keeps a faster response speed; at this time, if the load is in light load, the output signal V ZERO of the current zero comparator is in high level, and the output signal V ZERO outputs high level to turn off the PMOS transistor P 2 after passing through the nor gate D 1、D2 and the inverter E 1, so as to reduce the bias current of the comparator, reduce the static loss of the circuit, and improve the efficiency.
As preferable: the circuit comprises: voltage input end V IN, inductance L, current zero-passing comparator, rectifying tube M 1, power tube M 2, driving circuit driver, PFM module, comparator, voltage dividing resistor R 1、R2, The output capacitor C OUT and the on-time control circuit also comprise an output capacitor internal resistance R ESR, wherein the rectifying tube M 1 is a PMOS tube and the power tube M 2 is an NMOS tube; The voltage input end V IN is grounded after passing through the inductance L, the source electrode and the drain electrode of the rectifying tube M 1, the internal resistance R ESR of the output capacitor and the output capacitor C OUT in sequence, The voltage input end V IN is grounded after passing through the inductor L, the drain electrode and the source electrode of the power tube M 2 in sequence, the grid electrode of the power tube M 2 is simultaneously connected with the first output end of the driving circuit driver and the bias current setting end of the comparator, The grid electrode of the rectifying tube M 1 is connected with the second output end of the driving circuit driver, the non-inverting input end of the current zero-crossing comparator is connected with the source electrode of the rectifying tube M 1, the drain electrode of the power tube M 2 and the common end of the inductor L, The inverting input end is connected with the drain electrode of the rectifying tube M 1 and the common end of the output capacitor internal resistance R ESR, the output end of the current zero-crossing comparator is connected with the first input end of the driving circuit driver, one end of the voltage dividing resistor R 1 is connected with the drain electrode of the rectifying tube M 1 and the common end of the output capacitor internal resistance R ESR, the other end of the divider resistor R 1 is grounded through the divider resistor R 2, the inverting input end of the comparator is connected with the common end of the divider resistor R 1、R2, the non-inverting input end is connected with the reference voltage V REF, The output end of the comparator is connected with the first input end of the PFM module, the second input end of the PFM module is connected with the output end of the conduction time control circuit, and the output end of the PFM module is connected with the second input end of the driving circuit driver;
The output terminal voltage V OUT is the voltage of the common terminal of the drain electrode of the rectifying tube M 1 and the internal resistance R ESR of the output capacitor;
The divided voltage of the output voltage V OUT acts on the comparator as a sampling voltage FB, and the sampling voltage FB is compared with the reference voltage V REF of the comparator; the output signal V EA obtained by the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM module; The output signal of the PFM and the output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the on or off of the power tube M 2 or the rectifying tube M 1; When the output voltage V OUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit are all high levels, The power tube M 2 is turned on, the rectifying tube M 1 is turned off, the inductor L stores energy, and the on-time control circuit starts timing; After reaching the preset time, the on-time control circuit resets the PFM module to make the output signal of the PFM module be low level, so that the output signal V N、VP of the driving circuit is low level, the power tube M 2 is turned off, the rectifying tube M 1 is turned on, The inductor L releases energy to the output end of the circuit, meanwhile, the load is judged to be light or heavy according to the first output end of the driver of the driving circuit through the duty ratio of the first output signal V N, when the duty ratio of the first output signal V N is smaller than a set value, the load is in a light load state, at the moment, the first output signal V N reduces the bias current of the comparator, The static loss of the circuit is reduced, and the high efficiency under light load is maintained; When the duty ratio of the first output signal V N is greater than a set value, the load is in a heavy load state, and at this time, the first output signal V N increases the bias current of the comparator, so that the speed of the comparator is increased, and the working frequency of the circuit is increased.
As preferable: the internal circuit of the comparator includes: PMOS tube P 1、P2、P3、P4, NMOS tube N 1、N2、N3、N4、N5、N6, resistor R 0, capacitor C 1, The bias voltage V BN, the source electrodes of the PMOS pipes P 1、P2、P3、P4 are respectively connected with the power supply voltage, the drain electrode of the PMOS pipe P 1 is connected with the drain electrode of the NMOS pipe N 3, The grid electrode of the PMOS tube P 1 is connected with the grid electrode of the PMOS tube P 2, the source electrode of the NMOS tube N 3 is grounded, the grid electrode of the NMOS tube N 3 is connected with the grid electrode of the NMOS tube N 6, The drain electrode of the NMOS tube N 3 is connected with a gate wire, the drain electrode of the PMOS tube P 2 is connected with the drain electrode of the NMOS tube N 4, the gate electrode of the PMOS tube P 2 is connected with a drain wire, The grid electrode of the NMOS tube N 4 is connected with the sampling voltage FB, the source electrode of the NMOS tube N 4, the source electrode of the NMOS tube N 5, the drain electrode of the NMOS tube N 1, The drain of NMOS tube N 2 is connected, the source of NMOS tube N 1 is grounded, The first output signal V N of the driver is connected to the gate of the NMOS transistor N 1 and one end of the capacitor C 1 through a resistor R 0, The other end of the capacitor C 1 is grounded, the grid electrode of the NMOS tube N 2 is connected with the bias voltage V BN, the source electrode of the NMOS tube N 2 is grounded, The drain electrode of the PMOS tube P 3 is connected with the drain electrode of the NMOS tube N 5, the grid electrode of the PMOS tube P 3 is connected with the grid electrode of the PMOS tube P 4, The grid electrode of the PMOS tube P 3 is connected with a drain electrode lead, the grid electrode of the NMOS tube N 5 is connected with the reference voltage V REF of the comparator, the drain electrode of the PMOS tube P 4, The drain electrode of the NMOS tube N 6 is connected with the output end of the comparator, and the source electrode of the NMOS tube N 6 is grounded;
When the load is light load, the duty ratio of an output signal V N of the driving circuit is smaller than a set value, V N is changed into a direct current analog level with small amplitude after being filtered by a resistor R 0 and a capacitor C 1, and an NMOS tube N 1 is turned off, so that the bias current of a comparator is reduced, and the high efficiency of the light load state is maintained; when the load is heavy, the duty ratio of the output signal V N of the driving circuit is larger than a set value, V N is changed into a direct current analog level with larger amplitude after being filtered by a resistor R 0 and a capacitor C 1, so that the NMOS tube N 1 is conducted, the bias current of the comparator is increased along with the increase of the duty ratio of V N, and the response speed of the comparator is improved.
The other technical solution of the invention is a control method of the response speed conversion circuit of the boosting system based on PFM control, which is characterized in that the circuit comprises a voltage input end V IN, an inductance L, a current zero-passing comparator, a rectifying tube M 1, a power tube M 2, a driving circuit, a PFM module, a comparator, a voltage dividing resistor R 1、R2, an output capacitor C OUT, an output capacitor internal resistance R ESR and a conduction time control circuit, and the steps are as follows:
⑴ The output end voltage V OUT is divided by a divider resistor R 1、R2 to obtain a sampling voltage FB;
⑵ The sampling voltage FB acts on a comparator and is compared with a reference voltage V REF of the comparator, and the comparator obtains an output signal V EA of the comparator;
⑶ The output signal V EA of the comparator and the output signal of the on-time control circuit jointly act on the PFM module to obtain an output signal of the PFM module;
⑷ The output signal of the PFM module and the output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the power tube M 2 and the rectifying tube M 1 to be conducted or cut off;
⑸ When the output end voltage V OUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit driver are all high levels, the power tube M 2 is conducted, the rectifying tube M 1 is cut off, the inductor L stores energy, and meanwhile, the conduction time control circuit starts timing;
⑹ When the timing reaches the preset time, the on-time control circuit resets the PFM module to enable the output signal of the PFM module to be low level, and then the output signal V N、VP of the driving circuit is also low level, the power tube M 2 is turned off, and the rectifying tube M 1 is turned on;
⑺ The inductor L releases the energy stored in the step ⑸ to the output end of the circuit, and the current zero-crossing comparator detects whether the inductor current crosses zero to judge whether the load is light load or heavy load;
⑻ If the inductance current crosses zero, the output signal V ZERO of the current flowing through the zero comparator is in a high level, and the load is in a light load state, at the moment, the bias current of the comparator is reduced by the output signal V ZERO of the current flowing through the zero comparator, so that the static loss of the circuit is reduced;
If the inductance current does not cross zero, the output signal V ZERO of the current flowing through the zero comparator is low level, the load is in a heavy load state, at the moment, the bias current of the comparator is increased by the output signal V ZERO of the current flowing through the zero comparator, the speed of the comparator is increased, and the working frequency of the circuit is increased.
The control method of the boost system response speed conversion circuit based on PFM control is characterized in that the circuit comprises a voltage input end V IN, an inductance L, a current zero-crossing comparator, a rectifying tube M 1, a power tube M 2, a driving circuit, a PFM module, a comparator, a voltage dividing resistor R 1、R2, an output capacitor C OUT, an output capacitor internal resistance R ESR and a conduction time control circuit, and comprises the following steps:
⑴ The output end voltage V OUT is divided by a divider resistor R 1、R2 to obtain a sampling voltage FB;
⑵ The sampling voltage FB acts on a comparator and is compared with a reference voltage V REF of the comparator, and the comparator obtains an output signal V EA of the comparator;
⑶ The output signal V EA of the comparator and the output signal of the on-time control circuit jointly act on the PFM module to obtain an output signal of the PFM module;
⑷ The output signal of the PFM module and the output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the power tube M 2 and the rectifying tube M 1 to be conducted or cut off;
⑸ When the output end voltage V OUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit driver are all high levels, the power tube M 2 is conducted, the rectifying tube M 1 is cut off, the inductor L stores energy, and meanwhile, the conduction time control circuit starts timing;
⑹ When the timing reaches the preset time, the on-time control circuit resets the PFM module to enable the output signal of the PFM module to be low level, and then the output signal V N、VP of the driving circuit is also low level, the power tube M 2 is turned off, and the rectifying tube M 1 is turned on;
⑺ The inductor L releases the energy stored in the step ⑸ to the output end of the circuit, and the first output end of the driving circuit driver judges whether the load is light or heavy according to the duty ratio of the first output signal V N;
⑻ When the duty ratio of the first output signal V N is smaller than a set value, the load is in a light load state, and at the moment, the first output signal V N reduces the bias current of the comparator, so that the static loss of the circuit is reduced, and the high efficiency under light load is maintained;
When the duty ratio of the first output signal V N is greater than a set value, the load is in a heavy load state, and at this time, the first output signal V N increases the bias current of the comparator, so that the speed of the comparator is increased, and the working frequency of the circuit is increased.
Compared with the prior art, the invention has the beneficial effects that:
⑴ Two circuits are provided for realizing the conversion of the response speed of the boosting system:
The first circuit distinguishes whether the load is light load or heavy load through the output signal V ZERO of the internal current through the zero comparator, so that the bias current of the comparator is changed, the working frequency of the whole system can reach 1MHz or even higher when the load is heavy load, low static current and high efficiency can be ensured under the light load condition, the improvement of the working frequency of the system can enable the use of small inductance L and small output capacitance C OUT, the ripple wave of small output voltage V OUT can still be kept, the circuit is simple, the cost is low, the integration precision is high, and the system has market competitiveness.
The second circuit utilizes the driving signal V N to distinguish whether the load is light load or heavy load, when the load is light load, the duty ratio of V N is lower, when the load is heavy load, the duty ratio of V N is larger, the bias current of the comparator is controlled by utilizing the difference of the duty ratios to change the response speed of the comparator, and the response speed of the boost converter based on PFM control can be effectively improved by adopting the method, the high efficiency under the condition of no load or light load can be maintained, the circuit is simple, the effect is obvious, the cost of the whole system is greatly reduced, and the market competitiveness is improved.
⑵ The detection method of the invention is to increase the speed of the comparator when the output voltage V OUT is detected to be lower than the set value, thus increasing the response speed of the system when the load suddenly changes into heavy load, avoiding the output voltage from being greatly reduced and increasing the response speed of the system under the condition of sudden load. At this time, if the load is always under heavy load, the output V ZREO of the current-zero comparator remains unchanged, and at this time, the bias current of the comparator remains larger until the load becomes light load.
⑶ The control method can effectively improve the response speed of the boost converter based on PFM control and can maintain high efficiency under no-load or light-load conditions. The circuit is simple and has obvious effect, the cost of the whole system is greatly reduced, and the market competitiveness is improved.
⑷ The conversion circuit provided by the invention distinguishes whether the load is light load or heavy load through the duty ratio of the output signal V ZERO or the driving signal V N of the internal current through the zero comparator, so that the bias current of the comparator is changed, the working frequency of the whole system can be up to 1MHz or higher when the load is heavy load, and the low static current and high efficiency can be ensured under the light load condition. The increase in the operating frequency of the system allows the use of a small inductance L and a small output capacitance C OUT, while still maintaining a small ripple of the output voltage V OUT. The circuit is simple, low in cost and high in integration precision, so that the system has market competitiveness.
Drawings
FIG. 1 is a block diagram of a prior art PFM control-based boost converter system;
FIG. 2 is a circuit block diagram of response speed conversion of a boost system based on PFM control according to a first technical solution of the present invention;
FIG. 3 is a circuit block diagram of a specific implementation of the comparator according to the first technical solution of the present invention;
FIG. 4 is a circuit block diagram of response speed conversion of a boost system based on PFM control according to a second embodiment of the present invention;
Fig. 5 is a circuit block diagram of a specific implementation of the comparator according to the second technical solution of the present invention.
Detailed Description
The invention will be further described in detail below with reference to the accompanying drawings:
Referring to fig. 2, a first technical solution of the present invention is to provide a boost converter response speed conversion circuit based on PFM control, which distinguishes whether a load is a light load or a heavy load through an output signal V ZERO of an internal current flowing through a zero comparator, so as to change a bias current of the comparator.
Referring to fig. 2, the circuit includes: voltage input end V IN, inductance L, current zero-passing comparator, rectifying tube M 1, power tube M 2, driving circuit driver, PFM module, comparator, voltage dividing resistor R 1、R2, The output capacitor C OUT and the on-time control circuit also comprise an output capacitor internal resistance R ESR, wherein the rectifying tube M 1 is a PMOS tube and the power tube M 2 is an NMOS tube; The voltage input end V IN is grounded after passing through the inductance L, the rectifying tube M 1, the internal resistance R ESR of the output capacitor and the output capacitor C OUT in sequence, The voltage input end V IN is grounded after passing through the inductor L and the power tube M 2 in sequence, the drain electrode of the power tube M 2 is connected with one end of the inductor L, the source electrode is grounded, the grid electrode is connected with the first output end of the driving circuit driver, The source electrode of the rectifying tube M 1 is connected with one end of the inductance L, the drain electrode is connected with one end of the output capacitor internal resistance R ESR, the grid electrode is connected with the second output end of the driving circuit driver, the inverting input end of the current-through zero comparator is connected with the source electrode of the rectifying tube M 1, The normal phase input end is connected with the drain electrode of the rectifying tube M 1, the output end is simultaneously connected with the first input end of the driving circuit driver and the bias current setting end of the comparator, one end of the divider resistor R 1 is connected with the drain electrode of the rectifying tube M 1, The other end is grounded through a voltage dividing resistor R 2, the inverting input end of the comparator is connected with the common end of the voltage dividing resistor R 1、R2, the normal phase input end of the comparator is connected with a reference voltage V REF, the output end of the comparator is connected with the first input end of the PFM module, the second input end of the PFM module is connected with the output end of the on-time control circuit, the output end of the PFM module is connected with the second input end of the driving circuit driver;
The output terminal voltage V OUT is the voltage of the common terminal of the drain electrode of the rectifying tube M1 and the internal resistance R ESR of the output capacitor;
The divided voltage of the output voltage V OUT acts on the comparator as a sampling voltage FB, and the sampling voltage FB is compared with the reference voltage V REF of the comparator; the output signal V EA obtained by the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM module; The output signal of the PFM and the output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit to control the on or off of the power tube M 2 or the rectifying tube M 1; When the output voltage V OUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit are all high levels, The power tube M 2 is turned on, the rectifying tube M 1 is turned off, the inductor L stores energy, and the on-time control circuit starts timing; After reaching the preset time, the on-time control circuit resets the PFM module to make the output signal of the PFM module be low level, so that the output signal V N、VP of the driving circuit is low level, the power tube M 2 is turned off, the rectifying tube M 1 is turned on, The inductor L releases energy to the output end of the circuit, and meanwhile, the load is judged to be heavy load or light load according to whether the current passes through the zero comparator or not through zero crossing of the inductor current; If the inductance current crosses zero, the output signal V ZERO of the current flowing through the zero comparator is in a high level, and the load is in a light load state, at the moment, the bias current of the comparator is reduced by the output signal V ZERO of the current flowing through the zero comparator, so that the static loss of the circuit is reduced; if the inductance current does not cross zero, the output signal V ZERO of the current flowing through the zero comparator is low level, the load is in a heavy load state, at the moment, the bias current of the comparator is increased by the output signal V ZERO of the current flowing through the zero comparator, the speed of the comparator is increased, and the working frequency of the circuit is increased.
Specifically, if the zero crossing signal V ZERO is at a high level, the load is light or standby, and if the zero crossing signal V ZERO is at a low level, the load is heavy. The magnitude of the bias current of the comparator can be determined according to the high and low levels of the zero crossing signal V ZERO. If the system is lightly loaded, the bias current of the comparator is kept to be minimum, and the static current is kept low so as to improve the efficiency of the system under the condition of lightly loaded. If the load is heavy, the bias current of the comparator is increased, and the response speed of the comparator is improved, so that the working frequency of the whole system can be up to 1MHz or even higher. The method can effectively improve the working frequency of the system and keep low static current in light load, and can keep low ripple of output voltage VOUT by using small inductance and small output capacitance, so that the circuit is simple and the cost is low.
The first technical proposal of the invention is as follows: the output signal V ZERO of the internal current through zero comparator is used for distinguishing whether the load is light load or heavy load, so that the bias current of the comparator is changed, the working frequency of the whole system can be up to 1MHz or higher when the load is heavy load, and the low quiescent current and high efficiency can be ensured under the light load condition. The increase in the operating frequency of the system allows the use of a small inductance L and a small output capacitance C OUT, while still maintaining a small ripple of the output voltage V OUT. The circuit is simple, low in cost and high in integration precision, so that the system has market competitiveness.
As can be seen from fig. 2, when the voltage V OUT is lower than the preset target voltage, that is, when the voltage FB of V OUT divided by the feedback resistors R 1 and R 2 is lower than the reference voltage V REF, the comparator outputs a high level, the PFM module outputs a high level, the output V P、VN of the driving module driver is all high level, that is, the power tube NMOS tube M 2 is turned on, the synchronous rectifying tube PMOS tube M 1 is turned off, and the inductance current increases linearly and the inductance stores energy.
When the output V EA of the comparator is changed to a high level, the on-time control circuit starts timing, when the timing reaches a preset time, the on-time control circuit outputs a high level, resets the PFM module to enable the output of the PFM module to be changed to a low level, at the moment, V P、VN also becomes a low level, the power tube NMOS tube M 2 is cut off, the synchronous rectifying tube PMOS tube M 1 is conducted, at the moment, the inductance current is linearly reduced, and the inductance releases energy for output.
From the above analysis, the speed of the comparator is the bottleneck of the whole system working frequency limitation, and the invention judges the light and heavy load by utilizing the output signal of the current zero comparator. When the synchronous rectifier PMOS tube M 1 is conducted, if the current can cross zero, the current through zero comparator can output V ZERO to be high level at the zero crossing moment of the inductance current. If the output V ZERO of the current through zero comparator remains low at all times, this indicates that the inductor current has not crossed zero, which indicates that the load is in a heavy load condition. Therefore, the output V ZERO of the current zero-crossing comparator can be used for judging the weight of the load, namely the bias current of the comparator can be changed according to the output V ZERO of the current zero-crossing comparator, so that the response speed of the comparator is changed.
According to the application of the technical solution of fig. 2, referring to fig. 3, a specific implementation circuit of a comparator is provided, and an internal circuit of the comparator includes: NOR gate D 1、D2, inverter E 1, PMOS transistor P 1、P2、P3、P4、P5、P6, An NMOS tube N 1、N2、N3、N4、N5, a bias voltage V BP, an output signal V ZERO of the current zero comparator connected with a first input end of a NOR gate D 1, the output end of the NOR gate D 2 is connected with the second input end of the NOR gate D 1, the output end of the NOR gate D 1 is connected with the first input end of the NOR gate D 2, the output signal V EA of the comparator is connected with the second input end of the NOR gate D 2, the output end of the NOR gate D 1 is connected with the input end of the inverter E 1, The output end of the inverter E 1 is connected with the grid electrode of the PMOS tube P 2, the source electrode of the PMOS tube P 2 is connected with the drain electrode of the PMOS tube P 1, The drain electrode of the PMOS tube P 2 is connected with the drain electrode of the PMOS tube P 3 and the drain electrode of the NMOS tube N 1 at the same time, the source electrode of the PMOS tube P 1 is connected with the power supply voltage, The grid electrode of the PMOS tube P 1 is connected with the bias voltage V BP, the source electrode of the PMOS tube P 3 is connected with the power supply voltage, the grid electrode of the PMOS tube P 3 is connected with the bias voltage V BP, The drain electrode of the NMOS tube N 1 is connected with a gate wire, the source electrode of the NMOS tube N 1 is grounded, the source electrode of the PMOS tube P 4 is connected with a power supply voltage, the grid electrode of the PMOS tube P 4 is connected with the grid electrode of the PMOS tube P 5, The drain electrode of the PMOS tube P 4 is connected with the drain electrode of the NMOS tube N 2, the grid electrode of the PMOS tube P 4 is connected with a drain electrode lead, and the grid electrode of the NMOS tube N 2 is connected with the sampling voltage FB, The source of the NMOS tube N 2 is connected with the drain of the NMOS tube N 3, the grid of the NMOS tube N 3 is connected with the grid of the NMOS tube N 1, The source electrode of the NMOS tube N 3 is grounded, the source electrode of the PMOS tube P 5 is connected with the power supply voltage, the drain electrode of the PMOS tube P 5 is connected with the drain electrode of the NMOS tube N 4, The grid electrode of the NMOS tube N 4 is connected with the reference voltage V REF of the comparator, the source electrode of the NMOS tube N 4 is connected with the drain electrode of the NMOS tube N 3, the source electrode of the PMOS tube P 6 is connected with the power supply voltage, the grid electrode of the PMOS tube P 6 is connected with the drain electrode of the PMOS tube P 5, the drain electrode of the PMOS tube P 6 is connected with the output end of the comparator, the drain electrode of the NMOS tube N 5 is connected with the output end of the comparator, the grid electrode of the NMOS tube N 5 is connected with the grid electrode of the NMOS tube N 1, and the source electrode of the NMOS tube N 5 is grounded;
When the output end voltage V OUT is lower than the preset voltage, the output signal V EA of the comparator is high level, and V EA outputs low level to enable the PMOS tube P 2 to be conducted after passing through the NOR gate D 1、D2 and the inverter E 1, so that the bias current of the comparator is increased, and the response speed of the comparator is improved; at this time, if the load is in heavy load, the output signal V ZERO of the current zero-crossing comparator is low level, the PMOS transistor P 2 is always turned on, and the comparator keeps a faster response speed; at this time, if the load is in light load, the output signal V ZERO of the current zero comparator is high level, and V ZERO outputs high level to turn off the PMOS transistor P 2 after passing through the nor gate D 1、D2 and the inverter E 1, so as to reduce the bias current of the comparator, reduce the static loss of the circuit, and improve the efficiency.
Specifically, when the voltage V OUT is lower than the preset target voltage, that is, when the voltage FB of the voltage value V OUT divided by the feedback resistors R 1 and R 2 is lower than the reference voltage V REF, the comparator output V EA is at a high level, and after passing through the nor gate and the inverter, the comparator output V EA is at a low level, and at the moment, the PMOS transistor P 2 is turned on, and the bias current of the comparator is increased, so that the speed of the comparator is increased. The detection method is to increase the speed of the comparator when the output voltage V OUT is detected to be lower than a set value, so that the response speed of the system can be increased when the load suddenly changes into heavy load, thereby avoiding the occurrence of great reduction of the output voltage and increasing the response speed of the system under the condition of sudden load. At this time, if the load is always under the heavy load condition, the output V ZREO of the current zero comparator is always at a low level, and then the PMOS transistor P 2 is always on, so that the response speed of the comparator is faster.
When the load suddenly becomes smaller or is converted to an idle load condition, the current flowing through the zero comparator detects zero crossing of the inductance current, so that the output V ZERO is a high-level signal, the high-level signal passes through the NOR gate and the inverter to generate a high-level signal, the PMOS tube P 2 is turned off, the bias current of the comparator is reduced, the static loss of the whole system is reduced, and the efficiency of the system under the light load or idle load condition is improved.
Under no-load or light-load conditions, the output voltage V OUT will decrease slowly, and when the output voltage is lower than the set voltage value, the output voltage V EA of the comparator will also output a high level to increase the bias of the comparator, and then if the inductor current is detected to be zero-crossing in the freewheeling condition, the current zero-crossing signal V ZERO will immediately reduce the bias current of the comparator to the minimum to maintain high efficiency.
Referring to fig. 4, a first application of the technical solution of the present invention is to provide a boost converter response speed conversion circuit based on PFM control, which uses an output signal V N of a driving circuit to distinguish whether a load is a light load or a heavy load, when the load is a light load, the duty ratio of V N is relatively low, and when the load is a heavy load, the duty ratio of V N is relatively high. The bias current of the comparator is controlled by the difference of the duty ratio to change the response speed.
Referring to fig. 4, the implementation circuit includes: voltage input end V IN, inductance L, current zero-passing comparator, rectifying tube M 1, power tube M 2, driving circuit driver, PFM module, comparator, voltage dividing resistor R 1、R2, The output capacitor C OUT and the on-time control circuit also comprise an output capacitor internal resistance R ESR, wherein the rectifying tube M 1 is a PMOS tube and the power tube M 2 is an NMOS tube; The voltage input end V IN is grounded after passing through the inductance L, the rectifying tube M 1, the internal resistance R ESR of the output capacitor and the output capacitor C OUT in sequence, The voltage input end V IN is grounded after passing through the inductor L and the power tube M 2 in sequence, the drain electrode of the power tube M 2 is connected with one end of the inductor L, the source electrode is grounded, the grid electrode is simultaneously connected with the first output end of the driving circuit driver and the bias current setting end of the comparator, the source electrode of the rectifying tube M 1 is connected with one end of the inductance L, the drain electrode is connected with one end of the output capacitor internal resistance R ESR, the grid electrode is connected with the second output end of the driving circuit driver, the non-inverting input end of the current zero-crossing comparator is connected with the source electrode of the rectifying tube M 1, The inverting input end is connected with the drain electrode of the rectifying tube M 1, the output end is connected with the first input end of the driving circuit driver, one end of the divider resistor R 1 is connected with the drain electrode of the rectifying tube M 1, the other end is grounded through the divider resistor R 2, the inverting input end of the comparator is connected with the public end of the divider resistor R 1、R2, the non-inverting input end of the comparator is connected with the reference voltage V REF, the output end of the comparator is connected with the first input end of the PFM module, the second input end of the PFM module is connected with the output end of the on-time control circuit, and the output end of the PFM module is connected with the second input end of the driving circuit driver;
The output terminal voltage V OUT is the voltage of the common terminal of the drain electrode of the rectifying tube M 1 and the internal resistance R ESR of the output capacitor;
The divided voltage of the output voltage V OUT acts on the comparator as a sampling voltage FB, and the sampling voltage FB is compared with the reference voltage V REF of the comparator; the output signal V EA obtained by the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM module; The output signal of the PFM and the output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the conduction of the power tube M 2 or the rectifying tube M 1; When the output voltage V OUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit are all high levels, The power tube M 2 is turned on, the rectifying tube M 1 is turned off, the inductor L stores energy, and the on-time control circuit starts timing; After reaching the preset time, the on-time control circuit resets the PFM module to make the output signal of the PFM module be low level, so that the output signal V N、VP of the driving circuit is low level, the power tube M 2 is turned off, the rectifying tube M 1 is turned on, The inductor L releases energy to the output end of the circuit, meanwhile, the load is judged to be light or heavy according to the first output end of the driver of the driving circuit through the duty ratio of the first output signal V N, when the duty ratio of the first output signal V N is smaller than a certain value, the load is in a light load state, at the moment, the first output signal V N reduces the bias current of the comparator, The static loss of the circuit is reduced, and the high efficiency under light load is maintained; When the duty ratio of the first output signal V N is greater than a certain value, the load is in a heavy load state, and at this time, the first output signal V N increases the bias current of the comparator, so that the speed of the comparator is increased, and the working frequency of the circuit is increased.
According to a second application of the present invention, as shown in fig. 5, a specific implementation circuit of a comparator is provided, and an internal circuit of the comparator includes: PMOS tube P 1、P2、P3、P4, NMOS tube N 1、N2、N3、N4、N5、N6, resistor R 0, capacitor C 1, Bias voltage V BN, the source electrodes of the PMOS pipes P 1、P2、P3、P4 are respectively connected with power supply voltage, the drain electrode of the PMOS pipe P 1 is connected with the drain electrode of the NMOS pipe N 3, The grid electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P2, the source electrode of the NMOS tube N3 is grounded, the grid electrode of the NMOS tube N 3 is connected with the grid electrode of the NMOS tube N 6, the drain electrode of the NMOS tube N 3 is connected with a grid electrode lead, The drain electrode of the PMOS tube P 2 is connected with the drain electrode of the NMOS tube N 4, the grid electrode of the PMOS tube P 2 is connected with a drain electrode lead, and the grid electrode of the NMOS tube N 4 is connected with the sampling voltage FB, The source electrode of the NMOS tube N 4 is connected with the drain electrode of the NMOS tube N 1, the source electrode of the NMOS tube N 1 is grounded, the first output signal V N of the driving circuit driver is connected with the grid electrode of the NMOS tube N 1 through a resistor R 0, One end of the capacitor C 1 is connected with the grid electrode of the NMOS tube N 1, the other end is grounded, the grid electrode of the NMOS tube N 2 is connected with the bias voltage V BN, The drain of the NMOS tube N 2 is connected with the drain of the NMOS tube N 1, the source of the NMOS tube N 2 is grounded, the drain of the PMOS tube P 3 is connected with the drain of the NMOS tube N 5, The grid electrode of the PMOS tube P 3 is connected with the grid electrode of the PMOS tube P 4, the grid electrode of the PMOS tube P 3 is connected with the drain electrode wire, and the grid electrode of the NMOS tube N 5 is connected with the reference voltage V REF of the comparator, The source electrode of the NMOS tube N 5 is connected with the drain electrode of the NMOS tube N 1, the drain electrode of the PMOS tube P 4 is connected with the output end of the comparator, the drain electrode of the NMOS tube N 6 is connected with the output end of the comparator, the source electrode of the NMOS tube N 6 is grounded;
When the load is light load, the duty ratio of the output signal V N of the driving circuit is smaller than a certain value, V N is changed into a direct current analog level with small amplitude after being filtered by a resistor R 0 and a capacitor C 1, and the NMOS tube N 1 is turned off, so that the bias current of the comparator is reduced, and the high efficiency of the light load state is maintained; when the load is heavy, the duty ratio of the output signal V N of the driving circuit is larger than a certain value, the output signal V N is changed into a direct current analog level with larger amplitude after being filtered by the resistor R 0 and the capacitor C 1, and the NMOS tube N 1 is conducted, so that the bias current of the comparator is increased along with the increase of the duty ratio of the V N, and the response speed of the comparator is improved.
Specifically, when the load is light load, the duty ratio of the driving signal V N is very small, the driving signal V N is changed into a direct current analog level with very small amplitude after being filtered by the resistor R 0 and the capacitor C 1, then the NMOS tube N 1 is turned off, and the bias current of the comparator is the smallest at this time, so that the high efficiency under no-load or light load can be maintained;
When the load is heavy, the duty ratio of the driving signal V N is very large, the driving signal V N is changed into a direct current analog level with a relatively large amplitude after being filtered by the resistor R 0 and the capacitor C 1, then the NMOS tube N 1 is turned on, the bias current of the comparator is changed along with the duty ratio of the driving signal V N, and the larger the duty ratio is, the larger the direct current analog level after being filtered is, the larger the current flowing through the NMOS tube N 1 is, and the response speed of the comparator is faster.
The third application of the technical solution of the invention is a control method of a response speed conversion circuit of a boosting system based on PFM control, wherein the circuit comprises a voltage input end V IN, an inductance L, a current zero-crossing comparator, a rectifying tube M 1, a power tube M 2, a driving circuit, a PFM module, a comparator, a voltage dividing resistor R 1、R2, an output capacitor C OUT, an output capacitor internal resistance R ESR and a conduction time control circuit, and the steps are as follows:
S1, dividing the output end voltage V OUT by a dividing resistor R 1、R2 to obtain a sampling voltage FB;
S2, the sampling voltage FB acts on a comparator and is compared with a reference voltage V REF of the comparator, and the comparator obtains an output signal V EA of the comparator;
S3, the output signal V EA of the comparator and the output signal of the on-time control circuit act on the PFM module together to obtain an output signal of the PFM module;
S4, an output signal of the PFM module and an output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the on or off of the power tube M 2 and the rectifying tube M 1;
S5, when the voltage V OUT at the output end is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit driver are all high levels, the power tube M 2 is conducted, the rectifying tube M 1 is cut off, the inductor L stores energy, and meanwhile, the conduction time control circuit starts timing;
s6, when the timing reaches the preset time, the conducting time control circuit resets the PFM module to enable the output signal of the PFM module to be low level, and then the output signal V N、VP of the driving circuit is also low level, the power tube M 2 is cut off, and the rectifying tube M 1 is turned on;
S7, an inductor L releases the energy stored in the step S5 to the output end of the circuit, and the current through the zero comparator judges whether the load is light load or heavy load through zero crossing of the inductor current;
S8, if the inductance current crosses zero, an output signal V ZERO of the current-passing zero comparator is in a high level, and the load is in a light load state, at the moment, the bias current of the comparator is reduced by an output signal V ZERO of the current-passing zero comparator, so that the static loss of the circuit is reduced;
If the inductance current does not cross zero, the output signal V ZERO of the current flowing through the zero comparator is low level, the load is in a heavy load state, at the moment, the bias current of the comparator is increased by the output signal V ZERO of the current flowing through the zero comparator, the speed of the comparator is increased, and the working frequency of the circuit is increased.
The fourth technical solution of the invention is a control method of a boost system response speed conversion circuit based on PFM control, the circuit comprises a voltage input end V IN, an inductance L, a current zero-crossing comparator, a rectifying tube M 1, a power tube M 2, a driving circuit, a PFM module, a comparator, voltage dividing resistors R 1 and R 2, an output capacitor C OUT, an output capacitor internal resistance R ESR and a conduction time control circuit, and the steps are as follows:
S1, dividing the output end voltage V OUT by a dividing resistor R 1、R2 to obtain a sampling voltage FB;
S2, the sampling voltage FB acts on a comparator and is compared with a reference voltage V REF of the comparator, and the comparator obtains an output signal V EA of the comparator;
S3, the output signal V EA of the comparator and the output signal of the on-time control circuit act on the PFM module together to obtain an output signal of the PFM module;
S4, an output signal of the PFM module and an output signal V ZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the power tube M 2 and the rectifying tube M 1 to be conducted or cut off;
S5, when the voltage V OUT at the output end is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage V REF, the output signal V EA of the comparator, the output signal of the PFM module and the output signal V P、VN of the driving circuit driver are all high levels, the power tube M 2 is conducted, the rectifying tube M 1 is cut off, the inductor L stores energy, and meanwhile, the conduction time control circuit starts timing;
s6, when the timing reaches the preset time, the conducting time control circuit resets the PFM module to enable the output signal of the PFM module to be low level, and then the output signal V N、VP of the driving circuit is also low level, the power tube M 2 is cut off, and the rectifying tube M 1 is turned on;
S7, an inductor L releases energy stored in the step S5 to an output end of the circuit, and a first output end of a driver of the driving circuit judges whether a load is a light load or a heavy load according to the duty ratio of a first output signal V N;
S8, when the duty ratio of the first output signal VN is smaller than a certain value, the load is in a light load state, and at the moment, the bias current of the comparator is reduced by the first output signal VN, so that the static loss of the circuit is reduced, and the high efficiency under the light load is maintained;
when the duty ratio of the first output signal VN is larger than a certain value, the load is in a heavy load state, and at the moment, the bias current of the comparator is increased by the first output signal VN, so that the speed of the comparator is increased, and the working frequency of the circuit is increased.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (6)

1. A boost system response speed conversion circuit based on PFM control, the circuit comprising: the voltage dividing circuit comprises a voltage input end, an inductor, a current zero-crossing comparator, a rectifying tube, a power tube, a driving circuit, a PFM module, a comparator, a voltage dividing resistor, an output capacitor and a conduction time control circuit, wherein the voltage division of the voltage of the output end of the circuit is used as sampling voltage to act on the comparator and is compared with the reference voltage of the comparator; the output signal of the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM, and the output signal of the PFM and the output signal of the current-through zero comparator jointly act on the driving circuit to control the on or off of the power tube or the rectifying tube; when the voltage of the output end is lower than the preset voltage, the power tube is conducted, the rectifying tube is cut off, the inductance stores energy, and the conduction time control circuit starts timing; after reaching the preset time, the conducting time control circuit resets the PFM module, and then controls the driving circuit to enable the power tube to be cut off, the rectifying tube to be conducted and the inductor to release energy to the output end of the circuit, at the moment, the load is judged to be light load or heavy load according to the output signal of the current zero-crossing comparator or the output driving signal of the driving circuit, and when the load is light load, the current zero-crossing comparator detects that the inductance current zero-crossing or the duty ratio of the output driving signal of the driving circuit is very low, so that the bias current of the comparator is reduced; when the load is heavy, the zero-crossing of the inductance current is not detected by the current through zero comparator or the duty ratio of the output driving signal of the driving circuit is larger, so that the bias current of the comparator is increased;
When the load is judged to be light or heavy according to the output signal of the current zero-crossing comparator, the internal circuit of the comparator comprises: the output signal VZERO of the current through zero comparator is connected with the first input end of the nor gate D1, the output end of the nor gate D2 is connected with the second input end of the nor gate D1, the output end of the nor gate D1 is connected with the first input end of the nor gate D2, the output signal VEA of the comparator is connected with the second input end of the nor gate D2, the output end of the nor gate D1 is connected with the input end of the inverter E1, the output end of the inverter E1 is connected with the grid electrode of the PMOS tube P2, the source electrode of the PMOS tube P2 is connected with the drain electrode of the PMOS tube P1, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the PMOS tube P3 and the drain electrode of the NMOS tube N1 at the same time, the source electrode of the PMOS tube P1 is connected with the power supply voltage, the grid electrode of the PMOS tube P1 is connected with the bias voltage VBP, the source electrode of the PMOS tube P3 is connected with the source electrode of the power supply voltage, the grid electrode of the PMOS tube P3 is connected with bias voltage VBP, the drain electrode of the NMOS tube N1 is connected with a grid electrode lead, the source electrode of the NMOS tube N1 is grounded, the source electrode of the PMOS tube P4 is connected with power supply voltage, the grid electrode of the PMOS tube P4 is connected with the grid electrode of the PMOS tube P5, the drain electrode of the PMOS tube P4 is connected with the drain electrode of the NMOS tube N2, the grid electrode of the NMOS tube N2 is connected with the drain electrode of the NMOS tube N3 and the source electrode of the NMOS tube N4, the grid electrode of the NMOS tube N3 is connected with the grid electrode of the NMOS tube N1 and the grid electrode of the NMOS tube N5, the source electrode of the NMOS tube N3 is grounded, the source electrode of the PMOS tube P5 is connected with the drain electrode of the NMOS tube N4, the grid electrode of the NMOS tube N4 is connected with reference voltage VREF of the comparator, the source electrode of the PMOS tube P6 is connected with the power supply voltage, the drain electrode of the PMOS tube P6 and the drain electrode of the NMOS tube N5 are connected with the output end of the comparator, the source electrode of the NMOS tube N5 is grounded;
When the output end voltage VOUT is lower than the preset voltage, the output signal VEA of the comparator is high level, and the VEA outputs low level after passing through the NOR gates D2 and D1 and the inverter E1 to lead the PMOS tube P2 to be conducted, so that the bias current of the comparator is increased, and the response speed of the comparator is improved; at this time, if the load is in heavy load, the output signal VZERO of the current zero-crossing comparator is low level, the PMOS transistor P2 is always on, and the comparator keeps a faster response speed; at this time, if the load is in light load, the output signal VZERO of the current zero comparator is in high level, and the output signal VZERO outputs high level after passing through the nor gates D1 and D2 and the inverter E1 to turn off the PMOS transistor P2, so as to reduce the bias current of the comparator, reduce the static loss of the circuit, and improve the efficiency.
2. The PFM control-based boost system response speed conversion circuit according to claim 1, wherein when the load is judged to be light load or heavy load according to the output signal of the current zero-crossing comparator, the circuit comprises: the voltage input end VIN, the inductance L, the current zero-crossing comparator, a rectifying tube M1, a power tube M2, a driving circuit driver, a PFM module, a comparator, voltage dividing resistors R1 and R2, an output capacitor COUT, a conduction time control circuit and an output capacitor internal resistance RESR, wherein the rectifying tube M1 is a PMOS tube, and the power tube M2 is an NMOS tube; the voltage input end VIN sequentially passes through the inductor L, the source electrode and the drain electrode of the rectifying tube M1, the output capacitor internal resistance RESR and the output capacitor COUT and then is grounded, the voltage input end VIN sequentially passes through the inductor L and the power tube M2 and then is grounded, the drain electrode of the power tube M2 is connected with one end of the inductor L, the source electrode is grounded, the grid electrode is connected with the first output end of the driving circuit driver, the grid electrode of the rectifying tube M1 is connected with the second output end of the driving circuit driver, the inverting input end of the current flowing through the zero comparator is connected with the source electrode of the rectifying tube M1, the common end of the power tube M2 and the inductor L, the normal phase input end is connected with the drain electrode of the rectifying tube M1 and the common end of the output capacitor internal resistance RESR, the output end of the voltage dividing resistor R1 is simultaneously connected with the first input end of the driving circuit driver and the bias current setting end of the comparator, one end of the dividing resistor R1 is connected with the drain electrode of the output capacitor internal resistance RESR, the other end of the voltage dividing resistor R2 is grounded, the inverting input end of the comparator is connected with the inverting input end of the voltage dividing resistor R1, the positive end of the PFR 2 is connected with the first output end of the PFM, the PFM is connected with the output end of the positive end of the driving circuit;
the output terminal voltage VOUT is the voltage of the common terminal of the drain electrode of the rectifying tube M1 and the internal resistance RESR of the output capacitor;
The divided voltage of the output end voltage VOUT acts on the comparator as a sampling voltage FB, and the sampling voltage FB is compared with a reference voltage VREF of the comparator; the output signal VEA obtained by the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM module; the output signal of the PFM and the output signal VZERO of the current zero-crossing comparator jointly act on a driving circuit to control the on or off of the power tube M2 or the rectifying tube M1; when the output end voltage VOUT is lower than a preset voltage, the sampling voltage FB is lower than the reference voltage VREF, the output signals VEA of the comparator, the output signals VP and VN of the PFM module and the drive circuit are all high levels, the power tube M2 is conducted, the rectifying tube M1 is cut off, the inductor L stores energy, and the conduction time control circuit starts timing; after reaching the preset time, the on-time control circuit resets the PFM module to enable the output signals of the PFM module to be low level, so that the output signals VN and VP of the driving circuit are low level, the power tube M2 is cut off, the rectifying tube M1 is conducted, the inductor L releases energy to the output end of the circuit, and meanwhile, the current flowing through the zero comparator detects whether the inductor current crosses zero to judge whether the load is heavy load or light load; if the inductance current crosses zero, the output signal VZERO of the current through zero comparator is high level, the load is in light load state, at this time, the bias current of the comparator is reduced by the output signal VZERO of the current through zero comparator, so that the static loss of the circuit is reduced; if the inductor current does not cross zero, the output signal VZERO of the current through the zero comparator is low level, the load is in a heavy load state, and at the moment, the bias current of the comparator is increased by the output signal VZERO of the current through the zero comparator, so that the speed of the comparator is increased, and the working frequency of the circuit is increased.
3. The PFM control-based boost system response speed conversion circuit according to claim 1, wherein when the load is judged to be light load or heavy load according to the output driving signal of the driving circuit, the circuit comprises: the voltage input end VIN, the inductance L, the current zero-crossing comparator, a rectifying tube M1, a power tube M2, a driving circuit driver, a PFM module, a comparator, voltage dividing resistors R1 and R2, an output capacitor COUT, a conduction time control circuit and an output capacitor internal resistance RESR, wherein the rectifying tube M1 is a PMOS tube, and the power tube M2 is an NMOS tube; the voltage input end VIN is grounded after passing through an inductor L, a source electrode and a drain electrode of a rectifying tube M1, an output capacitor internal resistance RESR and an output capacitor COUT in sequence, the voltage input end VIN is grounded after passing through the inductor L and a drain electrode and a source electrode of a power tube M2 in sequence, a grid electrode of the power tube M2 is simultaneously connected with a first output end of a driving circuit driver and a bias current setting end of a comparator, the grid electrode of the rectifying tube M1 is connected with a second output end of the driving circuit driver, a non-inverting input end of the current zero comparator is connected with a source electrode of the rectifying tube M1, a drain electrode of the power tube M2 and a common end of the inductor L, an inverting input end is connected with a drain electrode of the rectifying tube M1 and an output capacitor internal resistance RESR, an output end of the current zero comparator is connected with a first input end of the driving circuit driver, one end of the voltage dividing resistor R1 is connected with a drain electrode of the rectifying tube M1 and a common end of the output capacitor internal resistance RESR, the other end of the voltage dividing resistor R1 is grounded through a voltage dividing resistor R2, and the inverting input end of the comparator is connected with an output end of the positive end PFR 2 of the rectifying tube M2, and the output end of the positive end PFR is connected with the positive end of the output module;
the output terminal voltage VOUT is the voltage of the common terminal of the drain electrode of the rectifying tube M1 and the internal resistance RESR of the output capacitor;
The divided voltage of the output end voltage VOUT acts on the comparator as a sampling voltage FB, and the sampling voltage FB is compared with a reference voltage VREF of the comparator; the output signal VEA obtained by the comparator and the output signal of the on-time control circuit jointly act on the PFM module to change the output frequency of the PFM module; the output signal of the PFM and the output signal VZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the on or off of the power tube M2 or the rectifying tube M1; when the output end voltage VOUT is lower than a preset voltage, the sampling voltage FB is lower than the reference voltage VREF, the output signals VEA of the comparator, the output signals VP and VN of the PFM module and the drive circuit are all high levels, the power tube M2 is conducted, the rectifying tube M1 is cut off, the inductance L stores energy, and the conduction time control circuit starts timing; after reaching the preset time, the on-time control circuit resets the PFM module to enable the output signals thereof to be low level, so that the output signals VN and VP of the driving circuit are low level, the power tube M2 is cut off, the rectifying tube M1 is conducted, the inductor L releases energy to the output end of the circuit, meanwhile, the load is judged to be light load or heavy load according to the first output end of the driver of the driving circuit through the duty ratio of the first output signal VN, when the duty ratio of the first output signal VN is smaller than a set value, the load is in a light load state, at the moment, the bias current of the comparator is reduced by the first output signal VN, so that the static loss of the circuit is reduced, and the high efficiency under light load is kept; when the duty ratio of the first output signal VN is larger than a set value, the load is in a heavy load state, and at the moment, the bias current of the comparator is increased by the first output signal VN, so that the speed of the comparator is increased, and the working frequency of the circuit is increased.
4. The PFM control-based boost system response speed conversion circuit of claim 3, wherein the internal circuit of the comparator includes: the sources of the PMOS pipes P1, P2, P3, P4, NMOS pipes N1, N2, N3, N4, N5, N6, a resistor R0, a capacitor C1 and a bias voltage VBN are respectively connected with a power supply voltage, the drains of the PMOS pipes P1, P2, P3 and P4 are connected with the drain of the NMOS pipe N3, the grid of the PMOS pipe P1 is connected with the grid of the PMOS pipe P2, the source of the NMOS pipe N3 is grounded, the grid of the NMOS pipe N3 is connected with the grid of the NMOS pipe N6, the drain of the NMOS pipe N3 is connected with a grid lead, the drain of the PMOS pipe P2 is connected with the drain of the NMOS pipe N4, the grid of the PMOS pipe P2 is connected with a drain lead, the grid of the NMOS pipe N4 is connected with a sampling voltage FB, the source electrode of the NMOS tube N4, the source electrode of the NMOS tube N5, the drain electrode of the NMOS tube N1 and the drain electrode of the NMOS tube N2 are connected, the source electrode of the NMOS tube N1 is grounded, a first output signal VN of a driving circuit driver is connected with the grid electrode of the NMOS tube N1 and one end of a capacitor C1 through a resistor R0, the other end of the capacitor C1 is grounded, the grid electrode of the NMOS tube N2 is connected with a bias voltage VBN, the source electrode of the NMOS tube N2 is grounded, the drain electrode of the PMOS tube P3 is connected with the drain electrode of the NMOS tube N5, the grid electrode of the PMOS tube P3 is connected with the grid electrode of the PMOS tube P4, the grid electrode of the PMOS tube P3 is connected with a drain electrode conducting wire, the grid electrode of the NMOS tube N5 is connected with a reference voltage VREF of a comparator, the drain electrode of the PMOS tube P4 and the drain electrode of the NMOS tube N6 are connected with the output end of the comparator, and the source electrode of the NMOS tube N6 is grounded;
When the load is light load, the duty ratio of an output signal VN of the driving circuit is smaller than a set value, VN becomes a direct current analog level with small amplitude after being filtered by a resistor R0 and a capacitor C1, and an NMOS tube N1 is turned off, so that the bias current of a comparator is reduced, and the high efficiency of the light load state is maintained; when the load is heavy load, the duty ratio of the output signal VN of the driving circuit is larger than a set value, VN becomes a direct current analog level with larger amplitude after being filtered by a resistor R0 and a capacitor C1, so that the NMOS tube N1 is conducted, the bias current of the comparator is increased along with the increase of the duty ratio of the VN, and the response speed of the comparator is improved.
5. The control method of the boost system response speed conversion circuit based on PFM control is characterized in that the circuit comprises a voltage input end VIN, an inductance L, a current zero-passing comparator, a rectifying tube M1, a power tube M2, a driving circuit, a PFM module, a comparator, voltage dividing resistors R1 and R2, an output capacitor COUT, an output capacitor internal resistance RESR and a conduction time control circuit, and the control method comprises the following steps:
⑴ The output end voltage VOUT is divided by divider resistors R1 and R2 to obtain sampling voltage FB;
⑵ The sampling voltage FB acts on a comparator and is compared with a reference voltage VREF of the comparator, and the comparator obtains an output signal VEA of the comparator;
⑶ The output signal VEA of the comparator and the output signal of the on-time control circuit jointly act on the PFM module to obtain an output signal of the PFM module;
⑷ The output signal of the PFM module and the output signal VZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the power tube M2 and the rectifying tube M1 to be conducted or cut off;
⑸ When the output end voltage VOUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage VREF, the output signals VEA of the comparator, the output signals VP and VN of the PFM module and the drive circuit driver are all high levels, the power tube M2 is conducted, the rectifying tube M1 is cut off, the inductance L stores energy, and the output signals VEA pass through or are output to enable the PMOS tube P2 of the internal circuit of the comparator to be conducted after passing through the NOT gates D2 and D1 of the internal circuit of the comparator and the inverter E1, so that the bias current of the comparator is increased, the response speed of the comparator is improved, and meanwhile, the conduction time control circuit starts timing;
⑹ When the timing reaches the preset time, the on-time control circuit resets the PFM module to enable the output signal of the PFM module to be low level, so that the output signals VN and VP of the driving circuit are also low level, the power tube M2 is cut off, and the rectifying tube M1 is turned on;
⑺ The inductor L releases the energy stored in the step ⑸ to the output end of the circuit, and the current zero-crossing comparator detects whether the inductor current crosses zero to judge whether the load is light load or heavy load;
⑻ If the inductance current crosses zero, the output signal VZERO of the current-passing zero comparator is high level, and the load is in a light load state, at this time, the output signal VZERO outputs high level after passing through the NOT gates D1 and D2 of the internal circuit of the comparator and the inverter E1 to turn off the PMOS tube P2 of the internal circuit of the comparator, so that the output signal VZERO of the current-passing zero comparator reduces the bias current of the comparator, and the static loss of the circuit is reduced and the efficiency is improved;
if the inductance current does not cross zero, the output signal VZERO of the current zero-crossing comparator is low level, the load is in a heavy load state, at this time, the PMOS tube P2 of the internal circuit of the comparator is always conducted, the bias current of the comparator is increased by the output signal VZERO of the current zero-crossing comparator, the comparator keeps a higher response speed, the speed of the comparator is increased, and the working frequency of the circuit is increased.
6. The control method of the boost system response speed conversion circuit based on PFM control is characterized in that the circuit comprises a voltage input end VIN, an inductance L, a current zero-passing comparator, a rectifying tube M1, a power tube M2, a driving circuit, a PFM module, a comparator, voltage dividing resistors R1 and R2, an output capacitor COUT, an output capacitor internal resistance RESR and a conduction time control circuit, and the control method comprises the following steps:
⑴ The output end voltage VOUT is divided by divider resistors R1 and R2 to obtain sampling voltage FB;
⑵ The sampling voltage FB acts on a comparator and is compared with a reference voltage VREF of the comparator, and the comparator obtains an output signal VEA of the comparator;
⑶ The output signal VEA of the comparator and the output signal of the on-time control circuit jointly act on the PFM module to obtain an output signal of the PFM module;
⑷ The output signal of the PFM module and the output signal VZERO of the current zero-crossing comparator jointly act on a driving circuit driver to control the power tube M2 and the rectifying tube M1 to be conducted or cut off;
⑸ When the output end voltage VOUT is lower than the preset voltage, the sampling voltage FB is lower than the reference voltage VREF, the output signals VEA of the comparator, the output signals VP and VN of the PFM module and the drive circuit driver are all high levels, the power tube M2 is conducted, the rectifying tube M1 is cut off, the inductance L stores energy, and the output signals VEA pass through or are output to enable the PMOS tube P2 of the internal circuit of the comparator to be conducted after passing through the NOT gates D2 and D1 of the internal circuit of the comparator and the inverter E1, so that the bias current of the comparator is increased, the response speed of the comparator is improved, and meanwhile, the conduction time control circuit starts timing;
⑹ When the timing reaches the preset time, the on-time control circuit resets the PFM module to enable the output signal of the PFM module to be low level, so that the output signals VN and VP of the driving circuit are also low level, the power tube M2 is cut off, and the rectifying tube M1 is turned on;
⑺ The inductor L releases the energy stored in the step ⑸ to the output end of the circuit, and the first output end of the driving circuit driver judges whether the load is light or heavy according to the duty ratio of the first output signal VN;
⑻ When the duty ratio of the first output signal VN is smaller than a set value, the load is in a light load state, and at this time, the output signal VZERO outputs a high level after passing through the nor gates D1 and D2 of the internal circuit of the comparator and the inverter E1 to turn off the PMOS transistor P2 of the internal circuit of the comparator, so that the bias current of the comparator is reduced by the first output signal VN, the static loss of the circuit is reduced, and the high efficiency under light load is maintained;
When the duty ratio of the first output signal VN is larger than a set value, the load is in a heavy load state, at the moment, the PMOS tube P2 of the internal circuit of the comparator is always conducted, the bias current of the comparator is increased by the first output signal VN, the comparator keeps a higher response speed, the speed of the comparator is increased, and the working frequency of the circuit is increased.
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CN111416505B (en) * 2020-04-14 2021-05-11 上海顺久电子科技有限公司 Switching power supply converter
JP7018095B2 (en) * 2020-07-07 2022-02-09 華邦電子股▲ふん▼有限公司 Power control circuit
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CN114977795B (en) * 2022-06-23 2023-05-23 圣邦微电子(苏州)有限责任公司 DC-DC converter

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8283907B1 (en) * 2009-11-20 2012-10-09 Texas Instruments Incorporated Boost regulator with pulse frequency mode of operation having substantially constant percentage output ripple and frequency
JP2014204536A (en) * 2013-04-03 2014-10-27 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit, and operation method thereof
CN209419485U (en) * 2019-01-14 2019-09-20 泉芯电子技术(深圳)有限公司 Booster system response speed translation circuit based on PFM control

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014007809A (en) * 2012-06-22 2014-01-16 Renesas Electronics Corp Semiconductor integrated circuit and operation method of the same
US9093899B2 (en) * 2013-09-30 2015-07-28 Micrel, Inc. Timer based PFM exit control method for a boost regulator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8283907B1 (en) * 2009-11-20 2012-10-09 Texas Instruments Incorporated Boost regulator with pulse frequency mode of operation having substantially constant percentage output ripple and frequency
JP2014204536A (en) * 2013-04-03 2014-10-27 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit, and operation method thereof
CN209419485U (en) * 2019-01-14 2019-09-20 泉芯电子技术(深圳)有限公司 Booster system response speed translation circuit based on PFM control

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