CN113922811B - BICMOS (binary complementary metal oxide semiconductor) process-based high-speed driving circuit with cold backup and short circuit protection functions - Google Patents
BICMOS (binary complementary metal oxide semiconductor) process-based high-speed driving circuit with cold backup and short circuit protection functions Download PDFInfo
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- CN113922811B CN113922811B CN202110726022.6A CN202110726022A CN113922811B CN 113922811 B CN113922811 B CN 113922811B CN 202110726022 A CN202110726022 A CN 202110726022A CN 113922811 B CN113922811 B CN 113922811B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/20—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage
- H02H3/202—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess voltage for dc systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00392—Modifications for increasing the reliability for protection by circuit redundancy
Abstract
The invention relates to a high-speed driving circuit 100 with cold backup and short-circuit protection functions based on a BICMOS process, which comprises a driving stage 101, a common mode feedback circuit 102, a short-circuit protection circuit 103, a cold backup power bias 104 and other modules. The driving circuit 100 adopts a current mode architecture, after the power-on is completed, the driver 101 starts to work, the common mode feedback circuit 102 ensures that the output working point meets the requirement of a driving level protocol, the short circuit protection circuit 103 monitors the voltage value of the output end, and if the output voltage is abnormal, the short circuit protection circuit closes the driving circuit 101 so as to avoid the circuit from being burnt. The circuit also supports cold-back use, and cold-back power bias 104 controls the leakage current from the output port to the power supply to be within microampere level, and completely cuts off the leakage path from the output port to the power supply. The architecture is suitable for various protocol drivers, meets various use conditions, and has strong protection capability and high-speed driving capability.
Description
Technical Field
The invention relates to a high-speed driving circuit with cold backup and short-circuit protection functions based on a BICMOS (binary complementary metal oxide semiconductor) process, in particular to a high-speed driving circuit controlled by common mode feedback and output short-circuit protection, belonging to the field of high-speed interface circuit design.
Background
The high-speed driving circuit outputs a common mode level in the high-gain amplifier, is sensitive to the change of an input voltage, the characteristics and mismatch of a device and the like, and cannot be stabilized through differential feedback, so that a common mode feedback circuit is required to be added to stabilize the output direct current voltage, and the output direct current level has enough stability.
In addition, if the output end of the driving circuit is short-circuited, the current is increased, and the circuit is burnt out. However, the driver is usually protected, and an additional protection circuit is often required.
Disclosure of Invention
The invention aims to provide a high-speed driving circuit with cold backup and short-circuit protection functions based on a BICMOS process. The driving stage does not need additional protection, and has stronger protection capability and high-speed driving capability.
The invention aims at realizing the following technical scheme: the high-speed driving circuit with cold backup and short-circuit protection functions based on the BICMOS process is a current mode circuit and comprises a common mode feedback module, a driving stage, a cold backup power supply bias module and a short-circuit protection comparator module;
the driving stage starts working after the power-on is completed, and the common mode feedback module ensures that the output working point meets the protocol requirement of the driving stage; the short-circuit protection module is used for monitoring the voltage value of the output end of the driving stage and closing the driving stage when the output voltage is abnormal; the cold backup power supply bias module controls leakage current from the output port of the driving stage to the power supply and is used for completely cutting off a leakage path from the output port to the power supply.
Further, the common mode feedback module comprises a common mode detection module and a common mode comparison amplifier, wherein the common mode detection module is composed of resistors R1 and R2, the common mode potential VIN is detected and output through the serial connection of the resistors R1 and R2, and the common mode comparison amplifier controls the output current through comparing the difference between the reference voltage VREF and the common mode potential VIN, so that the output common mode voltage is adjusted.
Furthermore, the common mode comparison amplifier consists of three stages of operational amplifiers, wherein the first stage adopts a differential input structure to inhibit common mode interference; the second stage adopts an NPN emitter follower structure to provide bandwidth and driving capability, and the last stage adopts a PMOS tube follower structure to adjust an output direct current working point.
Further, the common mode comparison amplifier comprises NMOS transistors N0-N5, PMOS transistors P0-P5 and a triode Q1;
the sources of the NMOS tubes N0, N3, N4 and N5 are grounded GS, the grid electrodes of the N3, N4 and N5 are connected in parallel and then connected with the grid electrode of N0, and the grid electrode of N0 is connected with the drain electrode and then connected with the bias current generated by the reference source; the substrates of the NMOS tubes N1 and N2 are grounded, the grid electrodes are respectively connected with a comparison reference voltage VREF and the sources of common-film potentials VIN, N1 and N2, the sources of the common-film potentials VIN, N1 and N2 are connected in parallel and then connected with the drain electrode of N4, the drain electrodes of the N1 and N2 are respectively connected with the drain electrodes of the PMOS tubes P1 and P2, and the source electrodes of the P1 and P2 are connected with a power supply VCC; the base electrode of the triode Q1 is connected with the drain electrode of the P2, the emitter electrode is connected with the drain electrode of the N5, and the collector electrode is connected with a power supply VCC; the source electrodes of the PMOS tubes P4 and P5 are connected with a power supply VCC, and the grid electrodes of the P4 and P5 are connected with the drain electrode of the P4 and then connected with the drain electrode of the N3; the substrates of the PMOS tubes P0 and P3 are connected with a source VCC, the drain electrode of the P0 is grounded GS, the grid electrode is connected with the drain electrode of the N5, the source electrode of the P3 is connected with the drain electrode of the P5, the grid electrode of the P3 is connected with an enable control signal EN, and the drain electrode of the P3 and the source electrode of the P0 are connected together to be used as the output VO of the common mode comparison amplifier.
Further, the short-circuit protection comparator module comprises two short-circuit protection modules and a logic discrimination circuit; the two short-circuit protection modules respectively compare the output voltage of the driving stage with the reference voltage PVB, output a signal V1 to a logic discrimination circuit according to the magnitude of the output voltage and the reference voltage PVB, and the logic discrimination circuit sends a corresponding enabling signal to a common mode feedback module according to the V1; if the output voltage of the driving stage is greater than the reference voltage PVB, a signal V1 representing normal operation of the driving stage is output, otherwise, a signal V1 representing closing of the main path of the driving stage is output.
Further, the short-circuit protection module comprises a comparator and a secondary protection circuit; the second-stage protection circuit comprises three NMOS tubes N6-N8 and a resistor, wherein the output of the driving stage is connected with the resistor in series and then connected with the input of the comparator and the grid electrode of N7. The substrates of N6 and N7 are grounded, after the source electrodes and the drain electrodes of N6, N7 and N8 are sequentially connected in series, the source electrode of N8 is grounded, the drain electrode of N6 is connected with a power supply VCC, and the grid electrode of N6 and the grid electrode of N8 are respectively connected with the power supply VCC and the ground.
Further, the cold-backup power supply bias module comprises an inverter 401, PMOS tubes P10 and P11 and an NMOS tube N12;
the sources of the PMOS tubes P10 and P11 are connected with the substrate, a cold backup source is generated after the sources of the P10 and P11 are connected, the grid electrode of the P10 is connected with the drain electrode of the P11, the drain electrode of the P10 is connected with the source VCC, the drain electrode of the P11 is connected with the drain electrode of the N12, the grid electrode of the P11 is connected with the output of the inverter, the grid electrode of the N12 is connected with the source VCC, the substrate of the N12 is grounded GS, and the source electrode of the N12 is connected with an enable signal EN;
when EN is effective, P10, P11 and N12 are all conducted, and the cold backup power supply is communicated with the power supply VCC to provide normal bias voltage for the driving stage; when the cold backup is used, EN is invalid, P10 and P11 close the cold backup power supply bias and disconnect the power supply, and cut off the leakage path of the driving stage from output to the power supply.
Compared with the existing driver, the invention has the following advantages:
(1) According to the invention, the common mode level of the common mode feedback circuit stabilizing circuit is used for ensuring that the output working point meets the requirements of a driving level protocol;
(2) The output voltage is protected through the short-circuit protection circuit, the circuit can be protected without additional protection, and the circuit is prevented from being burnt;
(3) The invention supports the use of circuit cold backup, and the application range is wider.
Drawings
FIG. 1 is a schematic diagram of a driving circuit structure;
FIG. 2 is a circuit diagram of a common mode comparison amplifier;
FIG. 3 is a circuit diagram of a short circuit protection module;
FIG. 4 is a diagram of a cold-standby power supply bias circuit.
Detailed Description
The following describes the embodiments of the present invention in detail with reference to the drawings.
The invention relates to a high-speed driving circuit with cold backup and short-circuit protection functions based on a BICMOS process, which comprises a driver (also called a driving stage) 101, a common mode feedback circuit 102, a short-circuit protection circuit 103, a cold backup power bias 104, a logic discrimination circuit 105 and other modules. The driving circuit 101 adopts a current mode architecture, after the power-on is completed, the driving circuit 101 starts to work, the common mode feedback circuit 102 ensures that the output working point meets the requirement of a driving level protocol, the short circuit protection circuit 103 monitors the voltage value of the output end, and if the output voltage is abnormal, the short circuit protection circuit 103 closes the driving circuit 101 so as to avoid the circuit from being burnt. The circuit also supports cold-back use, and the cold-back bias module 104 controls the leakage current from the output port to the power supply within microampere level, and completely cuts off the leakage path from the output port to the power supply. The architecture is suitable for various protocol drivers, meets various use conditions, and has strong protection capability and high-speed driving capability.
The main functions of the driver are as follows: when the enable is effective, completing differential signal output; when the switch is enabled to be turned off, the output is ensured to be in a high-resistance state; when the cold backup is used, the input leakage current is ensured to be extremely small; and when the output is short-circuited, the current is limited and protected.
The common mode feedback circuit 102 detects the output common mode voltage by using a resistor network, detects the output voltage of the output circuit, compares the detected output voltage with a desired common mode voltage, and controls the output voltage of the common mode comparison amplifier 201 by using the detected result.
The common mode feedback circuit 102 mainly comprises a common mode detection module R1/R2 and a common mode comparison amplifier 201, wherein the common mode detection module mainly comprises resistors R1 and R2, and the common mode potential VIN is detected and output through the serial connection of the resistors R1 and R2.
The common-mode comparison amplifier 201 controls the output VO by comparing the difference between the reference voltage VREF and the common-mode potential VIN. The common-mode comparison amplifier 201 is composed of three stages of operational amplifiers, wherein a differential input structure is adopted in a first stage, so that common-mode interference is restrained; the second stage adopts an NPN emitter follower structure to provide larger bandwidth and driving capability, and the most one stage adopts a PMOS tube follower structure to adjust the output VO direct current working point so that the NPN tube of the driving stage works normally. As shown in FIG. 2, the common mode comparison amplifier comprises NMOS transistors N0-N5, PMOS transistors P0-P5 and a triode Q1; the sources of the NMOS tubes N0, N3, N4 and N5 are grounded GS, the grid electrodes of the N3, N4 and N5 are connected in parallel and then connected with the grid electrode of N0, and the grid electrode of N0 is connected with the drain electrode and then connected with the bias current generated by the reference source; the substrates of the NMOS tubes N1 and N2 are grounded, the grid electrodes are respectively connected with a comparison reference voltage VREF and the sources of common-film potentials VIN, N1 and N2, the sources of the common-film potentials VIN, N1 and N2 are connected in parallel and then connected with the drain electrode of N4, the drain electrodes of the N1 and N2 are respectively connected with the drain electrodes of the PMOS tubes P1 and P2, and the source electrodes of the P1 and P2 are connected with a power supply VCC; the base electrode of the triode Q1 is connected with the drain electrode of the P2, the emitter electrode is connected with the drain electrode of the N5, and the collector electrode is connected with a power supply VCC; the source electrodes of the PMOS tubes P4 and P5 are connected with a power supply VCC, and the grid electrodes of the P4 and P5 are connected with the drain electrode of the P4 and then connected with the drain electrode of the N3; the substrates of the PMOS tubes P0 and P3 are connected with a source VCC, the drain electrode of the P0 is grounded GS, the grid electrode is connected with the drain electrode of the N5, the source electrode of the P3 is connected with the drain electrode of the P5, the grid electrode of the P3 is connected with an enable control signal EN, and the drain electrode of the P3 and the source electrode of the P0 are connected together to be used as the output VO of the common mode comparison amplifier.
The short-circuit protection comparator module comprises a short-circuit protection module 103 and a logic discrimination circuit 105, wherein the short-circuit protection module 103 consists of a comparator and a secondary protection circuit 301. The comparator compares the output voltage of the driver with the input reference voltage PVB, if the output voltage is larger than the input reference voltage PVB, the driver works normally, and if the output voltage is larger than or equal to the input reference voltage PVB, the short-circuit protection circuit closes the main path of the driver, and the short-circuit current is limited within the circuit index range. One of the input ports of the comparator is connected to the output, so that the secondary protection circuit 301 is designed to avoid ESD events from burning out internal devices. As shown in FIG. 3, the second-stage protection circuit comprises three NMOS transistors N6-N8 and a resistor, and the output of the driving stage is connected in series with the resistor and then connected to the input of the comparator and the grid electrode of N7. The substrates of N6 and N7 are grounded, after the source electrodes and the drain electrodes of N6, N7 and N8 are sequentially connected in series, the source electrode of N8 is grounded, the drain electrode of N6 is connected with a power supply VCC, and the grid electrode of N6 and the grid electrode of N8 are respectively connected with the power supply VCC and the ground.
As shown in fig. 4, the cold-standby power supply bias circuit includes an inverter 401, PMOS transistors P10 and P11, and an NMOS transistor N12. The sources of the PMOS tubes P10 and P11 are connected with the substrate, a cold backup source is generated after the sources of the P10 and P11 are connected, the grid electrode of the P10 is connected with the drain electrode of the P11, the drain electrode of the P10 is connected with the source VCC, the drain electrode of the P11 is connected with the drain electrode of the N12, the grid electrode of the P11 is connected with the output of the inverter, the grid electrode of the N12 is connected with the source VCC, the substrate of the N12 is grounded GS, and the source electrode of the N12 is connected with an enable signal EN; when EN is effective, P10, P12 and N12 are all conducted, and the cold backup power supply is communicated with the power supply VCC to provide normal bias voltage for the PMOS tube of the driver 101. When the cold backup is used, EN is invalid, and P10 and P12 close the cold backup power supply bias and disconnect the power supply, and cut off the leakage path from the output of the driver to the power supply.
The foregoing is merely illustrative of the best embodiments of the present invention, and the present invention is not limited thereto, but any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be construed as falling within the scope of the present invention.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.
Claims (5)
1. The high-speed driving circuit with the cold backup and short-circuit protection functions based on the BICMOS process is characterized by being a current mode circuit and comprising a common mode feedback module, a driving stage, a cold backup power supply bias module and a short-circuit protection comparator module;
the driving stage starts working after the power-on is completed, and the common mode feedback module ensures that the output working point meets the protocol requirement of the driving stage; the short-circuit protection comparator module is used for monitoring the voltage value of the output end of the driving stage and closing the driving stage when the output voltage is abnormal; the cold backup power supply bias module is used for controlling leakage current from the output port of the driving stage to the power supply and is used for completely cutting off a leakage path from the output port to the power supply; the common mode feedback module comprises a common mode detection module and a common mode comparison amplifier, wherein the common mode detection module consists of resistors R1 and R2, the common mode comparison amplifier is used for detecting and outputting a common mode potential VIN in series through the resistors R1 and R2, and the common mode comparison amplifier is used for controlling the output current and adjusting the output common mode voltage by comparing the difference of a reference voltage VREF and the common mode potential VIN; the common-mode comparison amplifier consists of three stages of operational amplifiers, wherein the first stage adopts a differential input structure to inhibit common-mode interference; the second stage adopts an NPN emitter follower structure to provide bandwidth and driving capability, and the last stage adopts a PMOS tube follower structure to adjust an output direct current working point.
2. The high-speed driving circuit according to claim 1, wherein: the common mode comparison amplifier comprises NMOS transistors N0-N5, PMOS transistors P0-P5 and a triode Q1;
the sources of the NMOS tubes N0, N3, N4 and N5 are grounded GS, the grid electrodes of the N3, N4 and N5 are connected in parallel and then connected with the grid electrode of N0, and the grid electrode of N0 is connected with the drain electrode and then connected with the bias current generated by the reference source; the substrates of the NMOS tubes N1 and N2 are grounded, the grid electrodes are respectively connected with a comparison reference voltage VREF and the sources of common mode potentials VIN, N1 and N2, the sources of the common mode potentials VIN, N1 and N2 are connected in parallel and then connected with the drain electrode of N4, the drain electrodes of the N1 and N2 are respectively connected with the drain electrodes of the PMOS tubes P1 and P2, and the source electrodes of the P1 and P2 are connected with a power supply VCC; the base electrode of the triode Q1 is connected with the drain electrode of the P2, the emitter electrode is connected with the drain electrode of the N5, and the collector electrode is connected with a power supply VCC; the source electrodes of the PMOS tubes P4 and P5 are connected with a power supply VCC, and the grid electrodes of the P4 and P5 are connected with the drain electrode of the P4 and then connected with the drain electrode of the N3; the substrates of the PMOS tubes P0 and P3 are connected with a source VCC, the drain electrode of the P0 is grounded GS, the grid electrode is connected with the drain electrode of the N5, the source electrode of the P3 is connected with the drain electrode of the P5, the grid electrode of the P3 is connected with an enable control signal EN, and the drain electrode of the P3 and the source electrode of the P0 are connected together to be used as the output VO of the common mode comparison amplifier.
3. The high-speed driving circuit according to claim 1, wherein: the short-circuit protection comparator module comprises two short-circuit protection modules and a logic discrimination circuit;
the two short-circuit protection modules respectively compare the output voltage of the driving stage with the reference voltage PVB, output a signal V1 to a logic discrimination circuit according to the magnitude of the output voltage and the reference voltage PVB, and the logic discrimination circuit sends a corresponding enabling signal to a common mode feedback module according to the V1; if the output voltage of the driving stage is greater than the reference voltage PVB, outputting a signal representing normal operation of the driving stage, otherwise, outputting a signal representing closing of a main passage of the driving stage.
4. A high-speed driving circuit according to claim 3, wherein: the short-circuit protection module comprises a comparator and a secondary protection circuit;
the second-stage protection circuit comprises three NMOS tubes N6-N8 and a resistor, wherein the output of the driving stage is connected with the resistor in series and then connected with the input of the comparator and the grid electrode of N7; the substrates of N6 and N7 are grounded, after the source electrodes and the drain electrodes of N6, N7 and N8 are sequentially connected in series, the source electrode of N8 is grounded, the drain electrode of N6 is connected with a power supply VCC, and the grid electrode of N6 and the grid electrode of N8 are respectively connected with the power supply VCC and the ground.
5. The high-speed driving circuit according to claim 1, wherein: the cold backup power supply bias module comprises an inverter 401, PMOS tubes P10 and P11 and an NMOS tube N12;
the sources of the PMOS tubes P10 and P11 are connected with the substrate, a cold backup source is generated after the sources of the P10 and P11 are connected, the grid electrode of the P10 is connected with the drain electrode of the P11, the drain electrode of the P10 is connected with the source VCC, the drain electrode of the P11 is connected with the drain electrode of the N12, the grid electrode of the P11 is connected with the output of the inverter, the grid electrode of the N12 is connected with the source VCC, the substrate of the N12 is grounded GS, and the source electrode of the N12 is connected with an enable signal EN;
when EN is effective, P10, P11 and N12 are all conducted, the cold backup power supply is communicated with the power supply VCC, and normal bias voltage is provided for the driving stage; when the cold backup is used, EN is invalid, P10 and P11 close the cold backup power supply bias and disconnect the power supply, and cut off the leakage path of the driving stage from output to the power supply.
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| CN202110726022.6A CN113922811B (en) | 2021-06-29 | 2021-06-29 | BICMOS (binary complementary metal oxide semiconductor) process-based high-speed driving circuit with cold backup and short circuit protection functions |
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| CN202110726022.6A CN113922811B (en) | 2021-06-29 | 2021-06-29 | BICMOS (binary complementary metal oxide semiconductor) process-based high-speed driving circuit with cold backup and short circuit protection functions |
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| CN113922811A CN113922811A (en) | 2022-01-11 |
| CN113922811B true CN113922811B (en) | 2023-08-29 |
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| CN117097326B (en) * | 2023-10-19 | 2023-12-22 | 四川艾瑞维尔科技有限公司 | Driving circuit compatible with LVDS and HCSL level standards |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109617412A (en) * | 2019-01-14 | 2019-04-12 | 泉芯电子技术(深圳)有限公司 | Booster system response speed translation circuit and its control method based on PFM control |
| CN111158423A (en) * | 2020-03-04 | 2020-05-15 | 广州致远微电子有限公司 | Protection circuit of linear regulator, linear regulation module and equipment |
| CN112667543A (en) * | 2020-12-16 | 2021-04-16 | 北京时代民芯科技有限公司 | Configurable high-speed LVDS driver with short-circuit self-protection function |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109617412A (en) * | 2019-01-14 | 2019-04-12 | 泉芯电子技术(深圳)有限公司 | Booster system response speed translation circuit and its control method based on PFM control |
| CN111158423A (en) * | 2020-03-04 | 2020-05-15 | 广州致远微电子有限公司 | Protection circuit of linear regulator, linear regulation module and equipment |
| CN112667543A (en) * | 2020-12-16 | 2021-04-16 | 北京时代民芯科技有限公司 | Configurable high-speed LVDS driver with short-circuit self-protection function |
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