CN109596976B - Method for testing DSP module in FPGA - Google Patents
Method for testing DSP module in FPGA Download PDFInfo
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- CN109596976B CN109596976B CN201811510144.6A CN201811510144A CN109596976B CN 109596976 B CN109596976 B CN 109596976B CN 201811510144 A CN201811510144 A CN 201811510144A CN 109596976 B CN109596976 B CN 109596976B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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Abstract
The method for testing the DSP module in the FPGA comprises the following steps: aiming at the test items, the PC generates a data file with a suffix of coe and loads the data file into an RAM inside the FPGA; the data file with the suffix coe comprises a pseudo-random number and a result corresponding to the pseudo-random number; completing test program compiling on a PC; downloading a test program to the FPGA, and configuring the FPGA by the test program; reading a pseudo-random number from the RAM as the input of a DSP module in the FPGA; and comparing the output of the DSP module with a result corresponding to the pseudo random number in the RAM to obtain a test result. The testing method of the DSP module in the FPGA realizes the full coverage testing of the DSP function by storing and reading the required pseudo random number by the RAM in the FPGA.
Description
Technical Field
The invention relates to the technical field of detection, in particular to a method for testing a DSP module in an FPGA.
Background
The random function in the computer is simulated according to a certain algorithm, and the result is determined and visible. The probability of occurrence of this predictable result is considered to be 100%, so the "random number" generated by the computer random function is not random, but rather a pseudo-random number. Pseudo-random numbers are not pseudo-random numbers, where "pseudo" is meant to be regular, meaning that a computer-generated pseudo-random number is both random and regular. Because the random number generated by a computer or a calculator has long periodicity, although the random number is not a true random number, the random number can be regarded as random within a certain range because the period is extremely long, so that the difference between the pseudo-random complexity and the true random is not large under the condition of no observation and interference as long as the pseudo-random complexity is high enough. In practice it is often sufficient to use pseudo random numbers and to use the characteristics of the pseudo random numbers to calculate the results obtained by the DSP.
Xilinx corporation uses revolutionary XtreemeDSP in Virtex-4 series of FPGAs to accomplish higher performance digital signal processing. Each DSP Slice has a 2-input multiplier followed by a multiplexer and a 3-input adder/subtractor. The multiplier receives two 18-bit 2's complement operands and produces a 36-bit 2's complement result. The result may be sign extended to 48 bits and may be fed back to the adder/subtractor. The adder/subtractor receives three 48-bit complement-2 operands (of which there is concatenated data and the result data of the accumulated addition and subtraction) and produces a complement-2 result of 48 bits. The cascade may also be implemented to support higher level DSP functions (cascade B bus and cascade P output bus of DSP provide cascading capability).
The Block RAM resource is an 18kb true dual port RAM Block, configurable according to depth and width, and programmable between 16k × 1 to 512 × 36. Each port is fully synchronized and independent, providing three "read while write" modes. Block RAMs can be cascaded to implement large embedded memory modules. In addition, the new functions supported by the Virtex-4FPGA comprise a back-end pipeline register, a clock circuit, a built-in FIFO support and byte write enable.
Disclosure of Invention
The invention aims to provide a method for testing a DSP module in an FPGA (field programmable gate array), which realizes the full-coverage test of the DSP function by storing and reading required pseudo-random numbers by using an RAM (random access memory) in the FPGA.
In order to achieve the above object, the present invention provides a method for testing an internal DSP module of an FPGA, comprising: aiming at the test items, the PC generates a data file with a suffix of coe and loads the data file into an RAM inside the FPGA; the data file with the suffix coe comprises a pseudo-random number and a result corresponding to the pseudo-random number; completing test program compiling on a PC; downloading a test program to the FPGA, and configuring the FPGA by the test program; reading a pseudo-random number from the RAM as the input of a DSP module in the FPGA; and comparing the output of the DSP module with a result corresponding to the pseudo random number in the RAM to obtain a test result.
According to the testing method of the DSP module in the FPGA, aiming at different testing items, the pseudo random number corresponding to the testing item and the result corresponding to the pseudo random number are generated.
According to the testing method of the DSP module in the FPGA, the test items comprise a multiplier function test, an A: B function test, a DSP cascade function test and an addition/subtraction function test.
According to the testing method of the DSP module in the FPGA, corresponding testing programs are compiled according to different testing items.
According to the testing method of the DSP module in the FPGA, if the output of the DSP module is consistent with the result corresponding to the pseudo random number in the RAM, the testing item of the DSP module meets the requirement, and if the output of the DSP module is inconsistent with the result corresponding to the pseudo random number in the RAM, the testing item of the DSP module does not meet the requirement.
According to the testing method of the DSP module in the FPGA, the testing state and the testing result are visually displayed through the LED indicating lamp.
According to the testing method of the DSP module in the FPGA, one test item is finished, the FPGA is continuously configured, and the test is continuously carried out until all the test items are finished.
Compared with the prior art, the invention has the beneficial technical effects that:
the testing method of the DSP module in the FPGA realizes the full coverage testing of the DSP function by storing and reading the required pseudo random number by the RAM in the FPGA.
Drawings
The testing method of the DSP module inside the FPGA of the invention is given by the following embodiments and the attached drawings.
FIG. 1 is a schematic diagram of a test system according to the present invention.
FIG. 2 is a flow chart of the testing method of the DSP module inside the FPGA of the present invention.
Detailed Description
The method for testing the DSP module inside the FPGA according to the present invention will be described in further detail with reference to fig. 1 to 2.
FIG. 1 is a schematic diagram of a test system according to the present invention.
As shown in fig. 1, in order to implement the testing of the DSP module inside the FPGA, the testing system adopted by the present invention includes a PC and an FPGA testing interface board; the FPGA and the peripheral circuit thereof are arranged on the FPGA test interface board; the FPGA test interface board is also provided with an LED indicator light; the PC is used for compiling a DSP test program and compiling DSP data generation software, the DSP data generation software generates a data file with coe suffix, and the data file with coe suffix comprises pseudo-random numbers and results corresponding to the pseudo-random numbers; the result corresponding to the pseudo random number is a result (correct result) which is obtained by taking the pseudo random number as the input of a DSP module in the FPGA and calculating by the DSP module, and the result corresponding to the pseudo random number is used as a judgment basis for the test result of the DSP module; depending on the nature of the pseudo random numbers, the corresponding result of the pseudo random numbers is predictable.
Fig. 2 is a flowchart of a testing method of the DSP module inside the FPGA according to the present invention.
Referring to fig. 2, the method for testing the DSP module inside the FPGA includes:
1) for the test item, the PC generates a data file with coe suffix, wherein the data file with coe suffix and the corresponding result of the pseudo-random number;
aiming at different test items, DSP data generation software in the PC generates pseudo random numbers corresponding to the test items and results corresponding to the pseudo random numbers; for each test item, the DSP data generation software generates a data file with a suffix coe;
2) loading a data file with a suffix of coe into a RAM inside the FPGA;
loading a data file with coe suffix of each test item into an RAM inside the FPGA;
3) completing test program compiling on a PC;
writing corresponding test programs aiming at different test items;
4) downloading a test program to the FPGA, and configuring the FPGA by the test program;
5) reading a pseudo-random number from the RAM as the input of a DSP module in the FPGA; comparing the output of the DSP module with a result corresponding to the pseudo random number in the RAM to obtain a test result;
reading a pseudo random number corresponding to a test item from an RAM as the input of a DSP module in the FPGA, and comparing the output of the DSP module with the result corresponding to the pseudo random number during comparison;
if the output of the DSP module is consistent with the result corresponding to the pseudo random number in the RAM, the test item of the DSP module is indicated to meet the requirement, and if the output of the DSP module is inconsistent with the result corresponding to the pseudo random number in the RAM, the test item of the DSP module is indicated to not meet the requirement;
the test state and the test result can be displayed through the LED indicating lamp, namely the test state and the test result are visually displayed through the LED indicating lamp;
automatically testing after the FPGA configuration is finished, wherein the testing process is controlled by a written testing program;
6) repeating the steps 4) to 5) until all the function tests are completed;
and when one function test is finished, the FPGA is continuously configured and the test is continuously carried out until all functions are tested.
The testing method of the DSP module in the FPGA realizes the full coverage testing of the DSP function by storing and reading the required pseudo random number by the RAM in the FPGA.
The testing method of the FPGA internal DSP module is described by taking XC4VSX55 in Virtex-4 series of Xilinx company as an example.
XC4VSX55 contains 512 DSPs, and aiming at the specific functions of the DSPs, a DSP data generation software is written by C + + to generate pseudo-random numbers with a certain number of digits and corresponding results of each pseudo-random number after certain operation (operation corresponding to the function) of the DSP, a data file with a suffix of coe is generated, the data file with the suffix of coe is loaded into a RAM inside XC4VSX55, and the utilization rate of the RAM reaches 100 percent: the RAM contains the input data and correct results of the DSP. And writing a test program, and performing automatic test after the configuration of the FPGA is completed.
(1)18 x 18 multiplier function test
The 512 DSPs were tested in parallel with OPMODE set to 7' B0000101, i.e. P ═ a × B. According to the DSP's instruction manual, P is 48 bits and A, B are all 18 bits, thereby determining that the maximum depth of data to be loaded into RAM is 69632 and the width is 84 bits. Obtaining a pseudo-random number meeting the requirements by C + + programming and generating a data file with a suffix coe, the data file with a suffix coe comprising: a ═ ram _ data [17:0], B ═ ram _ data [35:18], P ═ ram _ data [83:36], P is the corresponding a × B result (number of 48 bits of sign bit extension); the data file with the suffix coe is loaded into RAM. And completing the configuration of the FPGA according to a written test program of the 18 x 18 multiplier. And comparing the P serving as a reference with 48-bit output of the DSP, and judging whether the function of the DSP 18 multiplied by 18 multiplier meets the requirement or not through the LED lamp.
(2) A: B functional test
512 DSPs were tested in parallel with OPMODE set to 7' B0000011, i.e., P ═ a: B. According to the DSP's instruction manual, P is 48 bits and A, B are all 18 bits, thereby determining that the maximum depth of data to be loaded into RAM is 69632 and the width is 84 bits. Obtaining a pseudo-random number meeting the requirements by C + + programming and generating a data file with a suffix coe, the data file with a suffix coe comprising: b ═ ram _ data [17:0], a ═ ram _ data [35:18], P ═ ram _ data [83:36], P is the corresponding a: B result (number of 48 bits of sign bit extension); the data file with the suffix coe is loaded into RAM. And completing the configuration of the FPGA according to the written test programs A and B. And comparing the P serving as a reference with 48-bit output of the DSP, and judging whether the functions of the DSP A and the DSP B meet the requirements through the LED lamp.
(3)35 x 35 multiplier function test
According to the instruction manual of the DSP, dynamic OPMODE is required for the 35 × 35 multiplier function test, and OPMODE is set to 7 ' B0000101, 7 ' B1100101/7 ' B1010101, 7 ' B0100101/7 ' B0010101, and 7 ' B1100101/7 ' B1010101, respectively, that is, P ═ a × B, P ═ shift (P)/shift (PCIN) + a × B, P ═ P/PCIN + a × B, P ═ shift (P)/shift (PCIN) + a × B. There are two implementation modes, 1 DSP adopts dynamic OPMODE, or 4 DSPs each complete one OPMODE, and the result is obtained in a cascade form. This embodiment is implemented by using 1 DSP, that is, 512 DSPs are tested in parallel. Where A, B are all 35 bits and P is 70 bits, it can be determined that the maximum depth of data to be loaded into RAM is 41472 and the width is 140 bits. Obtaining a pseudo-random number meeting the requirements by C + + programming and generating a data file with a suffix coe, the data file with a suffix coe comprising: a ═ ram _ data [34:0], B ═ ram _ data [69:35], P ═ ram _ data [139:70], P being the result of the corresponding a × B; the data file with the suffix coe is loaded into RAM. And completing the configuration of the FPGA according to a written test program of the 35 x 35 multiplier. Taking P as a reference, dividing P into three parts (36 bits, 17 bits and 17 bits) to be compared with corresponding bits in three outputs of the DSP respectively, and judging whether the function of the DSP 35 multiplied by 35 multiplier meets the requirement through the LED.
(4) Cascading functional testing of DSPs
512 DSPs are distributed in 8 horizontal columns and 64 vertical columns, and the cascading mode is vertical cascading, namely cascading from the first to the last of each column.
The first is to test PCIN + BCIN. With subscribe set to 1 'B1, A-1, the first DSP in each column with OPMODE set to 0000101, i.e., P-A × B-B, B is 18 bits, so that the first DSP in each column results in B, the OPMODEs of the other DSPs are set to 7' B0010101, i.e., P-PCIN-A × B-PCIN + BCIN, the results of each DSP in the cascade are incremented by A multiple of B, and the last DSP in each column should result in 64 times the first DSP. It was thus determined that the RAM should contain data having a maximum depth of 327680 and a width of 18 bits, and the data was loaded into the RAM. The configuration of the FPGA is completed according to the written test program of the test item, 512 DSP columns are tested in parallel, and each column is in series. Due to the limitation of self resources of the FPGA, the result of each DSP cannot be verified, only whether the result of the last DSP in each column is correct is verified, and whether the function meets the requirement is judged through the LED.
The second term is test shift (PCIN) + BCIN. Sustrct is set to 1' b0, with a ═ 1. The OPMODE of the first DSP in each column is set to 0000101, i.e., P ═ a × B ═ B, so that the result of the first DSP in each column is B, B is 18 bits, and OPMODEs of the other DSPs are set to 7' B1010101, i.e., P ═ shift (pcin) + a × B ═ shift (pcin) + BCIN, thereby determining that the RAM should contain data with a maximum depth of 327680 and a width of 18 bits, and loading the data into the RAM. And completing the configuration of the FPGA according to the written test program of the test item. 512 DSP columns are tested in parallel with columns, each column itself being serial. The item is to verify whether the result of each DSP is correct or not, and judge whether the function meets the requirement or not through an LED.
(5) 48-bit 3-input adder functional test
OPMODE is set to 7' b0111110, that is, P ═ C + P, which is equal to the operation of realizing an accumulation, and it is not necessary to accumulate it indefinitely, so that only one accumulation is performed, that is, P ═ C + P ═ 2C +2C ═ 4C, C is 48 bits, and each time an accumulation is performed, the register is automatically reset and cleared, so that the result of each DSP should be 4C, and the RAM should contain data with a maximum depth of 121344 and a width of 48 bits, and the data is loaded into the RAM. And completing the configuration of the FPGA according to the written test program of the test item, and judging whether the function meets the requirement through the LED.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (1)
- The method for testing the DSP module in the FPGA is characterized by comprising the following steps:aiming at the test items, the PC generates a data file with a suffix of coe and loads the data file into an RAM inside the FPGA; the data file with the suffix coe is a pseudo-random number and a result corresponding to the pseudo-random number;completing test program compiling on a PC;downloading a test program to the FPGA, and configuring the FPGA by the test program;reading a pseudo-random number from the RAM as the input of a DSP module in the FPGA; comparing the output of the DSP module with the result corresponding to the pseudo random number in the RAM to obtain a test result, and generating the pseudo random number corresponding to the test item and the result corresponding to the pseudo random number aiming at different test items, wherein the test items comprise a multiplier function test and A: b, function test, DSP cascade function test and addition/subtraction function test; writing corresponding test programs aiming at different test items; if the output of the DSP module is consistent with the result corresponding to the pseudo random number in the RAM, the test item of the DSP module is indicated to meet the requirement, and if the output of the DSP module is inconsistent with the result corresponding to the pseudo random number in the RAM, the test item of the DSP module is indicated to not meet the requirement; the test state and the test result are visually displayed through an LED indicator lamp; and (4) after one test item is finished, continuously configuring the FPGA and continuously testing until all the test items are finished.
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