JP2019133591A - FPGA design support method and program - Google Patents

Abstract

To design an FPGA so as to exercise a function equal to a digital circuit before changing even when RTL description is changed to reduce the number of logical gates.SOLUTION: An FPGA design support method comprises the steps of: receiving information of one or more input signals and an output signal of target logic 121 which is a portion of a conversion target of RTL description 120; obtaining a value of the output signal by means of simulation when the one or more input signals of the target logic 121 is exhaustively changed; and creating memory estimation stereotype description 123 so as to replace with the target logic 121. The memory estimation stereotype description 123 uses one or more input signals as an address of a memory block of the FPGA, and is described to use the output signal obtained by means of the simulation as data stored in the address.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to an FPGA (Field Programmable Gate Array) design support method and program, and in particular, can be used to create an RTL (Register Transfer Level) description for FPGA design.

  The FPGA is reconfigurable hardware and includes a plurality of programmable logic cells, a memory, a DSP (Digital Signal Processor, for example, a multiplier), and the like. Then, a desired digital circuit can be realized by combining these with a changeable wiring.

  The number of logic cells and multipliers built in the FPGA (more generally, the number of logic gates) and the memory capacity are determined for each product. Therefore, depending on the FPGA product, the number of logic gates is insufficient, and there are often cases where a digital circuit having a desired function cannot be mounted on the FPGA.

  To cope with this problem, the design has been changed to reduce the functions of the digital circuit, change to an expensive FPGA product with more logic gates that can be mounted, or perform time-sharing processing by sharing resources I often do. For example, Patent Literature 1 discloses a design support program that reduces the circuit amount by performing circuit conversion that shares a common part of a design target system. In this case, the common part is executed by a plurality of modules by time division.

JP 2009-223661 A

  If the product is changed to a product with a large number of logic gates in order to deal with the above-mentioned problem of the insufficient number of logic gates in the FPGA, there is a problem in terms of cost. Further, when the common part is operated by time-division operation as in Patent Document 1, since functional restrictions are added, there is a case where the same operation as the original circuit cannot be performed.

  This disclosure takes the above-mentioned problems into consideration, and the purpose of this disclosure is to enable the FPGA to perform the same function as the digital circuit before the change even when the RTL description is changed so as to reduce the number of logic gates. An FPGA design support method that can be designed is provided.

  According to an embodiment, an FPGA design support method executed by a computer is provided. The FPGA design support method includes a step of receiving an RTL description used in FPGA design, a step of receiving information on one or more input signals and output signals of a target logic that is a part to be converted in the RTL description, and a target A step of obtaining by simulation a value of an output signal when one or more input signals of logic are exhaustively changed, and a step of generating a memory estimation fixed form description to replace the target logic. Here, the memory estimation fixed description is described so that one or more input signals described above are used as addresses of the memory block, and an output signal obtained by simulation is used as data stored at the address of the memory block.

  The memory estimation fixed description is a fixed description determined so that the logic synthesis tool selects a memory when the RTL description is logically synthesized.

  According to the above embodiment, the target logic included in the RTL description is replaced with the memory estimation fixed form description having the same input / output relationship. As a result, even when the RTL description is changed so as to reduce the number of logic gates, the FPGA can be designed so as to exhibit the same function as the digital circuit before the change.

It is a typical top view which shows an example of a structure of FPGA. It is a flowchart which shows the design procedure of FPGA. It is a flowchart which shows the modification of FIG. It is a functional block diagram for demonstrating the method of replacing a logic circuit with memory. It is a flowchart which shows the procedure of replacing a logic circuit with a memory. It is a figure for demonstrating the process which can be selected as object logic. FIG. 6 is a block diagram illustrating an example of a configuration of a computer for executing the steps of FIGS. 3 and 5. FIG. 5 is a diagram illustrating an example of a part of an RTL description including the target logic of FIG. It is a figure which shows an example of the input screen for performing the information input of FIG.5 S310. It is a figure which shows an example of the memory estimation fixed form description of FIG. It is a figure which shows an example of the test bench description of FIG. It is a figure which shows an example of the dump data of FIG. It is a flowchart which shows the procedure which changed the production | generation and execution of the test bench of step S320 of FIG. It is a figure which shows the example of the test bench description for fixing the value of a specific bit to 0. In Embodiment 2, it is a figure which shows the example of the information extracted from a target logic in order to produce | generate a memory estimation fixed form description and a test bench description.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

Embodiment 1 FIG.
[FPGA and its design method]
In the following, an exemplary configuration of an FPGA that is a premise of the present disclosure and an outline of a design method thereof will be described.

FIG. 1 is a schematic plan view showing an example of the configuration of an FPGA.
Referring to FIG. 1, the FPGA 100 includes, as an example, a plurality of logic cells 101, a plurality of memory blocks 102, a plurality of DSPs (multipliers, etc.), wiring elements (not shown) connecting them, and a chip And a plurality of input / output elements (not shown) arranged on the outer periphery. In FIG. 1, for ease of illustration, six logic cells 101, three memory blocks 102, and three DSPs 103 are shown, but in reality, a larger number of circuit elements are provided. It has been.

  The logic cell 101 includes a look-up table (LUT), a flip-flop (FF) for realizing a sequential circuit, and a selector. The function of the combinational circuit using a plurality of logic gates can be realized by the LUT.

  The memory block 102 is a dedicated area used as a memory, and has, for example, an SRAM (Static Random Access Memory) structure.

  FIG. 2 is a flowchart showing the FPGA design procedure. FIG. 3 is a flowchart showing a modification of FIG. FIG. 3 is obtained by adding the behavioral description 110 and the high-level synthesis S201 to FIG. Therefore, the other parts of FIG. 3 are the same as those of FIG. The following steps can be realized, for example, when a CPU (Central Processing Unit) 141 of the computer 140 shown in FIG. 7 executes a program.

  Referring to FIG. 2, in FPGA design, first, an RTL description 111 that describes the operation of a digital circuit at a register transfer level (RTL) using a hardware description language (HDL) is prepared. As shown in FIG. 3, the RTL description 111 may be synthesized by the CPU 141 from the behavioral description 110 in C language or the like by high-level synthesis (step S201).

  Next, a netlist 112 indicating the connection relationship between the logic cell 101, the memory block 102, and the DSP 103 is generated from the RTL description 111 by logic synthesis and technology mapping (step S202). Logic synthesis refers to generating a netlist representing a plurality of logic elements such as logic gates and flip-flops and their connection relations from the RTL description 111. Technology mapping refers to assigning logic elements included in the netlist to each element of the FPGA.

  Next, configuration data 113 is generated by inputting the generated netlist to the placement / wiring tool (step S203). The configuration data 113 is data for programming logic elements and wiring switches in the FPGA. Finally, the design of the FPGA is completed by downloading the configuration data 113 to the configuration memory in the FPGA (step S204).

  Note that, in hardware description languages such as Verilog HDL and VHDL, an environment (step S205) for performing simulation is prepared in the hardware description language. This simulation environment is called a test bench, test description, or the like.

[Problems in FPGA design]
The number of logic cells, memory capacity, and number of multipliers built in the FPGA are determined for each product. Therefore, depending on the FPGA product, the number of logic cells and multipliers (more generally, the number of logic gates) is insufficient, so that there is often a problem that a digital circuit having a desired function cannot be mounted on the FPGA.

  In order to address this problem, the present disclosure presents a method for replacing a part of the logic gate part of the FPGA described in the RTL description with a memory. Specifically, output signals that can be taken when the input signals of the logic to be replaced are exhaustively given are obtained in advance by simulation. Then, the input signal is used as an address, and the corresponding output signal is stored in the memory as a value corresponding to the address. The description of the target logic is replaced with a description that reads and outputs the value of the memory according to the input signal (referred to as a memory estimation fixed description). This will be specifically described below.

[Replacement method of logic circuit to memory]
FIG. 4 is a functional block diagram for explaining a method of replacing a logic circuit with a memory. FIG. 5 is a flowchart showing a procedure for replacing a logic circuit with a memory.

  Each step in FIG. 5 can be realized, for example, by a CPU (Central Processing Unit) 141 of the computer 140 shown in FIG. The program or script 122 may be VBA such as spreadsheet software or Shell used in Linux (registered trademark), and any means for realizing it may be used.

  Referring to FIGS. 5 and 6, in first step S300, CPU 141 determines target logic 121 to be stored in memory among RTL descriptions 120 described in the hardware description language, or a predetermined target logic. 121 information is received. The CPU 141 may automatically determine the target logic 121 during the high-level synthesis S201 in FIG.

  The target logic 121 is limited to one in which an output signal is uniquely determined when one or more input signals are determined. Therefore, the target logic 121 is limited to logic that can be pipelined or zero-cycle processing. A specific example of the target logic 121 will be described later with reference to FIG.

  In the next step S310, the CPU 141 acquires the input signal name, output signal name, clock signal name, latency, reset signal name, and superior information of the target logic. The latency is the number of clock cycles necessary for the target logic 121 to perform processing. These pieces of information may be automatically extracted by the CPU 141 from the given RTL description 120 and target logic 121 information.

  In the next step S320, the CPU 141 generates the test bench 124. The test bench 124 is an environment for simulating the target logic 121, and is configured using a hardware description language. The test bench 124 includes a part 125 that describes input data to the target logic 121, a part 120A that instantiates the RTL description 120, and a part that writes an output signal obtained by simulation for each input signal to an output variable. Including.

  The CPU 141 comprehensively gives all input patterns to the target logic 121 by executing the test bench 124 (that is, gives information on all possible inputs (0, 1)) (S321). Is obtained by simulation (S322). The CPU 141 stores the obtained output as dump data in the RAM 142 of FIG. 7 or the external storage device 144 (S323).

  In the next step S330, the CPU 141 generates a memory estimation fixed form description 123. Step S330 may be executed before step S320 or in parallel with step S320.

  Here, the memory estimation fixed description 123 is a fixed description determined so that the logic synthesis tool (step S202) in FIG. 3 selects a memory when the RTL description 120 is logically synthesized.

  In the case of the first embodiment given as an example, in the memory estimation fixed description 123, the memory address is a bit combination of one or more input signals of the target logic, and the read data is an output signal corresponding to the input signal. Is the value of In step S204 of FIG. 3, when the configuration data 113 is downloaded to the FPGA, the dump data 126 is transferred to the memory block 102 of the FPGA 100 of FIG.

In the next step S340, the CPU 141 replaces the target logic 121 in the RTL description 120 with the memory estimation fixed form description 123. By causing the logic synthesis tool in step S202 of FIG. 3 to read the replaced RTL description 120, the logic synthesis tool recognizes the memory as a corresponding element according to the memory estimation fixed description 123. The dump data 126 is written so as to be read by the memory estimation fixed description 123, and therefore stored in a directory read by the logic synthesis tool according to the memory estimation fixed description 123 at the time of logic synthesis.
As described above, the target logic can be replaced with a memory.

[Examples of processing that can be selected as target logic]
FIG. 6 is a diagram for explaining processes that can be selected as the target logic. 6A and 6B show processes that can be selected as the target logic, and FIGS. 6C and 6D show processes that cannot be selected as the target logic.

  Referring to FIG. 6A, process 1 (P1) is executed on the input signal, and process 2 (P2) is executed on the output of process 1 (P1). In this case, since the output is uniquely determined when the input is determined, a series of processes can be selected as the target logic 121.

  Referring to FIG. 6B, the input signal is stored in flip-flop FF1 in accordance with the clock signal. At the next clock, processing 1 (P1) is performed on the value stored in flip-flop FF1, and the result of processing 1 (P1) is stored in flip-flop FF2. At the next clock, processing 2 (P2) is performed on the value stored in flip-flop FF2, and the result of processing 1 (P2) is stored in flip-flop FF3. Then, the value stored in the flip-flop FF3 is output. Therefore, since the output is uniquely determined when the input is determined, a series of processes can be selected as the target logic 121.

  In the series of processes shown in FIG. 6C, the process 1 (P1) performs the process based on the point that the output of the flip-flop FF2 is input to the process 1 (P1) and the outputs of both the flip-flops FF1 and FF2. This is different from the process shown in FIG. As described above, when the internal information of the flip-flop FF1 and the internal information of the flip-flop FF2 are combined, the output is not uniquely determined in one cycle, and therefore cannot be selected as the target logic 121.

  In the series of processes shown in FIG. 6D, the process 2 (P2) performs the process based on the point that the output of the flip-flop FF1 is input to the process 2 (P2) and the outputs of both the flip-flops FF1 and FF2. This is different from the process shown in FIG. As described above, when the internal information of the flip-flop FF1 and the internal information of the flip-flop FF2 are combined, the output is not uniquely determined in one cycle, and therefore cannot be selected as the target logic 121.

  Note that the simulation time increases as the number of input bits (when there are a plurality of input signals, the total number of bits obtained by concatenating the plurality of input signals) increases. Furthermore, the capacity of the memory block 102 to be used increases with the square of the number of input bits. Therefore, it is preferable to determine the number of input bits of the target logic 121 according to the processing capability of hardware resources such as a CPU (for example, 16 bits or less).

[Computer configuration example]
FIG. 7 is a block diagram showing an example of the configuration of a computer for executing the steps of FIGS. 3 and 5.

  Referring to FIG. 7, a computer 140 includes a CPU 141, a RAM 142, a ROM (Read Only Memory) 143, an external storage device 144 such as a nonvolatile memory, an input interface 145 such as a keyboard, a mouse, and a touch panel, A display 146 such as a liquid crystal monitor and a network interface 147 such as a wired LAN (Local Area Network) and a wireless LAN are provided.

  The CPU 141 can execute the steps shown in FIGS. 3 and 5 by executing a program stored in the external storage device 144 as a non-temporary storage medium. Further, the computer 140 can be considered to constitute an FPGA design support apparatus for executing the FPGA design support program shown as the script 122 in FIG. 4 and the flowchart in FIG.

[Specific examples of RTL description, fixed memory description, test bench description, dump data]
Hereinafter, specific examples of the RTL description 120, the memory estimation fixed form description 123, the test bench 124, the dump data 126, etc. in FIG. 4 will be described.

(Example of RTL description including target logic)
FIG. 8 is a diagram showing an example of a part of the RTL description including the target logic of FIG. The RTL description shows an example of the verilog HDL, but any language such as VHDL or systemverilog may be used as long as it is an RTL description.

  The first line indicates that the module name of the RTL description 120 is “SAMPLE”.

  The processing contents of the target logic 121 are shown in the 21st to 32nd lines. The target logic 121 outputs the product of the square of the input signal SIGNALA [3: 0] and the square of SIGNALB at the positive edge of the clock signal. The target logic 121 outputs 0 at the negative edge of the reset signal.

(Example of information input screen)
FIG. 9 is a diagram showing an example of an input screen for inputting information in step S310 of FIG.

  In the 151st column, the input signal name information of the target logic 121 extracted from the RTL description 120 of FIG. In column 152, information on the bit width of each input signal is extracted from RTL description 120 and input.

  In the 153rd column, the module name of the RTL description 120 including the target logic 121 is input. In the 154th column, the language of the RTL description 120 is entered. The reason for specifying the language of the RTL description 120 is to create the test bench description 124 and the memory estimation fixed form description 123 in the language.

  A clock signal name is input in the 155th column, and a latency is input in the 156th column. The reason why the clock signal name and the latency are required is to instruct the script 122 how many cycles the data should be captured when the dump data 126 is generated by the test bench description 124.

  The reset signal name is input in the 157th column, and its superiority is input in the 158th column. The reason why the reset signal name and its superiority are necessary is that the dump data 126 cannot be correctly generated by the test bench description 124 unless the reset signal is negated.

  In the 159th column, the information of the output signal name of the target logic 121 is input to the script 122 from the description of the RTL description 120 of FIG. In the 160th column, the bit width information of the output signal is extracted from the RTL description 120 and inputted.

  In the 161st column, the module name of the memory used in the memory estimation fixed form description 123 is designated.

  In the example of FIG. 9, when the user selects the button 172 described as “ROM implementation”, automatic generation of the memory estimation fixed form description 123 and the test bench description 124 is started based on the above input. .

(Example of fixed memory description)
FIG. 10 is a diagram illustrating an example of the memory estimation fixed form description of FIG.

  FIG. 10A shows a description example of an instance of a memory estimation fixed form description. Instead of the target logic 121 shown in the 21st line to the 32nd line of the RTL description 120 in FIG. 8, the memory estimation fixed form description 123 can be used by pasting the description in FIG.

  In the 23rd row of FIG. 10A, the address of the memory is specified as a value obtained by bit-coupling the input signal SIGNALA [3,0] and the input signal SIGNALB. In the 24th row, the value of the memory is designated as the output signal RESULT.

  FIG. 10B shows a module output as a memory estimation fixed description. In line 51, the name of the RTL to be output, that is, the module name “aun” is declared. As described in FIG. 10A, the module of FIG. 10B is instantiated and described instead of the target logic 121 of the RTL description 120 of FIG.

  In line 53, the address bit width of the memory is specified. The address bit width of the memory is equal to the total number of bits of the input signals SIGNALA and SIGNALB.

  In line 54, the data width of the memory is specified. The data width of the memory is equal to the bit width of the output signal RESULT.

  In line 66, the value of the data name “aundata.txt” as the dump data 126 is read as the initial value of the memory rom. The start address is 0, and the final address is 2 ** PADDR_WIDTH-1.

  From the 69th line to the 71st line, output is made to wait for the number of latency settings. FIG. 10B shows one cycle, but if the latency increases, the number of shift registers described in this row is increased.

(Example of test bench description)
FIG. 11 is a diagram illustrating an example of the test bench description of FIG.

  When the test bench description 124 of FIG. 11 is executed, a comprehensive input pattern from the minimum value to the maximum value of the input signal is given to the target logic 121 as an input signal by increasing the variable i by 1. The output signal is uniquely determined according to the input signal given to the target logic 121. The output value of the target logic 121 is stored in the output variable ROM every cycle after a cycle corresponding to the specified latency has passed. Finally, information stored in the output variable ROM is output as text data.

  In line 103, the total number of bits of the input signal is described. This total value is used as the address bit width of the memory and is used as the maximum value of the input signal that is comprehensively input.

  In line 104, the bit width of the output signal is described. This bit width is associated with the data width of the memory.

  In lines 109 to 114, a pseudo clock provided on the test bench is generated. The RTL description 120 of FIG. 8 instantiated on the test bench is driven by this clock.

  In lines 116 to 120, the release of the reset signal RST is described in positive logic. In line 135, when the RTL description 120 (module name: SAMPLE) is instantiated, the value obtained by logically inverting “˜” of the reset signal RST is given to the RTL description 120 to the input RTL, whereby the reset advantage information described in FIG. Is realized. Instead of this description, the release of the reset signal RST may be described by negative logic.

  In line 123, variable i is forcibly input to the input signal. In the 123rd line, “SAMPLE.SIGNALA” means the signal name SIGNALA included in the instantiated module SAMPLE (that is, the RTL description 120 in FIG. 8).

  As shown in the 122nd line, the forced input in the 123rd line is repeated up to the number of times that the input bit width is raised to the power of 2, while increasing the variable i by 1 from 0. As a result, values of 0 and 1 are comprehensively given to each bit of the input signal (that is, all input patterns are input to the target logic 121).

  After changing the input signal, in line 124, data is captured after the cycle using latency information. If the latency increases, the weight of this description increases accordingly.

  In line 126, the output signal of target logic 121 is stored in output variable ROM. By repeating the 122nd to 126th lines described above, the process is repeated until all bits of the input signal are toggled, thereby generating output values corresponding to all input patterns of the target logic 121.

  In line 129, the data stored in the output variable ROM is output to the text file “aundata.txt”. The output data is used in the memory estimation fixed form description 123.

  In line 135, the RTL description 120 (module name: SAMPLE) of FIG. 8 is instantiated. The input shown in line 123 above is given to the instantiated RTL description 120.

(Dump data)
FIG. 12 is a diagram illustrating an example of the dump data of FIG. In the example of FIG. 12, output data is described in order from the 0th address.

[effect]
As described above, according to the first embodiment, since the usage rate of the logic cell included in the FPGA becomes 100%, it is possible to cope with a situation in which all the functions of the logic circuit included in the RTL description cannot be mounted in the FPGA. can do. Specifically, the RTL description is changed so as to reduce the number of logic gates by replacing a part of the logic circuit portion included in the RTL description with a memory estimation fixed description having the same input / output relationship. As a result, functions equivalent to those of the digital circuit before the reduction of the number of logic gates can be mounted on the FPGA.

Embodiment 2. FIG.
In the second embodiment, a method for reducing the capacity of the memory block 102 of the FPGA used as a result of replacing the target logic will be described. Specifically, bits that are not used in the target logic 121 in the input signal are not stored in the memory block 102. Hereinafter, it will be described in detail with reference to the drawings.

  FIG. 13 is a flowchart showing a procedure in which the generation and execution of the test bench in step S320 of FIG. 5 are changed. Each of the following procedures is realized by executing a program by the CPU 141 in FIG.

  First, when the specific input bit of the target logic 121 is fixed to 0 and the other inputs are exhaustively changed (step S400), the CPU 141 obtains the output of the target logic for each input by simulation (step S401). ).

  Next, when the specific input bit is fixed to 1 and the other inputs are exhaustively changed (step S402), the CPU 141 obtains the output of the target logic for each input by simulation (step S403).

  In the next step S404, if there is no change in output between the case where the specific input bit is 0 and the case where the specific input bit is 1, the CPU 141 determines that the specific input bit is an unnecessary bit.

  In the next step S405, the CPU 141 determines whether or not all bits of the input signal have been set to specific bits. If all the bits of the input signal are not set to specific bits, the CPU 141 changes the specific bits to unset bits (step S406) and repeats the above steps S400 to S405. The above steps S400 to S406 correspond to identifying unnecessary bits.

  When all bits of the input signal are set to specific bits (YES in step S405), the CPU 141 comprehensively changes the input bits excluding all unnecessary bits with respect to the target logic 121 (step S407). In step S408, an output for each input is obtained by simulation. In the next step S409, the CPU 141 stores the obtained output as dump data in the RAM 142 or the external storage device 144.

  FIG. 14 is a diagram illustrating an example of a test bench description for fixing the value of a specific bit to 0.

  After the variable i is input to the input signal as shown in line 152 of FIG. 14, the input signal is overwritten with “0” in bit 2 of the input signal SIGNALA, which is a specific bit, as shown in line 153. The value of bit 2 of SIGNALA can be fixed to “0”.

  FIG. 15 is a diagram illustrating an example of information extracted from the target logic in order to generate the memory estimation fixed form description and the test bench description in the second embodiment. The example of FIG. 15 corresponds to FIG. 9 of the first embodiment.

  FIG. 15 shows a case where bit 2 of the input signal SIGNALA is an unnecessary bit. In this case, SIGNALA [2] is not extracted as an input signal name, and other input signals SIGNALA [1: 0], SINGNLA [3], and SIGNALB are extracted.

[effect]
As described above, according to the second embodiment, whether or not each bit of the input signal is used in the target logic 121 is determined in steps S400 to S405. In steps S407 and S408 described above, output signals corresponding to all input signal patterns of the target logic 121 are obtained by simulation, except for unnecessary bits that are not used in the target logic 121. In step S409, the simulation result is stored in the storage device as dump data. This dump data is finally transferred to the memory block 102 of the FPGA 100 in FIG. Accordingly, the portion related to the unnecessary bits is not stored in the memory block 102, so that the necessary capacity of the memory block 102 can be reduced.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  100 FPGA, 101 logic cell, 102 memory block, 103 DSP, 111, 120 RTL description, 121 target logic, 122 script, 123 memory estimation fixed form description, 124 test bench description, 126 dump data, 140 computer, 141 CPU, 142 RAM 144 External storage device.

Claims (7)

A step in which a computer receives an RTL (Register Transfer Level) description used in FPGA (Field Programmable Gate Array) design;
Receiving the information of one or more input signals and output signals of the target logic that is a part to be converted in the RTL description;
Obtaining a value of the output signal by simulation when the computer comprehensively changes the one or more input signals of the target logic;
The computer generating a memory estimated boilerplate description to replace the target logic;
The FPGA is described in such a manner that the one or more input signals are used as addresses of memory blocks, and the output signals obtained by simulation are used as data stored at the addresses of the memory blocks. Design support method. The step of obtaining by the simulation is as follows:
Generating a test bench description;
Executing the test bench description,
The test bench description is
A part for instantiating the RTL description;
A part for comprehensively inputting values as the one or more input signals;
The FPGA design support method according to claim 1, further comprising: a part that inputs the value of the output signal to an output variable for each value of the one or more input signals. The step of receiving the information further receives latency information,
In the test bench description, the part to be input to the output variable is the value of the output signal when a time corresponding to the latency has elapsed after the values of the one or more input signals are input to the target logic. The FPGA design support method according to claim 2, wherein: is input to the output variable. In the step of receiving the information, a reset signal and its superior information are further received,
The FPGA design support method according to claim 2, wherein the test bench description includes a portion for releasing the reset signal. The computer further comprising identifying unwanted bits included in the one or more input signals;
The step of identifying the unnecessary bits includes:
The value of the output signal in the first case in which 0 is input to specific bits of the one or more input signals and the other bits are changed comprehensively, 1 is input to the specific bits, and the other bits Obtaining the value of the output signal in the second case in which
Determining the specific bit as an unnecessary bit when the value of the output signal in the first case matches the value of the output signal in the second case,
The step of obtaining by the simulation obtains the value of the output signal when the other bits excluding the unnecessary bits of the one or more input signals of the target logic are comprehensively changed by simulation. 2. The FPGA design support method according to 1.   The FPGA design support method according to claim 1, wherein the target logic uniquely determines a value of the output signal with respect to the one or more input signals. The program for making a computer perform the FPGA design assistance method of any one of Claims 1-6.

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