JPH0696151A - Logic simulator - Google Patents

Abstract

PURPOSE:To provide the logic simulator which can deal with a large scale circuit as well while effectively utilizing the high degree of parallelism provided for an emulator. CONSTITUTION:This device is provided with an emulator 4 composed of a host computer 1, emulation chips 6, input/output interface 2 and network 5. The host computer 1 sets a program corresponding to each circuit of a simulation object to the emulator 4, and the emulator 4 constitutes a prescribed circuit by changing the internal connection of emulation chips 6 and setting the connection of the network 5 basing on the program of the host computer 1. The divided circuit of the simulation object is mapped to this circuit, the emulated result is stored in the input/output interface 2, and the stored contents of the input/output interface 2 are applied to the circuit of the emulator 4 reconstituted by mapping the other divided circuit of the simulation object.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation device used for simulating a logic circuit.

[0002]

2. Description of the Related Art Recently, in designing a digital system using a logic circuit, simulating the logic circuit has become an indispensable element for shortening the system development period and satisfying a high degree of completion. There is.

Conventionally, it has been considered that a logic circuit is simulated by software. However, this method requires a long calculation due to its enormous amount of calculation, resulting in a simulation turnaround time. It took a long time.

Therefore, in order to perform such a simulation easily, a hardware simulation engine specialized in the simulation has been developed.

Simulation engines are roughly classified into the following two types. One is an event-driven simulation engine that processes and simulates events in a logic circuit by a dedicated simulation processor. The other is mapping the logic circuit to programmable elements such as field program gate arrays. It is an emulator that performs emulation by doing. The technique of this emulator is disclosed, for example, in Japanese Patent Laid-Open No. 2-245831.

[0006]

However, the former event-driven simulation engine can handle a large-scale circuit, but the parallelism originally present in the simulation target is limited to the number of process processors. There is a problem that it is difficult to speed up.The latter emulator can obtain high speed because the target parallelism is used as it is, but the circuit scale is limited by the size of the emulator, so large scale circuits can not be handled. There was a problem that it did not exist.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic simulation apparatus capable of handling a large-scale circuit while taking advantage of the high parallelism of the emulator.

[0008]

A logic simulation apparatus of the present invention is an emulation having a host computer, an input / output interface, a programmable emulation chip, and a programmable network connecting the emulation chip and the input / output interface. The emulation device, the host computer sets each of program information corresponding to a plurality of divided circuits to be simulated to each of a plurality of banks existing in a memory built in the emulation device, The device changes the internal connection of the emulation chip by switching the bank, and sets the connection of the network into a predetermined circuit so that these circuits can be connected to the simulation pair. Of the divided circuit, the emulation result is stored in the input / output interface, and the memory content of the input / output interface is reconfigured by mapping the divided other circuit of the simulation target. Is configured to be given to.

[0009]

As a result, according to the present invention, instead of inputting a signal from the host computer one by one to change the circuit configuration, the program information representing the configuration of each circuit is put in the bank of the memory built in the emulation device at once. ,
During simulation, the configuration can be changed simply by switching banks without host intervention, so the emulator to be simulated can be executed in a time-sharing manner, and with the same scale of program elements, the high parallelism of the emulation device can be achieved. It becomes possible to handle a large-scale simulation target while making the most of.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of the entire apparatus. The device includes a host computer 1, an input / output interface 2, a host interface 3, and an emulation device 4.
It is composed by. The emulation device 4 here includes a network 5, a plurality of emulation chips 6, a memory module 7, and an emulation controller 8.

In this case, the simulation target is mapped to the plurality of emulation chips 6 forming the emulation device 4. Since these emulation chips 6 are composed of universal functions called primitives, the simulation is performed. The target is converted into a primitive, a primitive netlist is generated, and mapping is performed.

In this state, mapping information is downloaded from the host computer 1 through the host interface 3 and the emulation controller 8 to the network 5, emulation chip 6 and memory module 7 of the emulation device 4. The emulation chip 6 and the memory module 7 here are connected to each other by the network 5 and emulate a simulation target.

When an input vector (input pattern) to the simulation target is given from the host computer 1 to the emulation device 4 via the input / output interface 2, the emulation device 4 executes the execution condition given via the host interface 3. Emulates the simulation target and outputs the result as an output vector via the input / output interface 2.
Here, the bank switching of the emulation chip 6 and the network switching are performed by the emulation controller 8
Controlled by. Further, the memory module 7 is used to emulate a memory portion to be simulated. Further, the emulation controller 8 controls the bank switching of the emulation chip 6 and the network switching.

The input / output interface 2 is used to emulate a storage element to be simulated and give a value to the next phase described later. The host interface 3 is used to observe and control the internal state of the emulation device 4 from the host computer 1.

FIG. 2 shows a schematic structure of the emulation chip 6, which is composed of a plurality of primitives 61 and a crossbar switch 62. In this case, the signal comes in at the left input and goes out at the right output. Further, both the crossbar switch 62 and the primitive 61 have their configurations given from storage elements of a plurality of banks, and each bank can be switched by a bank signal.

FIG. 3 shows a schematic configuration of the primitive 61. The inputs A, B, C and D together with the bank signal are
It is given as an address of the function memory 611. The function memory 611 outputs 1-bit data as the output of the function. The information of the function memory 611 here is set using the bank setting path.

FIG. 4 shows a schematic structure of the crossbar switch 62 of the emulation chip 6. In the figure,
Although it has 6 inputs and 2 outputs, the expansion is performed by increasing the number of inputs of the multiplexer 621 and the number of the multiplexers 621. The switching of the multiplexer 621 is performed by the data from the output switching memory 622, and the bank signal specifies the bank of the output switching memory 622. The bank setting path is the output switching memory 6
22 is downloaded.

FIG. 5 shows a schematic configuration of the network 5. The network 5 is formed by connecting emulation chips 6 and memory modules 7 in multiple stages via crossbar switches 51. When the input from the host computer 1 is transmitted to the network 5 via the input / output interface 52, the output from the network 5 is transmitted to the host computer 1. In this case, the input / output interface 52 returns the signal from the output of the final stage of the multi-stage configuration to the input of the first stage. Further, the connection of the crossbar switch 51 of the network 5 is determined by the contents of the memory bank selected by the bank signal, similarly to the configuration of the crossbar switch 62 described in FIG. Connection information is downloaded from the host computer 1 to this memory bank through a bank setting path.

FIG. 6 shows a schematic configuration of the input / output interface 52. In this case, the input / output interface 52
Is composed of an output vector register 521 for n bits, a cycle register 522, and an output control memory 523. The output vector register 521 holds the output from the final stage of the network and is read to the host by the host read signal. Also, output vector register 5
The enable of each bit of 21 is controlled by the output control memory 523 and holds the value of the required phase.

Here, the phase means executing one divided part of the simulation object which is time-divided as shown in FIG.

FIG. 8 shows the structure of one bit of the cycle register 522. In this case, cycle register 5
Reference numeral 22 denotes three functions of (a) holding the input vector from the host computer 1, (2) holding the value of the storage element to be simulated in each phase, and (3) passing the value from one phase to another phase. Used for one purpose.
The cycle register 522 has two sets of registers which are switched by a cycle signal, that is, the cycle 0 register 522
1 and a cycle 1 register 5222, which are switched by a cycle signal which is switched alternately for each simulation clock of the simulation object.

In this case, when the cycle signal is 1, the output from the emulation device 4 is accumulated in the cycle 1 register 5222, and at the same time, the input is given from the cycle 0 register 5221 to the emulation device 4. When the simulation clock advances by one, the cycle signal becomes 0, the input from the cycle 1 register 5222 is given to the emulation device 4 contrary to the previous case, and the output from the emulation device 4 is accumulated in the cycle 0 register 5221. Thus, the two cycle registers 522
By alternately operating 1 and 5222, the value of the memory element to be simulated is held. These two sets of cycle registers 5221 and 5222 constitute a shift register having a depth of m, and one stage corresponds to each time-divided phase, and a value is output from any stage of the shift register through a multiplexer. So that it can be taken out. Therefore, the value of the storage element to be simulated is given to the emulation device 4 in an arbitrary phase.

The host computer 1 is connected to the cycle register 522.
In order to hold the input vector from, the input multiplexer 5223 is switched by the host write signal, the cycle signal is set to 0, and it is written in the cycle 0 register 5221 by the emulation clock. Next, the output of the cycle 0 register is the input control memory 522.
According to the value previously written in 4, the multiplexer 52
23 is switched, and the cycle signal is set to 1 to be applied from the data output to the input of the first stage of the network.

Transmission of a value from one phase to the next is performed by the phase forward FF 5225. In the phase forward FF 5225, the signal of the previous phase is latched by the emulation clock, the output multiplexer 5226 is switched, and the data output is given to the emulation device 4. By making the phase-forward FF 5225 a shift register having a depth of m, any value of the previous phase can be used as long as it is the value of the previous phase. The phase forward memory 52 determines which phase value is used.
The value previously downloaded from the host computer is used for 27.

The output of the cycle register 522 is selected by the input control memory 5224 loaded in advance from the host computer 1. The address of the input control memory 5224 is a bank signal indicating whether the current phase is being executed.

Here, the time division simulation is performed in the following procedure.

(1) In the case of cycle signal 0 (1).

(2) Cycle 1 (0) register 5222
A value is given to the first stage of the network 5 from the FF of a certain phase of (5221) or the phase forward FF 5225.

(3) A signal is transmitted to the network 5 and the emulation chip 6.

(4) Signals from the network 5 and the emulation chip 6 are cycle 0 (1) register 522.
1 (5222) is shifted in by the emulation clock. At the same time, it is also latched in the phase forward FF 5225.

(5) The bank signal is switched to switch the connection for the next phase.

(6) Repeat (2) to (5) for the required number of phases.

(7) One simulation cycle is completed when all the phases are completed. The cycle signal is switched to execute the next cycle.

Finally, the output of the emulation device 4 is added to the input / output interface 52 from the final stage.
It is latched in the output vector register by the emulation clock and given to the host computer 1 by the host read signal. Since the output vector is given from each phase, a bit-wise clock enable is given from the output control memory to capture the appropriate value for each phase.

In order to debug the simulation target, a scan path for debugging is prepared in the cycle 0 register 5221 and the cycle 1 register 5222. By accessing the scan path for debugging from the host computer, the value of the storage element to be simulated can be known.

FIG. 9 shows a schematic configuration of the memory module 7. The memory module is composed of the RAM 71 and peripheral circuits. When reading from the memory module 7, the address given in a certain phase and the CS signal are read by the R
The output signal is output to the data output in the next phase. Writing to the memory module 7 is performed by supplying the address, data, CS signal, and WE signal given in a certain phase to the RAM 71. The input / output signal of the memory module is latched by the phase clock in order to stabilize the input / output of the RAM 71 of the memory module 7.

The primitive conversion and mapping of the simulation target by the device configured as described above are shown in FIG.
It is executed by the software shown in 0.

In this case, the simulation target 101 is converted into a primitive (shown in 102) and a primitive netlist is generated (shown in 103). The mapping software 104 is then used to determine how to map the primitives to the emulation device 4. The mapping software 104 here assigns which primitive to which part of which emulation chip, and the connection in the emulation chip 6, the connection of the network 5, and the connection of the input / output interface 2 in a time-division target of simulation. How to allocate is determined, and data to be loaded in each bank of the emulation chip 6, the network 5, and the memory of the input / output interface 2 is generated as mapping data (illustration 105).

Then, this mapping data is loaded into the emulation device 4 by the emulator control software 106. Further, the emulator control software 106 gives an input from the console 107 and an input vector 108 to the emulation device 4, obtains an output vector 109 while controlling the emulation device 4,
This is displayed on the console 107.

FIG. 11 shows the concept of converting a simulation target into a primitive. In this case, each primitive has four inputs and one output. Then, if five elements are used as shown in FIG. 11A, a 4-input primitive is used as shown in FIG.
It can be realized with individual primitives.

There are various methods for collecting a plurality of elements into a primitive, but the following method is known as an example.

(1) One of the outputs is selected and the element to be output to that node is used as a primitive. Here, when the primitive has 5 or more inputs, it is divided into multiple stages so that the number of inputs is 4 or less.

(2) When the number of inputs of the primitive is less than 4, one of the inputs of the primitive is selected and the element output to the input is included in the primitive to check whether the number of inputs is 4 or less.

(3) When the number of inputs of a primitive exceeds 4, the element output to that input is stopped from being included in the primitive and registered as a primitive.

(4) When the input of the primitive is less than 4, the operation from (2) is repeated.

Using such a method, the primitives are put together so that all the elements are included in the primitive starting from the output.

Note that this method is just an example, and this method and some heuristics may be applied for efficient use of primitives.

The simulation object thus converted into the primitive netlist is mapped to the emulation device 4, and the mapping of the primitive netlist to the emulation device 4 is performed in the following procedure.

(1) Register the primitive netlist as an old wave front.

(2) The old wave front is set in the first stage of the emulation device 4, and the primitives are taken out one by one from the netlist and assigned to the primitives in the emulation chip of the emulation device 4. At the same time, advance the wave front.

(3) When the allocation is stopped, the signal is transmitted to the last stage of the emulation device.

(4) The wave front is all of the output,
It ends when all the simulation targets are passed. If it is not finished, the wave front is repeated as the old wave front from (2).

In the procedure shown above, the number of wavefront signal lines may exceed the number of output signal lines of the emulation device 4. In that case, the wave front is further divided into a plurality of sections and the division is carried out in a time division manner.

Next, a specific example of mapping the logic circuit will be described.

Here, the decimal counter "TEXAS INSTRUMENT model number SN74A" is used.
LS168 ".

FIG. 12 shows an internal equivalent circuit of such a decimal counter. By performing primitive conversion on this circuit, the primitive netlists shown in FIGS. 13A to 13D are generated.

Then, this circuit is used as shown in FIG.
One primitive 131 is accommodated in one chip 132, these chips 132 are connected in multiple stages by three crossbar switches 133 to 135, and a total of 6 inputs are transmitted from the host computer via the input / output interface 130. The case of mapping to an emulation device composed of chips will be described.

First, the circuit for producing the RCO signal shown in FIG. 13A is mapped to the emulation device as phase 1 (FIG. 15). In this case, the wave front cannot be further advanced due to the input restriction.

Next, the phases are switched to phase 2 shown in FIG. In this case, the wave front is shown in Figure 12.
To Q and S to obtain intermediate signals T1 and T2, and these signals are passed to the next phase through the phase forward FF.

In phase 3 shown in FIG. 17, T1, T2
Is made with P and N8 'is output, and N6' is made at the same time. Further, N7 'is created in phase 4 shown in FIG. 18 and phase 5 shown in FIG. 19, and finally N5' is created in phase 6 shown in FIG. 20 and phase 7 shown in FIG.

In this way, the wavefront can cover all the outputs and the memory element (FF) to be simulated in seven phases while switching each phase.

[0063]

According to the present invention, instead of inputting a signal from the host computer to change the circuit configuration, the program information representing the configuration of each circuit is put in the bank of the memory built in the emulation device at once. , At the time of simulation, the configuration can be changed simply by switching the bank without intervention of the host, so that the emulator to be simulated can be executed in a time-sharing manner, and with the same size program element,
It is possible to handle large-scale simulation targets while taking advantage of the high parallelism of the emulation device.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of an emulation chip of one embodiment.

FIG. 3 is a diagram showing a schematic configuration of a primitive according to an embodiment.

FIG. 4 is a diagram showing a schematic configuration of a crossbar switch according to an embodiment.

FIG. 5 is a diagram showing a schematic configuration of a network according to an embodiment.

FIG. 6 is a diagram showing a schematic configuration of an input / output interface according to an embodiment.

FIG. 7 is a diagram for explaining a phase of an embodiment.

FIG. 8 is a diagram showing a schematic configuration of a cycle register of one embodiment.

FIG. 9 is a diagram showing a schematic configuration of a memory module of one embodiment.

FIG. 10 is a diagram showing an overall configuration of software according to an embodiment.

FIG. 11 is a diagram for explaining the concept of primitive conversion according to an embodiment.

FIG. 12 is a diagram showing an example of a specific circuit for explaining mapping of a logic circuit.

FIG. 13 is a diagram showing a primitive net list of the specific example of FIG. 12;

14 is a diagram showing an emulation device used in the specific example of FIG.

FIG. 15 is a diagram showing phases of the specific example of FIG. 12;

FIG. 16 is a diagram showing phases of the specific example of FIG. 12;

FIG. 17 is a diagram showing phases of the specific example of FIG. 12;

FIG. 18 is a diagram showing phases of the specific example of FIG. 12;

FIG. 19 is a diagram showing phases of the specific example of FIG. 12;

FIG. 20 is a diagram showing a phase of the specific example of FIG. 12;

FIG. 21 is a diagram showing phases of the specific example of FIG. 12;

[Explanation of symbols]

1 ... Host computer, 2 ... Input / output interface, 3 ... Host interface, 4 ... Emulation device, 5 ...
Network, 6 ... Multiple emulation chips, 7
... memory module, 8 ... emulation controller, 61 ... primitive, 62 ... crossbar switch,
51 ... Crossbar switch, 52 ... Input / output interface, 521 ... Output vector register, 522 ... Cycle register, 523 ... Cycle control memory, 52
21 ... Cycle 0 register, 5222 ... Cycle 1 register, 5223 ... Multiplexer, 5224 ... Input control memory, 5225 ... Phase forward FF,
5226 ... Multiplexer, 611 ... Function memory, 62
1 ... Multiplexer, 622 ... Output switching memory, 71
... RAM.

Claims (1)

[Claims] 1. A host computer, an input / output interface, an emulation device having a programmable emulation chip and a programmable network connecting the emulation chip and the input / output interface, and the host computer is a simulation target. Each of the program information corresponding to the plurality of divided circuits is set for each of a plurality of banks existing in the memory built in the emulation device, and the emulation device switches the inside of the emulation chip by switching the bank. By changing the connection and setting the connection of the network and configuring it into a predetermined circuit, the divided circuit to be simulated is mapped to these circuits and the emulation connection thereof is performed. Is stored in the input / output interface, and the storage content of the input / output interface is given to a circuit of the emulation device reconfigured by mapping of the divided other circuit of the simulation target. .