CN115952755A - ATPG (automatic transfer printing) library model generation system of synchronizer standard unit - Google Patents
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Abstract
The invention relates to an ATPG library model generation system of a synchronizer standard unit, which realizes the step E1 of obtaining the synchronizer standard unit to be processed and a fourth liberty file; step E2, extracting K s A state table of (2); step E3, extracting K s The timing information, the third logic information and the register sequence; e4, generating a third target ATPG library model with the same logic as the third logic information; e5, setting each register unit RF u Will RF u Is connected to the RF u+1 The third target ATPG library model is connected to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u To generate the target ATPG library model. The invention simplifies A of the standard unit of the synchronizerAnd in the generation process of the TPG library model, the generation efficiency of the ATPG library model of the synchronizer standard unit is improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an ATPG library model generation system of synchronizer standard cells.
Background
Automatic Test Pattern Generation (ATPG) is a process in which Test vectors used in semiconductor chip testing are automatically generated by a program. Test vectors are sequentially loaded onto the input ports of the device, and the output signals are collected and compared with the budgeted test vectors to determine the results of the test. ATPG effectiveness is an important indicator for measuring test error coverage. The ATPG is realized by constructing an ATPG library model corresponding to the standard unit and generating a chip based on the ATPG library model; and designing an ATPG model corresponding to the gate-level netlist, and automatically generating a test vector through an ATPG tool to test the chip.
The traditional ATPG library model is generated based on the Verilog model corresponding to the standard cell, which is developed for accurate simulation and verification and is not suitable for ATPG purposes. For example, to accurately describe the simulation behavior, the Verilog model corresponding to the standard cells of the IO pad type is very complex. As another example, standard cells of Integrated Clock Gating (ICG) are designed for clock gating, and the corresponding Verilog model is also very complex. However, ATPG only concerns the logic behavior of the digital circuit, and the ATPG library model is generated based on these complex Verilog models, so that the generation of the ATPG library model is complex, and further, the ATPG model corresponding to the generated design gate-level netlist is not simplified enough, and the test efficiency is reduced.
In addition, the prior art usually displays the design gate level netlist through a Graphical User Interface (GUI) so as to debug the design gate level netlist and the ATPG process. The standard cells in the design gate-level netlist, the connection relationships among the standard cells, and the input and output values generated by the standard cells based on the ATPG model are usually directly shown in the prior art. However, the occupied area of some standard cells is large, the composition details in the standard cells cannot be directly displayed, readability is poor, if the composition detail information needs to be acquired, the corresponding standard cells need to be clicked one by one to present the composition details, and the occupied area of the expanded standard cells is further increased, so that debugging efficiency is low, and user experience is poor.
Disclosure of Invention
The invention aims to provide an ATPG library model generation system of a synchronizer standard unit, which simplifies the generation process of the ATPG library model of the synchronizer standard unit and improves the generation efficiency of the ATPG library model of the synchronizer standard unit.
The invention provides an ATPG (automatic transfer printing) library model generation system of a synchronizer standard unit, which comprises a pre-constructed ATPG basic unit library { A } 1 ，A 2 ，…A M }, memory and processor storing computer programs, A m When the processor executes the computer program, the following steps are implemented:
step E1, acquiring a synchronizer standard unit set { K ] to be processed 1 ,K 2 ,…K S H and a fourth liberty file, K s The standard unit of the synchronizer to be processed is the S-th standard unit of the synchronizer to be processed, the value range of S is 1 to S, S is the total number of the standard units of the synchronizer to be processed, K 1 ,K 2 ,…K S Belonging to the same standard cell library to be processed;
step E2, extracting each K from the fourth liberty file s Corresponding state table, K s The corresponding state table comprises a plurality of second state records, wherein each second state record comprises L(s) input fields and T(s) output fields, and the L(s) input fields comprise a second enabling input field, a selection signal field and L(s) -2 data input fields; the second enable input field is used for storing a first edge trigger state and a second edge trigger state, the selection signal field, the other L(s) -2 data input fields and the T(s) output fields are used for storing corresponding level states, and the level states comprise a first level state and a second level state; when the second enable input field is in the first edge trigger state, the T(s) output fields are determined based on the logic relation of the selection signal field and the L(s) -2 data input fields; when the second enabled input field is the secondWhen the edge triggers the state, keeping the current state of T(s) output fields unchanged; the jth output field corresponds to K s Output state of the jth register, K s T(s) registers are included;
step E3, from K s Extracting K from corresponding state table s Corresponding sequence information, third logic information and a register sequence (RE) in which T(s) registers are arranged in a connection order 1 ，RE 2 ，…RE T(s) ),RE u Is K s The value range of u is 1 to T(s);
step E4, from { A 1 ，A 2 ，…A M Selecting at least one A m Combining generation with K s A third target ATPG library model with the same logic of the corresponding third logic information;
step E5, setting K s Each RE in u Corresponding register unit RF u Each RF u Including valid signal port, data input port and output port, RF u Is connected to the RF u+1 The third target ATPG library model is connected to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u Valid signal port of, generating K s Corresponding target ATPG library models.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the ATPG library model generation system of the synchronizer standard unit can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
the system generates the ATPG library model aiming at the logic information based on the ATPG basic unit library by extracting the time sequence information, the logic information and the connection relation among the registers in the state table of the synchronizer standard unit and combining the ATPG library model with the connection relation among the clock information and the registers to generate the ATPG library model of the synchronizer standard unit, thereby simplifying the generation process of the ATPG library model of the synchronizer standard unit and improving the generation efficiency of the ATPG library model of the synchronizer standard unit.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a flow chart of ATPG library model generation according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating the generation of the ATPG library model of the combinational logic standard cell according to the second embodiment of the present invention;
FIG. 3 is a schematic diagram of a generation flow of an ATPG library model of an integrated clock gating standard cell according to a third embodiment of the present invention;
FIG. 4 is a state representation of an integrated clock gating standard cell according to a third embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a generation flow of an ATPG library model of a standard cell of a synchronizer according to a fourth embodiment of the present invention;
FIG. 6 is a state representation of a standard cell of a synchronizer according to a fourth embodiment of the present invention;
fig. 7 is a schematic diagram illustrating a target display structure according to a fifth embodiment of the present invention;
fig. 8 is a schematic diagram of converting the gate-level netlist of the chip design to be tested into a display based on a target display structure according to the fifth embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the following detailed description will be given with reference to the accompanying drawings and preferred embodiments of an ATPG library model generation system of a synchronizer standard cell according to the present invention.
Aiming at the technical problems that the traditional ATPG library model is generated based on a Verilog model corresponding to a standard unit, ATPG only focuses on the logic behavior of a digital circuit, and the ATPG library model is generated based on the complex Verilog models, so that the ATPG library model generation efficiency is low, the ATPG library model is complex, the ATPG model corresponding to the generated design gate-level netlist is not simplified enough, and the test efficiency is reduced, the first embodiment is provided.
The first embodiment,
The embodiment I provides an ATPG library model generation system which comprises a pre-constructed ATPG basic unit library { A } 1 ，A 2 ，…A M }, memory and processor storing computer programs, A m The value range of M is 1 to M for the mth ATPG basic unit in the ATPG basic unit library, M is the total number of the ATPG basic units in the ATPG basic unit library, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Composition structure of (A2) m Is A m Logical information of (A3) m Is A m Weight value of (A) m Weight value of and A m Inversely proportional to the cost of ATPG, the more easily ATPG can handle the higher the weight value of the basic unit, and when the processor executes the computer program, as shown in fig. 1, the following steps are implemented:
step S1, obtaining a standard cell library { B ] to be processed 1 ，B 2 ，…B N } and a first liberty file, B n The value of N is 1 to N, N is the nth standard cell in the standard cell library to be processed>>M, each B is stored in the first liberty file n Corresponding logic information and timing information therein.
The step S1 specifically obtains a standard cell library { B ] to be processed from preset process design information 1 ，B 2 ，…B N And a first liberty file.
The standard cell library comprises a version library, a symbol library, a circuit logic library and the like. The design method specifically comprises combinational logic, sequential logic, functional units and special type units, and is a basic part in the back end design process of the integrated circuit chip. And the automatic logic synthesis and layout wiring are carried out by using the pre-designed optimized library unit, so that the design efficiency can be greatly improved. Usually, each process manufacturer provides corresponding targets under each processA quasi cell. For example, a 7nm standard cell library, a 10nm standard cell library, etc. provided by the process manufacturer. Each standard cell library may include thousands of standard cells, some standard cells are very complex, for example, a 7nm standard cell library may include tens of thousands of standard cells, a gate-level netlist of a chip design to be tested is generated based on the standard cell library, and since ATPG cannot directly and effectively process a final gate-level netlist of the chip design to be tested, an ATPG library model of each standard cell needs to be abstracted to generate an ATPG model corresponding to the chip design to be tested. Each ATPG library model is based on ATPG basic unit library { A 1 ，A 2 ，…A M Generation, that is, generation of thousands of standard cells in the same or different standard cell libraries based on the same small number of ATPG basic cells, has universality. Preferably, N is of the order of 10 1 For example, 30 ATPG basic cells may be provided.
The first liberty file is a file including standard cell timing information and logic information, and both the first liberty file and the standard cell library can be directly obtained from preset Process Design information (PDK for short), which is not described herein again.
S2, extracting B from the first liberty file n Corresponding logic information to be processed.
Wherein the first liberty file stores B n Corresponding Boolean functions or truth tables, B can be directly connected n The corresponding boolean function or truth table is used as the logic information to be processed, and the truth table can also be converted into the boolean function as the logic information to be processed.
Step S3, based on at least one A m Generating a combination of logical information and constituent structure of (A) n And constructing a candidate ATPG library model set by corresponding candidate ATPG library models with the same logic of the logic information to be processed.
S4, based on A corresponding to each candidate ATPG library model m Selecting the candidate ATPG library model with the maximum total weight from the candidate ATPG library model set as B n And (4) corresponding to-be-processed ATPG library models.
It should be noted that, based on the ATPG basic cell library, a plurality of AND-Bs may be generated n The candidate ATPG library models with the same logic of the corresponding logic information to be processed are based on the A corresponding to each candidate ATPG library model m The candidate ATPG library model with the maximum total weight, namely the model which is most beneficial to the ATPG process, is selected from the weighted values of the ATPG library as a combinational logic standard unit.
Step S5, based on B n Corresponding to-be-processed ATPG library model and/or B n Corresponding timing information is generated for each B n Corresponding target ATPG library models.
It should be noted that the standard cell may be a combinational logic cell or a sequential logic cell, if B n If it is a combinational logic standard cell, then directly connect B n The corresponding ATPG library model to be processed is determined as B n Corresponding target ATPG library model if B n If it is a sequential logic standard cell, B is also required n Corresponding to-be-processed ATPG library model and B n Corresponding time sequence information is combined to generate B n Corresponding target ATPG library models.
The traditional ATPG library model generation method is based on Verilog generation of a standard unit, if test related information needs to be extracted, the test related information needs to be extracted from a first liberty file, and the information is annotated into an ATPG model, and the method needs to be realized in two steps n And when corresponding logic information to be processed is obtained, the related information of the test is directly extracted, so that the generation efficiency of the ATPG library model is further improved.
As an embodiment, the test related information may specifically be scan chain related information, specifically, if B n Including a register with a scan function, the step S2 further includes:
and S21, extracting scan chain access information and scan chain control information from the first liberty file.
The step S5 includes:
step S51, based on the scan chain access information, the B n Corresponding target ATPG library modelThe data input end and the scanning enabling end are marked in the corresponding ATPG library model for realizing the automatic insertion of the subsequent scanning chain.
More specifically, in order to effectively support automatic insertion and generation of a test circuit, a register bank unit with a scan function needs to be provided in a liberty file of a standard cell library, and relevant information is passed through a test _ cell structure. The following is illustrated by a specific example:
in the above example, the register bank unit explicitly defines how to access the bank unit into the scan chain, specifically, pin 'SI' is used as a data terminal to access into the scan chain, and pin 'SE' is used to control data input of the scan chain. This information needs to be extracted from the first liberty file and then inserted into the ATPG library model to ensure that the scan chain-taking tool at the back end can correctly identify and utilize these register library cells to correctly insert the scan chains required for testing into the circuit.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing three-state logic, a pull-up resistor and a pull-down resistor; wherein the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit comprises a multi-input AND-NOR gate (AOI), an exclusive-OR gate (XOR), an exclusive-OR gate (XNOR), a selector (MUX) and the like; the basic sequential logic ATPG basic cell comprises a Latch (Latch) and a register (Flip-flop). Based on ATPG basic unit library, for a given standard unit, the ATPG library model can be simplified as much as possible. The ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the efficiency of the result of the ATPG are ensured.
As an example, each ATPG basic cell is generated based on Verilog language description, such as a 4-input and nor gate:
as another two-input MUX:
it is to be understood that the above lists only a portion of the ATPG base cells, and is not so limited.
ATPG basic units are generated based on Verilog language description so that each B n The corresponding target ATPG library model is a model based on Verilog language. And subsequent verification of the ATPG library model is facilitated. Specifically, the first liberty file further includes B n A corresponding Verilog model, further comprising after step S5:
step S6, mixing B n Corresponding target ATPG library model and B n Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, judging B n And adding the corresponding target ATPG library model into a preset target ATPG library model library.
It should be noted that, since the target ATPG library model is a model based on Verilog language, it can directly interact with B n The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the test efficiency of the target ATPG library model is improved, and B n The corresponding Verilog model is also directly available from the pre-set process design information. The predetermined calibration tool can be specifically an industry standardThe form of (1) verifying the tool.
Through steps S1 to S6, an ATPG library model corresponding to each standard cell in a standard cell library to be processed may be generated, and on this basis, an ATPG model of a chip design to be tested may be generated based on a gate-level netlist of the chip design to be tested, as an embodiment, the step S6 further includes:
s7, obtaining a design gate-level netlist of the chip to be tested, wherein the design gate-level netlist to be tested is based on the standard cell library { B ] to be processed 1 ，B 2 ，…B N And (4) generating.
And S8, replacing each standard unit in the design gate-level netlist of the chip to be tested with a corresponding target ATPG library model in a preset target ATPG library model library to generate an ATPG model corresponding to the design gate-level netlist of the chip to be tested.
It should be noted that after the ATPG model corresponding to the designed gate-level netlist of the chip to be tested is generated, a test vector can be generated by an ATPG tool based on the ATPG model, and the chip to be tested is tested.
The ATPG base cell library is flexibly configurable according to specific application requirements, and as an embodiment, when the processor executes the computer program, the following steps are further implemented:
and S9, updating the ATPG basic unit library, wherein the updating comprises adding, deleting or modifying the ATPG basic unit.
And S10, acquiring a standard cell library corresponding to the updated ATPG basic cell to reconstruct the standard cell library to be processed, and acquiring a corresponding ATPG library model again through the steps S1-S5.
The system in the first embodiment can directly extract the logic information corresponding to the standard unit from the liberty file, and generate the ATPG library model corresponding to each standard unit based on the logic information and the preset ATPG basic unit library without paying attention to the Verilog model corresponding to the standard unit, thereby simplifying the generation process of the ATPG library model and improving the generation efficiency and quality of the ATPG library model.
Example II,
The second embodiment provides a combined logic standard cellThe ATPG library model generation system comprises a pre-constructed ATPG basic unit library { A 1 ，A 2 ，…A M }, memory and processor storing computer programs, A m The value of M is 1 to M, M is the total number of ATPG basic units in the ATPG basic unit library, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Composition structure of (A2) m Is A m Logical information of (A3) m Is A m Weight value of (A) m Weight value of and A m Inversely proportional to the cost of ATPG, the more easily ATPG can handle the higher the weight of the basic unit. When the processor executes the computer program, as shown in fig. 2, the following steps are implemented:
step C1, acquiring a to-be-processed combinational logic standard unit set { D } 1 ，D 2 ，…D P } and a second liberty file, D p The value range of P is 1 to P for the P-th to-be-processed combinational logic standard cell, P is the total number of the to-be-processed combinational logic standard cells, and D 1 ，D 2 ，…D P Belonging to the same standard cell library to be processed, wherein each D is stored in the second liberty file p Corresponding boolean functions or truth tables.
Step C2, taking the total weight value of the ATPG library model as a logic optimization target based on { A } 1 ，A 2 ，…A M Couple D p Performing logic optimization on corresponding Boolean function or truth table to generate f (p) groups of at least one A m Is generated by combining the constituent structures of (1) with (D) p Set of logically identical candidate ATPG library models of logical information { E } 1 p ,E 2 p ,…E f(p) p },E x p Is the x-th candidate ATPG library model, the value range of x is 1 to f (p), E x p Consists of g (xp) ATPG basic units.
It should be noted that the truth table may be converted into a boolean function and then logic optimization may be performed. The algorithm of logic synthesis is used for finding the optimal ATPG library model. The ATPG algorithm is sensitive to the number of basic cells of ATPG in the chip gate-level netlist, and the goal of optimization is usually to find an equivalent ATPG library model with the fewest basic library cells. However, it can be understood that if other factors need to be considered in the application scenario, other factors may also be set, but the weight corresponding to the number of the basic library units is set to be the highest.
Step C3, obtaining each E x p Total weight value G of x p ：
Wherein, the first and the second end of the pipe are connected with each other,
and the weight value is the weight value corresponding to the ith ATPG basic unit in the xth candidate ATPG library model.
Step C4, will { E 1 p ,E 2 p ,…E f(p) p E with the largest total weight value x p Is determined as D p Corresponding target ATPG library models.
It should be noted that, based on the ATPG basic cell library, a plurality of AND-Ds may be generated p The candidate ATPG library models with the same logic of the corresponding logic information to be processed are based on A corresponding to each candidate ATPG library model m The candidate ATPG library model with the maximum total weight, namely the model which is most beneficial to the ATPG process, is selected as D p Corresponding target ATPG library models.
As an example, the step C1 includes:
and step C11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein the first liberty file stores logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed.
The first liberty file is a file including standard cell timing information and logic information, and both the first liberty file and the standard cell library can be directly obtained from preset Process Design information (PDK), which is not described herein again.
Step C12, extracting a combined logic standard unit set { D) only comprising logic information from the standard unit library to be processed and the first liberty file 1 ，D 2 ，…D P A } and a second liberty file.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing three-state logic, a pull-up resistor and a pull-down resistor; wherein the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit comprises a multi-input AND-NOR gate, an exclusive-OR gate (XOR), an exclusive-OR gate (XNOR) and a selector (MUX); the basic sequential logic ATPG basic cell comprises latches (Latch) and registers (Flip-flop). Based on ATPG basic unit library, for a given standard unit, the ATPG library model can be simplified as much as possible. The ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the efficiency of the result of the ATPG are ensured.
As an example, each ATPG base cell is generated based on Verilog language description, such that each B n The corresponding target ATPG library model is a model based on Verilog language. The subsequent verification of the ATPG library model is facilitated, and specifically, the second liberty file further comprises D p A corresponding Verilog model, said step C4 further comprising, after:
step C5, adding D p Corresponding target ATPG library model and D p Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, judging D p And adding the corresponding target ATPG library model into a preset target ATPG library model library.
It should be noted that, since the target ATPG library model is based on Verilog language, it can directly connect with D p The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the method improves the quality of the Verilog modelTest efficiency of target ATPG library model, D p The corresponding Verilog model is also directly available from the pre-set process design information. The predetermined calibration tool may be a calibration tool in a standard form in the industry.
The process is not only suitable for the combinational logic standard unit, but also can be applied to the construction process of the target ATPG library model of the sequential logic standard unit after the sequential information is extracted. As an embodiment, when the processor executes the computer program, the following steps are also implemented:
and step C10, acquiring a time sequence logic standard unit set to be processed and a third liberty file, and extracting a state table corresponding to each time sequence logic standard unit from the third liberty file.
And step C20, acquiring corresponding time sequence information and logic information from a state table corresponding to each time sequence logic standard unit to be processed, wherein the logic information is a truth table or a Boolean function.
And step C30, generating a target ATPG library model corresponding to the logic information through the steps C2-C4 based on the logic information corresponding to the time sequence logic standard unit to be processed.
And C40, combining the target ATPG library model corresponding to the logic information with the time sequence information to generate a target ATPG library model corresponding to each time sequence logic standard unit to be processed.
As an embodiment, the to-be-processed sequential logic standard unit is an integrated clock gating standard unit, and the technical details for specifically constructing the target ATPG library model corresponding to the integrated clock gating standard unit are specifically described in embodiment three, and are not described herein again.
As an embodiment, the to-be-processed sequential logic standard unit is a synchronizer standard unit, and the technical details for specifically constructing the target ATPG library model corresponding to the synchronizer standard unit are specifically described in embodiment four, and are not described herein again.
In the system in the second embodiment, the candidate ATPG library model set of each combinational logic standard unit is obtained by performing logic optimization on each combinational logic standard unit, and the target ATPG library model is selected from the candidate ATPG library model set based on the weight value set for each standard unit, so that the generation process of the ATPG library models of the combinational logic standard units is simplified, and the generation efficiency of the ATPG library models of the combinational logic standard units is improved.
Example III,
An Integrated Clock Gating (ICG) standard cell integrated ATPG library model generation system comprises a pre-constructed ATPG basic cell library { A } 1 ，A 2 ，…A M }, memories and processors storing computer programs, A m The value range of M is 1 to M for the mth ATPG basic unit in the ATPG basic unit library, and M is the total number of the ATPG basic units in the ATPG basic unit library. When the processor executes the computer program, as shown in fig. 3, the following steps are implemented:
step D1, acquiring a to-be-processed integrated clock gating standard unit set { F 1 ，F 2 ，…F R And a third liberty file, F r The value range of R is 1 to R for the R-th integrated clock gating standard unit to be processed, R is the total number of the integrated clock gating standard units to be processed, and F 1 ，F 2 ，…F R Belonging to the same standard cell library to be processed.
Step D2, extracting each F from the third liberty file r Corresponding state table, F r The corresponding state table comprises a plurality of first state records, each first state record comprises h (r) input fields and an output field, each h (r) input field comprises a first enabling input field and h (r) -1 data input fields, each first enabling input field is used for storing a first state or a second state, each h (r) -1 data input field and each output field are used for storing corresponding level states, each level state comprises a first level state and a second level state, when the first enabling input field is in the first state, the output field is determined based on the logic relation of the h (r) -1 data input fields, and when the first enabling input field is in the second state, the output field keeps the current state unchanged.
Step D3, from step F r Extracting F from corresponding state table r Corresponding timing information and first logic information, and from F r The output of the middle acquisition state table is connected to F r F of the output r Corresponding second logical information.
It should be noted that, the first logic information is more complex than the second logic information, and taking the state table shown in fig. 4 as an example, the first logic information extracted is IQ = (FE | TE), and the second logic information is usually simpler, for example, GCK = IQ = (FE | TE), GCK = |)! IQ + CK or GCK = IQ | CK, GCK being the final output of the integrated clock gating standard cell.
Step D4, from { A } 1 ，A 2 ，…A M Select at least one A m Combining Generation with F r A first target ATPG library model with the same logic as the corresponding first logic information, and F r The corresponding second target ATPG library models with the same logic of the second logic information;
step D5, setting F r Corresponding memory cell, said F r The corresponding memory unit comprises an effective signal port, a data input port and an output port based on F r Corresponding timing information connects a clock signal to the valid signal port, the first target ATPG library model to a data input port, the second target ATPG library model to an output port, and F is generated r Corresponding target ATPG library models.
As an embodiment, the step D3 comprises:
step D31, adding F r Deleting the record of which the first enabling input field is in the second state in the corresponding state table, and deleting the column of the first enabling input field to obtain F r Corresponding truth table.
Step D32 based on F r The corresponding truth table obtains the first logic information.
Wherein, F can be specifically r The corresponding truth table is converted into a boolean function as the first logic information.
As an example, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Composition structure of (A2) m Is A m Logical information of (A3) m Is A m Weight value of (A) m Weight value of and A m Inversely proportional to the cost of ATPG, the D4 comprises:
step D41, taking the total weight value of the ATPG library model as a logic optimization target based on { A 1 ，A 2 ，…A M F pair r Performing logic optimization on the corresponding first logic information to generate k (r) pieces of at least one A m Is generated by combining with F r Corresponding candidate ATPG library models with the same first logic information logic form a candidate ATPG library model set { Ey 1 r ,Ey 2 r ,…Ey k(r) r },Ey z r For the z-th candidate ATPG library model, the value range of z is 1 to k (r), ey z r Consists of V (r) ATPG basic units.
It should be noted that the algorithm of logic synthesis is used to find the optimal ATPG library model. The ATPG algorithm is sensitive to the number of basic cells of ATPG in the chip gate-level netlist, and the goal of optimization is usually to find an equivalent ATPG library model with the fewest basic library cells. However, it can be understood that if other factors need to be considered in the application scenario, other factors may also be set, but the weight corresponding to the number of the basic library units is set to be the highest.
Step D42, obtaining each Ey z r Total weight value G of z r ：
Wherein the content of the first and second substances,
the weighted value corresponding to the ith ATPG basic unit in the nth candidate ATPG base model.
Step D43, will { Ey 1 r ,Ey 2 r ,…Ey k(r) r The total weight value in (1) } is the largestEy of z r Is determined as F r A corresponding first target ATPG library model.
It should be noted that, based on the ATPG basic unit library, a plurality of AND Fs may be generated r The candidate ATPG library models with the same logic of the logic information to be processed corresponding to the corresponding first logic information are based on A corresponding to each candidate ATPG library model m The candidate ATPG library model with the maximum total weight, namely the model which is most beneficial to the ATPG process, is selected as F r A corresponding first target ATPG library model.
As an embodiment, the D4 comprises:
step D41', from { A 1 ，A 2 ，…A M Acquisition with F r Corresponding second logic information logic identical A m As the second target ATPG library model.
Note that, since F r The corresponding second logical information is usually relatively simple and can therefore be derived directly from { A } 1 ，A 2 ，…A M Acquisition with F r Corresponding second logic information logic identical A m As the second target ATPG library model, no further screening step needs to be performed.
As an example, the step D1 includes:
and D11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein the first liberty file stores logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed.
The first liberty file is a file including standard cell timing information and logic information, and both the first liberty file and the standard cell library can be directly obtained from preset Process Design information (PDK), which is not described herein again.
Step D12, traversing the standard units in the standard unit library to be processed, determining the standard unit with the 'clock _ gate _ clock _ pin' item with at least one pin set as 'true' as the integrated clock gating standard unit to be processed, and generating the integrated clock gating standard unitSet of standard cells { F 1 ，F 2 ，…F R And acquiring a third liberty file from the first liberty file.
It should be noted that "clock _ gate _ clock _ pin" is an attribute item of a pin, and when set to "true", it indicates that the corresponding standard cell is an integrated clock gating standard cell.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing three-state logic, a pull-up resistor and a pull-down resistor; wherein the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit comprises a multi-input AND-NOR gate, an exclusive-OR gate (XOR), an exclusive-OR gate (XNOR) and a selector (MUX); the basic sequential logic ATPG basic cell comprises a Latch (Latch) and a register (Flip-flop). Based on ATPG basic unit library, for a given standard unit, the ATPG library model can be simplified as much as possible. The ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the efficiency of the result of the ATPG are ensured.
As an example, each ATPG base cell is generated based on Verilog language description, such that each B n The corresponding target ATPG library model is a model based on Verilog language. Facilitating subsequent verification of the ATPG library model, specifically, the second liberty file further includes D p A corresponding Verilog model, said step D5 further comprising:
step D6, adding F r Corresponding target ATPG library models and F r Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, F r And adding the corresponding target ATPG library model into a preset target ATPG library model library.
It should be noted that, since the target ATPG library model is a model based on Verilog language, it can directly interact with F r The corresponding Verilog model is verified through a preset verification toolAnd other conversion is not needed, so that the test efficiency of the target ATPG library model is improved, F r The corresponding Verilog model is also directly available from the pre-set process design information. The predetermined calibration tool may be a calibration tool in the form of an industry standard.
As an example, if F r An integrated clock-gated standard cell constructed as a latch, then F r The first state and the second state in the corresponding state table are the first level state or the second level state, and the storage unit corresponding to the step D5 is a latch.
Specifically, the first level state is a high level state, and the second level state is a low level state, or the first level state is a low level state, and the second level state is a high level state.
As an embodiment, if the second electrical state is a high state, the step D5 further includes: an inverter is inserted at the active signal port of the memory cell.
FIG. 4 shows a state table of an integrated clock gating standard cell, where "CK" is the enable input field, "FE" is the first data input field, "TE" is the second data input field, and "IQ" is the output field. "L" indicates a first state and a first level state, specifically, a low level. H represents a second state and a second level state, specifically, a high level. "N" indicates that the field remains unchanged, "-" indicates that the corresponding field is ignored, i.e., no state has any effect on the result.
As an example, if F r An integrated clock-gated standard cell formed as a register, then F r The corresponding first and second states are first and second edge triggered states.
Specifically, the first edge trigger state is a rising edge, and the second edge trigger state is a falling edge, or the first edge trigger state is a falling edge, and the second edge trigger state is a rising edge.
As an embodiment, if the second electrical state is a rising edge, the step D5 further includes: an inverter is inserted at the active signal port of the memory cell.
The system of the third embodiment generates the ATPG library model for the logic information based on the ATPG base unit library by extracting the time sequence information and the logic information in the state table of the integrated clock gating standard unit and then generates the ATPG library model of the integrated clock gating standard unit by combining the ATPG base unit model with the clock information, thereby simplifying the generation process of the ATPG library model of the integrated clock gating standard unit and improving the generation efficiency of the ATPG library model of the integrated clock gating standard unit.
Example four,
The fourth embodiment provides an ATPG library model generation system of synchronizer standard cells, which comprises a pre-constructed ATPG basic cell library { A } 1 ，A 2 ，…A M }, memories and processors storing computer programs, A m And when the processor executes the computer program, the value range of M is 1 to M, and M is the total number of ATPG basic units in the ATPG basic unit library. As shown in fig. 5, the following steps are implemented:
step E1, obtaining a synchronizer standard unit set { K ] to be processed 1 ,K 2 ,…K S } and a fourth liberty file, K s The standard unit of the synchronizer to be processed is the S-th standard unit of the synchronizer to be processed, the value range of S is 1 to S, S is the total number of the standard units of the synchronizer to be processed, K 1 ,K 2 ,…K S Belonging to the same standard cell library to be processed.
Step E2, extracting each K from the fourth liberty file s Corresponding state table, K s The corresponding state table comprises a plurality of second state records, wherein each second state record comprises L(s) input fields and T(s) output fields, and the L(s) input fields comprise a second enabling input field, a selection signal field and L(s) -2 data input fields; the second enable input field is used for storing a first edge trigger state and a second edge trigger state, the selection signal field, the other L(s) -2 data input fields and the T(s) output fields are used for storing corresponding level states, and the level states comprise a first levelA state and a second level state; when the second enable input field is in the first edge trigger state, the T(s) output fields are determined based on the logical relationship of the selection signal field and the L(s) -2 data input fields; when the second enable input field is in a second edge trigger state, keeping the current state of the T(s) output fields unchanged; the jth output field corresponds to K s Output state of the jth register, K s T(s) registers are included.
As shown in fig. 6, in the state table of a standard unit of a synchronizer, in this example, there are two registers, and the corresponding output fields are "IQ1" and "IQ2", respectively; "CLK" denotes a second enable input field, "se" denotes a select signal field, "d" denotes a first data input field of the synchronizer standard cell, and "si" denotes a second data input field of the synchronizer standard cell. "R" represents a first state, "-R" represents a second state, "L" represents a first level state, specifically a low level, "H" represents a second level state, specifically a high level. "N" indicates to remain unchanged, "H/L" indicates to be the first level state or the second level state, "-" indicates that the corresponding field is ignored, i.e., any state does not affect the result.
Step E3, from K s Extracting K from corresponding state table s Corresponding timing information, third logic information, and a register sequence (RE) in which T(s) registers are arranged in a connection order 1 ，RE 2 ，…RE T(s) ),RE u Is K s The value of u is 1 to T(s).
Still in the example shown in fig. 6, the register corresponding to "IQ1" is arranged before the register corresponding to "IQ2", i.e. the output terminal of the register corresponding to "IQ1" is connected to the input terminal of the register corresponding to "IQ 2".
Step E4, from { A 1 ，A 2 ，…A M Selecting at least one A m Combining generation with K s And the corresponding third logic information is the same as the third target ATPG library model in logic.
Step E5, setting K s Each RE in u Corresponding register unit RF u Each RF u Including valid signal port, data input port and output port, RF u Is connected to the RF u+1 The third target ATPG library model is connected to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u Valid signal port of, generating K s Corresponding target ATPG library models.
As an example, the step E1 includes:
and E11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein the first liberty file stores logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed.
The first liberty file is a file including standard cell timing information and logic information, and both the first liberty file and the standard cell library can be directly obtained from preset Process Design information (PDK), which is not described herein again.
Step E12, traversing the standard cells in the standard cell library to be processed, determining the time sequence standard cell comprising more than two registers as the synchronizer standard cell to be processed, and generating the synchronizer standard cell set { K ] to be processed 1 ,K 2 ,…K S And acquiring a fourth liberty file from the first liberty file.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing three-state logic, a pull-up resistor and a pull-down resistor; wherein the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit comprises a multi-input AND-NOR gate, an exclusive-OR gate (XOR), an exclusive-OR gate (XNOR) and a selector (MUX); the basic sequential logic ATPG basic cell comprises a Latch (Latch) and a register (Flip-flop). Based on ATPG basic unit library, for a given standard unit, the ATPG library model can be simplified as much as possible. The ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the efficiency of the result of the ATPG are ensured.
As an example, each ATPG base cell is generated based on Verilog language description, such that each B n The corresponding target ATPG library model is a model based on Verilog language. The subsequent verification of the ATPG library model is facilitated, and specifically, the second liberty file further comprises D p A corresponding Verilog model, said step E5 being followed by:
step E6, adding K s Corresponding target ATPG library model and K s Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, K s And adding the corresponding target ATPG library model into a preset target ATPG library model library.
It should be noted that, since the target ATPG library model is a model based on Verilog language, it can directly interact with K s The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the test efficiency of the target ATPG library model is improved, and K is s The corresponding Verilog model is also directly available from the pre-set process design information. The predetermined calibration tool may be a calibration tool in the form of an industry standard.
As an example, the step E3 includes:
step E31, adding K s Deleting the record of which the second enabling input field is in the second edge trigger state in the corresponding state table, deleting the column of the second enabling input field to obtain K s Corresponding truth table.
Step E32, based on K s And acquiring the third logic information by the corresponding truth table.
Wherein, K can be s The corresponding truth table is converted into a boolean function as the first logic information.
As an example, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Composition structure of (A2) m Is A m Logical information of (A3) m Is A m Weight value of A m Weight value of and A m Inversely proportional to the cost of ATPG, the more readily ATPG can handle the higher the weight of the base unit, and E4 comprises:
step E41, taking the total weight value of the ATPG library model as a logic optimization target based on { A 1 ，A 2 ，…A M To K s Performing logic optimization on the corresponding third logic information to generate I(s) of at least one A m Is generated by combining the composition structure of (1) with K s The corresponding candidate ATPG library model set { Ec) with the same logic of the third logic information 1 s ,Ec 2 s ,…Ec I(s) s },Ec w s Is the w-th candidate ATPG library model, and the value range of w is 1 to I(s), ec w s Consists of J(s) ATPG basic units.
It should be noted that the algorithm of logic synthesis is used to find the optimal ATPG library model. The ATPG algorithm is sensitive to the number of basic cells of ATPG in the gate-level netlist of the chip, and the goal of optimization is usually to find an equivalent ATPG library model with the fewest basic library cells. However, it can be understood that if other factors need to be considered in the application scenario, other factors may also be set, but the weight corresponding to the number of the basic library units is set to be the highest.
Step E42, obtaining each Ec w s Total weight value G of w s ：
Wherein the content of the first and second substances,
the weighted value corresponding to the ith ATPG basic unit in the w candidate ATPG base model.
Step E43, mixing { Ec 1 s ,Ec 2 s ,…Ec I(s) s Total in }Ec with the largest weight value w s Is determined as K s A corresponding third target ATPG library model.
It should be noted that multiple AND Ks may be generated based on the ATPG basic cell library s The candidate ATPG library models with the same logic of the logic information to be processed corresponding to the corresponding first logic information are based on A corresponding to each candidate ATPG library model m The candidate ATPG library model with the maximum total weight, namely the model which is most beneficial to the ATPG process, is selected as K s A corresponding third target ATPG library model.
In an embodiment, the first edge triggered state is a rising edge and the second edge triggered state is a falling edge, or the first edge triggered state is a falling edge and the second edge triggered state is a rising edge.
As an embodiment, if the second electrical state is a rising edge, the step E5 further includes inserting an inverter into the active signal port of each register.
The system of the fourth embodiment generates the ATPG library model of the standard unit of the synchronizer by extracting the time sequence information, the logic information and the connection relation between the registers in the state table of the standard unit of the synchronizer, generating the ATPG library model for the logic information based on the ATPG basic unit library, and combining the ATPG library model with the connection relation between the clock information and the registers, thereby simplifying the generation process of the ATPG library model of the standard unit of the synchronizer and improving the generation efficiency of the ATPG library model of the standard unit of the synchronizer.
Examples V,
The standard cells in the design gate-level netlist, the connection relation among the standard cells and the input and output values generated by the standard cells based on the ATPG model are directly shown aiming at the common direct display in the prior art. However, the occupied area of some standard cells is large, the composition details in the standard cells cannot be directly displayed, readability is poor, if the composition detail information needs to be acquired, corresponding standard cells need to be clicked one by one to present the composition details, the occupied area of the expanded standard cells is further increased, and therefore debugging efficiency is low, and user experience is poor.
An embodiment five provides a data processing system for generating a standard cell target display structure, comprising a standard cell library { B } to be processed 1 ，B 2 ，…B N }, a first liberty file, a memory and a processor storing a computer program, B n The standard cell library is the nth standard cell in the standard cell library to be processed, the value range of N is 1 to N, and each B is stored in the first liberty file n Corresponding logic information and timing information. When the processor executes the computer program, as shown in fig. 7, the following steps are implemented:
step F1, based on B n The corresponding logic information and timing information obtain the corresponding boolean function Q (n).
Step F2, inverting Q (n) to obtain! And Q (n).
Step F3, respectively adding Q (n) and! Q (n) is logically optimized to generate candidate functions Q1 (n) in the form Of Sum Of products SOP (Sum Of Product) corresponding to Q (n), candidate functions Q2 (n) in the form Of Sum Of products POS (Product Of Sum) corresponding to Q (n), and | are! Candidate function in the form of the sum of products Q (n)! Q3 (n),! Q (n) corresponding to a candidate function in the form of the sum product POS! And Q4 (n).
SOP represents the sum of products, i.e., in the form of min terms, and POS represents the product of sums, i.e., in the form of max terms. Existing generation of Q (n) and! The implementation of candidate functions in the form of SOPs and POS for Q (n) are all within the scope of the present invention.
Step F4, from Q1 (n), Q2 (n),! Q3 (n) and! Selecting the simplest candidate function from Q4 (n) as the target function corresponding to Q (n);
and F5, generating a target display structure corresponding to the Q (n) based on the target function corresponding to the Q (n), wherein the target display structure comprises an input port, an output port, a composition module and a connection relation between the composition modules.
Step F4 is achieved by two example ways as follows:
the first embodiment,
The step F4 includes:
step F41, if Q1 (n), Q2 (n),! Q3 (n) and! And Q4 (n) has a candidate function with the minimum variable number, and the candidate function with the minimum variable number is determined as the target function corresponding to Q (n), wherein WX and! WX is regarded as a variable, WX represents any variable, and if there are a plurality of candidate functions with the smallest number of variables, step F42 is performed.
And F42, if the candidate functions with the minimum number of variables have one candidate function with the minimum number of gates, determining the candidate function with the minimum number of gates as the target function corresponding to Q (n), wherein each bracket in the candidate functions corresponds to one gate, and if the candidate functions with the minimum number of gates exist, executing the step F43.
And step F43, determining the candidate function with the least number of inversions in the candidate functions with the least number of gates as the target function corresponding to Q (n).
Wherein the step F43 includes:
step F431, if there is one candidate function with the minimum number of negations among the plurality of candidate functions with the minimum number of gates, determining the candidate function with the minimum number of negations as the target function corresponding to Q (n), and if there are a plurality of candidate functions with the minimum number of negations, randomly selecting one candidate function with the minimum number of negations as the target function corresponding to Q (n).
The target display structure corresponding to Q (n) is obtained based on the constraint condition optimization, so that the displayed schematic diagram can be conveniently understood and analyzed, the readability of a user is improved, and the debugging efficiency is improved.
The second embodiment,
The step F4 includes:
step F41 ’ Set variable quantity weight We 1 Gate number weight We 2 And the inverse number weight We 3 ,We 1 、We 2 、We 3 Satisfy We 1 >We 2 >We 3 ，We 1 -We 2 >WZ 1 ,We 2 -We 3 >WZ 2 ,WZ 1 >WZ 2 ，WZ 1 Is a first step difference threshold, WZ 2 Is the second step difference threshold.
Step F42 ’ Obtaining SX d Number of medium variables a d Number of doors b d And the number of negations c d ，SX d Is { Q1 (n), Q2 (n)! Q3 (n) and! Q4 (n), and d ranges from 1 to 4, wherein the preset constraint is satisfied: WX and! WX is regarded as a variable, and WX represents any variable; one for each bracket.
Step F43', obtaining SX d Corresponding total weight SY d :
SY d ＝We 3 *a d +We 2 *b d +We 3 *c d ；
Step F44' of mixing SY d Maximum SX d And determining an objective function corresponding to Q (n).
The target display structure corresponding to Q (n) is obtained by optimizing based on the constraint conditions, so that the displayed schematic diagram is convenient to understand and analyze, the readability of a user is improved, and the debugging efficiency is improved.
As an embodiment, the system further includes a display interface, and after step F5, the method further includes:
f6, obtaining a design gate-level netlist of the chip to be tested, wherein the design gate-level netlist to be tested is based on the standard cell library { B ] to be processed 1 ，B 2 ，…B N And (4) generating.
And F7, replacing each standard unit in the design gate-level netlist of the chip to be tested with a corresponding target display structure based on the target display structure, and displaying on the display interface.
It can be understood that the structure displayed in step F7 is directly a structure in which the standard cell is replaced with a corresponding target display structure, and what is displayed is a structure with correct logic and optimal display, and the specific composition of the designed gate-level netlist of the whole chip to be tested can be visually presented without extra click, which is convenient for debugging.
As an embodiment, the system further includes an ATPG model corresponding to a pre-generated gate-level netlist of the chip design to be tested, and step F7 further includes:
and F71, generating an input parameter value and an output parameter value corresponding to each target display structure based on the ATPG model corresponding to the to-be-tested chip design gate-level netlist, and displaying an input end and an output end corresponding to each target display structure on the interface.
The debugging efficiency is further improved by visually displaying the output input parameter value and the output parameter value.
Fig. 8 shows a display interface (a part above an arrow) from an original design gate-level netlist of a chip to be tested to a display interface (a part below the arrow) based on a target display structure, and it can be seen from the figure that the display interface based on the target display structure enables the size of the same unit to be obviously reduced, and the detailed components and the connection relationship of each component unit are clearly shown.
It should be noted that the specific generation details of the ATPG model corresponding to the gate-level netlist of the chip design to be tested may be implemented by any one of the technical details of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment, and are not described herein again.
It will be appreciated that some of the technical details of the above-described embodiments are equally applicable to other embodiments and will not be fully described.
The system in the fifth embodiment can perform logic optimization on each standard cell to generate a corresponding target display structure, so that when a gate-level netlist is displayed, the target display structure corresponding to each standard cell is directly displayed, the specific composition structure of the gate-level netlist can be clearly displayed, the readability is high, the display area of the gate-level netlist of the chip design can be reduced, the debugging by a user is facilitated, and the debugging efficiency is improved.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. An ATPG library model generation system of synchronizer standard cells is characterized in that,
comprises a pre-constructed ATPG basic unit library { A 1 ，A 2 ，…A M }, memories and processors storing computer programs, A m When the processor executes the computer program, the following steps are implemented:
step E1, acquiring a synchronizer standard unit set { K ] to be processed 1 ,K 2 ,…K S } and a fourth liberty file, K s The standard unit of the synchronizer to be processed is the S-th standard unit of the synchronizer to be processed, the value range of S is 1 to S, S is the total number of the standard units of the synchronizer to be processed, K 1 ,K 2 ,…K S Belong to the same standard cell library to be processed;
step E2, extracting each K from the fourth liberty file s Corresponding state table, K s The corresponding state table comprises a plurality of second state records, wherein each second state record comprises L(s) input fields and T(s) output fields, and the L(s) input fields comprise a second enabling input field, a selection signal field and L(s) -2 data input fields; the second enable input field is used for storing a first edge trigger state and a second edge trigger state, the selection signal field,The other L(s) -2 data input fields and the T(s) output fields are used for storing corresponding level states, and the level states comprise a first level state and a second level state; when the second enable input field is in the first edge trigger state, the T(s) output fields are determined based on the logical relationship of the selection signal field and the L(s) -2 data input fields; when the second enable input field is in a second edge trigger state, keeping the current state of the T(s) output fields unchanged; the jth output field corresponds to K s Output state of the jth register, K s T(s) registers are included;
step E3, from K s Extracting K from corresponding state table s Corresponding timing information, third logic information, and a register sequence (RE) in which T(s) registers are arranged in a connection order 1 ，RE 2 ，…RE T(s) ),RE u Is K s The value range of u is 1 to T(s);
step E4, from { A 1 ，A 2 ，…A M Selecting at least one A m Combining generation with K s A third target ATPG library model with the same logic of the corresponding third logic information;
step E5, setting K s Each RE in u Corresponding register unit RF u Each RF u Including valid signal port, data input port and output port, RF u Is connected to the RF u+1 The third target ATPG library model is connected to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u Valid signal port of, generating K s Corresponding target ATPG library models.
2. The system of claim 1,
the step E1 comprises the following steps:
step E11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein the first liberty file stores logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed;
step E12, traversing the standard units in the standard unit library to be processed, determining the time sequence standard unit comprising more than two registers as the standard unit of the synchronizer to be processed, and generating the standard unit set { K } of the synchronizer to be processed 1 ,K 2 ,…K S And acquiring a fourth liberty file from the first liberty file.
3. The system of claim 1,
the step E3 comprises the following steps:
step E31, adding K s Deleting the record of which the second enabling input field is in the second edge trigger state in the corresponding state table, deleting the column of the second enabling input field to obtain K s A corresponding truth table;
step E32, based on K s And acquiring the third logic information by the corresponding truth table.
4. The system of claim 1,
A m ＝(A1 m ,A2 m ,A3 m ),A1 m is A m Composition structure of (1), A2 m Is A m Logical information of (A3) m Is A m Weight value of A m Weight value of and A m Inversely proportional to the cost of ATPG, the E4 comprises:
e41, taking the total weight value of the ATPG library model as a logic optimization target based on { A } 1 ，A 2 ，…A M Is to K s Performing logic optimization on the corresponding third logic information to generate I(s) of at least one A m Is generated by combining the constituent structures of (1) with K s The corresponding candidate ATPG library model set { Ec) with the same logic of the third logic information 1 s ,Ec 2 s ,…Ec I(s) s },Ec w s Is the w-th candidate ATPG library model, and the value range of w is 1 to I(s), ec w s Consists of J(s) ATPG basic sheetsMeta-composition;
step E42, obtaining each Ec w s Total weight value G of w s ：
Wherein, the first and the second end of the pipe are connected with each other,
the weighted value corresponding to the ith ATPG basic unit in the w candidate ATPG library model;
step E43, mixing { Ec 1 s ,Ec 2 s ,…Ec I(s) s Ec with the largest total weight value w s Is determined as K s A corresponding third target ATPG library model.
5. The system of claim 1,
the first edge trigger state is a rising edge and the second edge trigger state is a falling edge, or the first edge trigger state is a falling edge and the second edge trigger state is a rising edge.
6. The system of claim 1,
if the second electrical state is a rising edge, step E5 further includes inserting an inverter at the active signal port of each register.
7. The system of claim 1,
the ATPG basic unit library comprises basic logic ATPG basic units, combinational logic ATPG basic units, basic sequential logic ATPG basic units and ATPG basic units for processing three-state logic, pull-up resistors and pull-down resistors; the basic logic ATPG basic unit comprises a buffer, an inverter, an AND gate, an OR gate, a NAND gate and a NOR gate; the combinational logic ATPG basic unit comprises a multi-input exclusive-OR gate, an exclusive-OR gate and a selector; the basic sequential logic ATPG basic unit comprises a latch and a register.
8. The system of claim 1,
each ATPG basic unit is generated based on Verilog language description, and each B n The corresponding target ATPG library model is a model based on Verilog language.
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