CN109596958A - Sensor unit, fingerprint sensor and electronic equipment - Google Patents
Sensor unit, fingerprint sensor and electronic equipment Download PDFInfo
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- CN109596958A CN109596958A CN201710909129.8A CN201710909129A CN109596958A CN 109596958 A CN109596958 A CN 109596958A CN 201710909129 A CN201710909129 A CN 201710909129A CN 109596958 A CN109596958 A CN 109596958A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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- Image Input (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Abstract
The present invention provides a kind of sensor unit, fingerprint sensor and electronic equipment, which includes: fingerprint sensing electrode, fingerprint sensing circuit and memory addressing circuit.Wherein, fingerprint sensing circuit includes reference voltage input terminal, differential amplifier circuit and first switch, and memory addressing circuit includes shift register gating circuit and multiple bit line units arranged side by side.Wherein, the shift register gating circuit carries out shifting processing according to the addressing signal, mode switching signal and the second default clock signal, generates multiple word-line signals, and the word-line signal is exported to the bit line unit.According to mode switching signal, the addressing circuit and differential amplifier circuit being multiplexed in fingerprint sensing circuit, the memory addressing circuit for arranging in pairs or groups again newly-increased will need the SRAM circuit being independently arranged to be arranged in sensor array, so that the size reduction of fingerprint sensor in the prior art.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically to a kind of sensor unit, fingerprint sensor with
And electronic equipment.
Background technique
With the continuous development of science and technology, requirement of the user to security performance is also higher and higher, and bio-identification is by its biology
The exclusive property of feature has obtained quick development.
Wherein, a Main Branches of the fingerprint recognition as bio-identification, currently, fingerprint recognition is passed by fingerprint recognition
Sense chip is realized, as shown in Figure 1, the fingerprint recognition sensing chip 10 includes sensor array 100 and peripheral circuit, it is described outer
Enclose circuit include analog front circuit 120 (hereinafter referred to as: AFE circuitry), analog to digital conversion circuit 130 (hereinafter referred to as: ADC electricity
Road), addressing circuit 210 (hereinafter referred to as: XY Decoder), digital control circuit 220 (hereinafter referred to as: Digital
Control), MCU circuit 230 and static storage circuit 300 (hereinafter referred to as: SRAM circuit), wherein sensor array 100
Including the multiple sensor units 110 being arranged in array.And module of the SRAM circuit as an independent design, it include addressing electricity
The components such as road and amplifier.Therefore, the area of the fingerprint recognition sensing chip 10 after combination is larger, does not meet current semiconductor device
Part tends to the development trend of miniaturization.
To sum up, how a kind of sensor unit, fingerprint sensor and electronic equipment are provided, fingerprint sensing can be reduced
The size of chip is that those skilled in the art wish persistently improve one big technical problem.
Summary of the invention
In view of this, the present invention provides a kind of sensor unit, fingerprint sensor and electronic equipment, it being capable of basis
Mode switching signal, the addressing circuit and differential amplifier circuit being multiplexed in fingerprint sensing circuit, then newly-increased memory of arranging in pairs or groups are fixed
Location circuit will need the SRAM circuit being independently arranged to be arranged in sensor array in the prior art, so that fingerprint sensor
Size reduction.
To achieve the above object, the invention provides the following technical scheme:
A kind of sensor unit is applied to fingerprint recognition sensing chip, comprising: fingerprint sensing electrode, fingerprint sensing circuit
And memory addressing circuit；
The fingerprint sensing circuit includes reference voltage input terminal, differential amplifier circuit and first switch；
The first input end of the differential amplifier circuit connects the fingerprint sensing electrode, and inputs with the reference voltage
End connection, and the first input end as the fingerprint sensing circuit, the second input terminal of the differential amplifier circuit with it is described
Reference voltage input terminal connection, and the second input terminal as the fingerprint sensing circuit, the first of the differential amplifier circuit
First output end of the output end as the fingerprint sensing circuit, the second output terminal of the differential amplifier circuit is as the finger
The second output terminal of line sensing circuit；
The first switch is according to addressing signal, mode switching signal and the first preset signals control received
The starting of differential amplifier circuit；
The memory addressing circuit includes at least one bit line unit and shift register gating circuit, the bit line
Unit is connected in parallel between the first input end and the second input terminal of the fingerprint sensing circuit, and the position of the bit line unit
It chooses signal input part to be connected to the shift register gating circuit, the shift register gating circuit is according to described fixed
Location signal, mode switching signal and the second default clock signal carry out shifting processing, generate multiple word-line signals, and will be described
Word-line signal chooses signal as the position of the bit line unit；
The mode switching signal is for controlling in fingerprint sensing circuit described in the memory addressing circuit time-sharing multiplex
Differential amplifier circuit.
Optionally, further includes: the first logic circuit, the second logic circuit and third logic circuit,
First logic circuit is used to control the first input end and the first output end and difference of differential amplifier circuit
Second input terminal of amplifying circuit and the conducting of second output terminal；First logic circuit has first input end, second defeated
Enter end, the first output end, second output terminal, third output end and the 4th output end, the first input end and connects described first
Preset signals, second input terminate the mode switching signal, first output end and the differential amplifier circuit
First input end connection, the second output terminal are connected to the first output end of the differential amplifier circuit, the third output
End is connected to the second input terminal of the differential amplifier circuit, and the second of the 4th output end and the differential amplifier circuit is defeated
Outlet connection；
Second logic circuit is used to control the starting of differential amplifier circuit；Second logic circuit is defeated with first
Entering end, the second input terminal, third input terminal and output end, the first input end connects first preset signals, and described
Two inputs terminate the mode switching signals, and the third input terminates the addressing signal, and the output end is as described the
The control terminal of one switch；
The third logic circuit is used to control the starting of shift register gating circuit；The third logic circuit has
First input end, the second input terminal and output end, the first input end connect the addressing signal, the second input termination
The mode switching signal, the output end are connected to the reset signal end of the shift register gating circuit.
Optionally, first logic circuit include first with door, first switch tube and second switch, described first
First preset signals are terminated with an input of door, and described first, which terminates described pattern switching with another input of door, believes
Number, described first with the output end of the door first end with the first end of the first switch tube and the second switch respectively
Connection, first output end of the second end of the first switch tube as first logic circuit, the first switch tube
Second output terminal of the third end as first logic circuit, the second end of the second switch is as first logic
The third output end of circuit, fourth output end of the third end of the second switch as first logic circuit；
Second logic circuit include second with door and the first NAND gate, first NAND gate one termination described in
First preset signals, another termination mode switching signal of first NAND gate, the output end of first NAND gate
It is connected to described second with an input terminal of door, described second terminates the addressing signal with another input of door, and described the
Two output ends with the output end of door as second logic circuit；
The third logic circuit includes third and door, a termination addressing signal of the third and door, the other end
Connect the mode switching signal, output end of the output end as the third logic circuit.
Optionally, the reference voltage input terminal includes the first reference voltage input terminal and the second reference voltage input terminal,
First reference voltage input terminal is connected to the first input end of the differential amplifier circuit, the second reference voltage input
End is connected to the second input terminal of the differential amplifier circuit.
Optionally, further include reference voltage input circuit, the reference voltage input circuit include third switching tube and
5th switching tube；
The input terminal of the third switching tube is as first reference voltage input terminal, for receiving first with reference to electricity
Pressure, the output end of the third switching tube are connected to the first input end of the differential amplifier circuit；
The input terminal of 5th switching tube is as second reference voltage input terminal, for receiving second with reference to electricity
Pressure, the output end of the 5th switching tube are connected to the second input terminal of the differential amplifier circuit；
The control of the control terminal of the third switching tube and the 5th switching tube terminates first preset signals.
Optionally, the reference voltage input circuit further includes the 4th switching tube and the 6th switching tube；
It is first defeated to be connected to the output end of the third switching tube and the differential amplifier circuit for 4th switching tube
Enter between end；
It is second defeated to be connected to the output end of the 5th switching tube and the differential amplifier circuit for 6th switching tube
Enter between end；
The control terminal of 4th switching tube and the default clock letter of control termination described second of the 6th switching tube
Number.
Optionally, first preset signals are dead level signal.
Optionally, first preset signals and the described second default clock signal inverting clock signal each other.
A kind of fingerprint sensor, comprising:
Sensor array, the sensor array include the above-mentioned sensor unit of any one that is arranged in array.
A kind of electronic equipment, including above-mentioned fingerprint sensor.
Compared with prior art, the technical scheme provided by the invention has the following advantages:
The present invention provides a kind of sensor unit, fingerprint sensor and electronic equipment, which includes:
Fingerprint sensing electrode, fingerprint sensing circuit and memory addressing circuit.Wherein, fingerprint sensing circuit includes reference voltage input
End, differential amplifier circuit and first switch, memory addressing circuit include shift register gating circuit and it is multiple side by side
Bit line unit.Wherein, the shift register gating circuit is pre- according to the addressing signal, mode switching signal and second
If clock signal carries out shifting processing, multiple word-line signals are generated, and the word-line signal is exported to the bit line unit.Root
According to mode switching signal, the addressing circuit and differential amplifier circuit being multiplexed in fingerprint sensing circuit, then newly-increased memory of arranging in pairs or groups
Addressing circuit will need the SRAM circuit being independently arranged to be arranged in sensor array, so that fingerprint sensor in the prior art
Size reduction.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the circuit module figure of fingerprint recognition sensing chip in the prior art；
Fig. 2 is the circuit module figure of the common SRAM circuit of fingerprint recognition sensing chip in the prior art；
Fig. 3 is a kind of circuit structure diagram of sensor unit provided in an embodiment of the present invention；
Fig. 4 is the displacement schematic diagram that a kind of clock signal provided in an embodiment of the present invention is converted into word-line signal；
Fig. 5 is the circuit theory of shift register gating circuit in a kind of sensor unit provided in an embodiment of the present invention
Figure；
Fig. 6 is a kind of signal transmission end schematic diagram of sensor unit provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
In conjunction with background technique it is found that the structure of existing fingerprint recognition sensing chip is as shown in Figure 1, the fingerprint recognition senses
Chip 10 includes sensor array 100 and peripheral circuit, and the peripheral circuit includes AFE circuitry 120, adc circuit 130, determines
Location circuit 210, digital control circuit 220, MCU circuit 230 and SRAM circuit 300, wherein sensor array 100 includes being in
Multiple sensor units 110 of array arrangement, the sensing electrode of the multiple sensor unit 110 are in fingerprint recognition sensing core
The surface of piece 10.
In the prior art, SRAM circuit 300 is the mould group of an independent design, as shown in Fig. 2, including bit line unit array
Bit-Cell Array 310, wordline decoder X-Decoder 320, bit line decoder Y-Decoder 330 and sensing are put
Big device Sense Amplifier 340.
Since the system level of fingerprint recognition requires, the occupancy width of sensor unit 110 in fingerprint recognition sensing chip
Usually 50um, therefore, in addition to fingerprint sensing circuit, sensor unit 110 also has redundant space, and therefore, this programme will show
There is the SRAM circuit 300 of technology to be disassembled, be dissolved into sensor unit 110, and then reduces entire fingerprint recognition and sense core
The area occupied of piece.
Specifically, as shown in figure 3, being applied to fingerprint recognition the embodiment of the invention provides a kind of sensor unit 110 '
Sensing chip, the sensor unit 110 ' include: fingerprint sensing electrode 60, fingerprint sensing circuit 61 and memory addressing electricity
Road 62.
Wherein, the fingerprint sensing circuit 61 includes reference voltage input terminal (input terminal of VR1 and VR2 in figure), poor
Point amplifying circuit 20 and first switch 13, in the present embodiment, reference voltage input terminal include the first reference voltage input terminal and
Second reference voltage input terminal, wherein the first reference voltage input terminal and the second reference voltage input terminal can receive first respectively
Reference voltage VR1 and the second reference voltage VR2.It should be noted that in the present embodiment, the first reference voltage VR1 can be with
The voltage value of second reference voltage VR2 is identical, then at this point, reference voltage input terminal can be a reference voltage input terminal, i.e.,
First reference voltage input terminal and the second reference voltage input terminal are the same end.
Except this, it is preferred that in the present embodiment, the first reference voltage input terminal can divide with the second reference voltage input terminal
Not Jie Shou voltage value different the first reference voltage VR1 and the second reference voltage VR2, in favor of the sensing of fingerprint.Specifically, institute
It states the first reference voltage input terminal to be connected to the first input end of the differential amplifier circuit, second reference voltage input terminal
With the second input terminal of the differential amplifier circuit be connected to.
The first input end (at 11 in figure) of the differential amplifier circuit 20 connects the fingerprint sensing electrode 60, and with institute
Stating the connection of the first reference voltage input terminal, (wherein, connection indicates the of the first reference voltage input terminal and differential amplifier circuit 20
Electric signal transmission is able to carry out between one input terminal, but, the first reference voltage input terminal not necessarily with the differential amplifier circuit 20
First input end be connected directly), and the first input end as the fingerprint sensing circuit 61, the differential amplifier circuit 20
The second input terminal (at 12 in figure) be connected to second reference voltage input terminal, and as the fingerprint sensing circuit 61
Second input terminal, the first output end (at 21 in figure, i.e. OUT1) of the differential amplifier circuit 20 is as the fingerprint sensing electricity
The second output terminal (at 22 in figure, i.e. OUT2) of first output end on road 61, the differential amplifier circuit 20 is used as the fingerprint
The second output terminal of sensing circuit 61.
The first switch 13 is according to the addressing signal XY, mode switching signal M and the first preset signals received
CK1 controls the starting of differential amplifier circuit.Specifically, predetermined current Is flows into differential amplification electricity when first switch 13 is connected
Road 20, at this point, differential amplifier circuit 20 is in operating mode.When first switch 13 disconnects, predetermined current Is cannot flow into difference
Divide amplifying circuit 20, at this point, differential amplifier circuit 20 is in power-off not operating mode.
The memory addressing circuit 62 includes at least one bit line unit 30 and shift register gating circuit 40.
The bit line unit 30 is connected in parallel on the first input end (at 11 in figure) and second of the fingerprint sensing circuit 63
Between input terminal (at 12 in figure), and the position of the bit line unit 30 is chosen signal input part and is selected with the shift register
Circuit passband 40 is connected to, and the shift register gating circuit 40 is according to the addressing signal XY, mode switching signal M and second
Default clock signal CK2 carries out shifting processing, generate multiple word-line signals [WL (1), WL (2) ..., WL (N-1) and WL
(N)], and by the word-line signal [WL (1), WL (2) ..., WL (N-1) and WL (N)] as the bit line unit 30
Signal is chosen in position, is written and read to select bit line unit 30 by word-line signal WL.
Specifically, it is assumed that square-wave waveform in the waveform diagram such as figure of the second default clock signal CK2, then,
Multiple word-line signals that shift register gating circuit 40 generates are successively to produce high level as timing carries out shifting processing
Raw multiple word-line signal WL (1), WL (2) ..., WL (N-1) and WL (N).
The mode switching signal M is for controlling fingerprint sensing circuit described in 62 time-sharing multiplex of memory addressing circuit
Differential amplifier circuit 20 in 61 will need the amplifying circuit being separately provided to save, and will show in SRAM circuit 300 in the prior art
There is the Bit-CellArray of SRAM circuit 300 in technology that the excess room of sensor unit is set, so that fingerprint sensor
Size reduction.
Specifically, the addressing principle of sensor unit 110 ' provided in this embodiment is as follows:
When setting addressing signal XY=0, sensing unit 110 ' is without addressing.At this point, shift register gating circuit 40
The signal of reset signal end input be 0, therefore shift register gating circuit 40 does not work, and, first switch 13 disconnects, and makes
Obtaining predetermined current Is cannot flow into difference amplifier 20, i.e., at this point, difference amplifier 20 is in power-off not operating mode.
As addressing signal XY=1, sensing unit 110 ' enters addressing state, due to sensor list provided in this embodiment
Sensing unit addressing and storage addressing in member are therefore the same addressing circuit of multiplexing in addressing signal XY=1, needs
The value of further control mode switch signal M, to guarantee fingerprint sensing and storage addressing timesharing movement.
Specifically, in the present embodiment, when setting mode switching signal M=0, which is fingerprint sensing mould
Formula, at this point, addressing signal XY=1, therefore, first switch 13 are connected, differential amplifier circuit 20 due to mode switching signal M=0
It is in running order.Meanwhile shift register gating circuit 40 does not work.At this point, when fingerprint sensing electrode 60 has finger close
Or when touching, the voltage signal of the first input end of differential amplifier circuit 20 and the input of the second input terminal is with respect to reference voltage
VR1 and reference voltage VR2 can be changed, and after the amplification of differential amplifier circuit 20, the first of output to fingerprint sensing circuit 61 is defeated
Outlet and second output terminal, so that subsequent conditioning circuit carries out fingerprint recognition, to differentiate whether current finger print can pass through safety
Certification.
When setting mode switching signal M=1, which is storage addressing mode.It should be noted that storage is fixed
Location mode is divided into read mode and write mode again, needs to distinguish by the first preset signals CK1 at this time.The present embodiment
In, the first preset signals CK1 is set as static dead level signal.For example, when the first preset signals CK1=0 of setting, to read
Modulus formula is write mode when setting the first preset signals CK1=1.
So, when sensor unit is in read mode, addressing signal XY=1, mode switching signal M=1, and, the
One preset signals CK1=0, at this point, first switch 13 is connected, differential amplifier circuit 20 is in running order.Meanwhile shift LD
There is input signal on device gating circuit 40, therefore, shift register gating circuit 40 is also at working condition.At this point, displacement is posted
Storage gating circuit 40 carries out shifting processing according to the second default clock signal CK2, generates the wordline for characterizing selected bit line unit
Then signal after the amplification of differential amplifier circuit 20, is exported to the first output end of fingerprint sensing circuit 61 and second and is exported
End, so that subsequent conditioning circuit is identified, determines the location information of current selected bit line unit 30, realizes the reading of data.
Similarly, when sensor unit is in write-in addressing mode, addressing signal XY=1, mode switching signal M=1,
And the first preset signals CK1=1, at this point, first switch 13 disconnects, differential amplifier circuit 20 is in power-off off position.And
At this point, there is input signal on shift register gating circuit 40, therefore, shift register gating circuit 40 is in running order.
At this point, external write-in signal counter can be poured into the first input end (at 11 in figure) and the second input terminal of fingerprint sensing circuit 61
(at 12 in figure), then shift register gating circuit 40 carries out shifting processing according to the second default clock signal CK2, generates table
The word-line signal for levying selected bit line unit 30, is realized to the selected of bit line unit 30, preset data are written.
It should be noted that preferably selecting a fingerprint sensing electrode 60 right in sensor unit provided in this embodiment
Answer the combination of multiple bit line units 30.Because, it is assumed that a fingerprint sensing electrode 60 correspondences, one bit line unit 30, that
The memory capacity of entire sensor unit will very little therefore in the present embodiment, preferably set each fingerprint sensing electrode 60
Corresponding multiple bit line units 30, for example, can be with are as follows: a fingerprint sensing electrode 60 corresponding 8 or 16 bit line units 30.
In summary, the storage addressing in the present embodiment is by first determining one or more fingerprint sensing electrodes 60, so
Afterwards again by shift register gating circuit 40 to multiple bit line units 30 corresponding with the fingerprint sensing electrode 60 carry out by
One addressing.
On the basis of the above embodiments, the present embodiment additionally provides a kind of specific structure circuit of fingerprint sensing unit,
In conjunction with Fig. 3, i.e., increase the first logic circuit 31, the second logic circuit 32 and third logic electricity on above-mentioned fingerprint sensing unit
Road 33.
Wherein, first logic circuit 31 be used to control first input end and the first output end of differential amplifier circuit with
And differential amplifier circuit the second input terminal and second output terminal conducting.First logic circuit 31 has the first input
End, the second input terminal, the first output end, second output terminal, third output end and the 4th output end, the first input end connect
The first preset signals CK1, second input terminate the mode switching signal M, first output end 70 with it is described
The first input end (at 11 in figure) of differential amplifier circuit is connected to, and the first of the second output terminal and the differential amplifier circuit
Output end 21 is connected to, and the third output end is connected to the second input terminal (at 12 in figure) of the differential amplifier circuit, described
4th output end is connected to the second output terminal 22 of the differential amplifier circuit.
Specifically, as shown in figure 3, first logic circuit 31 includes first and door, first switch tube 51 and second
Switching tube 52, described first with an input of door termination the first preset signals CK1, described first with door another is defeated
Enter to terminate the mode switching signal M, described first with the output end 70 of the door first end with the first switch tube 51 respectively
And the first end connection of the second switch 52, the second end of the first switch tube 51 is as first logic circuit
31 the first output end, second output terminal of the third end of the first switch tube as first logic circuit 31 are described
Third output end of the second end of second switch 52 as first logic circuit 31, the third of the second switch 52
Hold the 4th output end as first logic circuit 31.
Second logic circuit 32 is used to control the starting of differential amplifier circuit.Second logic circuit 32 has the
One input terminal, the second input terminal, third input terminal and output end, the first input end meet the first preset signals CK1,
Second input terminates the mode switching signal M, and the third input terminates the addressing signal XY, and the output end is made
For the control terminal of the first switch 13.
Specifically, as shown in figure 3, second logic circuit 32 includes second and door and the first NAND gate, described the
One termination the first preset signals CK1 of one NAND gate, another termination mode switching signal of first NAND gate
M, the output end of first NAND gate are connected to described second with an input terminal of door, described second with another input of door
Terminate the addressing signal XY, the described second output end with the output end of door as second logic circuit 32.
The third logic circuit 33 is used to control the starting of shift register gating circuit.The third logic circuit 33
With first input end, the second input terminal and output end, the first input end meets the addressing signal XY, and described second is defeated
Entering to terminate the mode switching signal M, the output end is connected to the reset signal end of the shift register gating circuit 40,
For to shift register output reset signal.
Specifically, as shown in figure 3, the third logic circuit 33 includes third and door, a termination of the third and door
The addressing signal XY, another termination mode switching signal M, output of the output end as the third logic circuit 33
End.
It should be noted that the first logic circuit 31 provided in the present embodiment, the second logic circuit 32 and third are patrolled
Collect circuit 33 solely for the purpose of illustration, the present embodiment is not limited to the specific structure of foregoing circuit, as long as can have above-mentioned
The circuit function of embodiment.
Except this, the present embodiment additionally provides a kind of physical circuit of reference voltage input circuit, and in conjunction with Fig. 3, this is with reference to electricity
Pressing input circuit 34 includes third switching tube 53 and the 5th switching tube 55.
Wherein, the input terminal of the third switching tube 53 is as first reference voltage input terminal 61, for receiving the
One reference voltage VR1, the output end of the third switching tube 53 are connected to the first input end of the differential amplifier circuit 20.
The input terminal of 5th switching tube 55 is as second reference voltage input terminal 62, for receiving the second reference
Voltage VR2, the output end of the 5th switching tube 55 are connected to the second input terminal of the differential amplifier circuit 20.
Also, the control termination described first of the control terminal of the third switching tube 53 and the 5th switching tube 55 is pre-
If signal CK1.
Optionally, in order to further eliminate charge injection, the present embodiment on the basis of above-mentioned reference voltage input circuit,
Also add the 4th switching tube 54 and the 6th switching tube 56.
Wherein, the 4th switching tube 54 is connected to the output end and the differential amplifier circuit of the third switching tube 53
Between 20 first input end.
6th switching tube 56 is connected to the output end and the differential amplifier circuit 20 of the 5th switching tube 55
Between second input terminal.
And the control terminal of the 4th switching tube 54 and the control termination described second of the 6th switching tube 56 are default
Clock signal CK2.
In the present embodiment, the input terminal of the 4th switching tube 54 is connected to output end, and the input terminal of the 4th switching tube 54 connects
The output end of the third switching tube 53 is connect, the output end of the 4th switching tube 54 connects the first input of the differential amplifier circuit
End；The input terminal of 6th switching tube 56 is connected to output end, and the input terminal of the 6th switching tube 56 connects the defeated of the 5th switching tube 55
The output end of outlet, the 6th switching tube 56 connects the second input terminal of the differential amplifier circuit.
Except this, the present embodiment additionally provides a kind of specific implementation circuit of shift register gating circuit 40, such as Fig. 5 institute
Show, which includes multiple d type flip flops.
Wherein, multiple d type flip flop cascades, the end CK of multiple d type flip flops connect the described second default clock letter
Number CK2, the end R of multiple d type flip flops are connected to the output end of the third logic circuit 33, the d type flip flop it is defeated
Outlet is successively used as the output end of the shift register gating circuit 40.
In conjunction with above-mentioned particular circuit configurations, the working principle of sensor unit provided in this embodiment is illustrated:
Fingerprint sensing mode:
When not having sensor unit to be selected, addressing signal XY=0, the output end output 0 of third and door are then shifted at this time
Register gating circuit 40 does not work, the word-line signal WL that all output ends of shift register gating circuit 40 receive at this time
It is 0, and, the output end of the first logic circuit is 0, and first switch 13 disconnects, then at this point, bit line unit 30 and differential amplification electricity
Road 20 does not work.
When a certain sensor unit is chosen, addressing signal XY=1 at this time, it is assumed that system configuration mode switching signal M=0
When be fingerprint recognition mode.Under fingerprint sensing mode, it is mutual for setting the default clock signal CK2 of the first preset signals CK1 and second
For the clock signal of reverse phase.Third switching tube 53 and the 5th switching tube 55 are controlled by the first preset signals CK1.Pass through second
Default clock signal CK2 controls the switch state of the 4th switching tube 54 and the 6th switching tube 56.Due to the 4th switching tube 54 with
6th switching tube 56 constant conduction itself, and the second default clock signal CK2 and the first preset signals CK1 reverse phase, therefore can be with
Eliminate charge injection.
Due to addressing signal XY=1,40 output end WL of shift register gating circuit is 0, at this point, 30 nothing of bit line unit
Signal transmission.Simultaneously as mode switching signal M=0, therefore first is 0 with the output end 70 of door, so that first switch tube 51
And second switch 52 turns off.Again due to set the first preset signals CK1=1, mode switching signal M=0 so that first with
NOT gate output 1, and addressing signal XY=1, so that second exports 1 with door, and then the control terminal of first switch 13 receives closure
Signal has electric current Is to be flowed into differential amplifier circuit 20, makes the normal work of differential amplifier circuit 20 so that first switch 13 is connected
Make.
The present embodiment realizes control ginseng by the value of the setting default clock signal CK2 of the first preset signals CK1 and second
The input state for examining voltage VR1 and reference voltage VR2, when there is the capacitor as caused by fingerprint ridge paddy on fingerprint sensing electrode 60
When variation, the voltage signal of the first input end of differential amplifier circuit 20 and the input of the second input terminal can be changed, through difference
After amplifying circuit 20 amplifies, export to the first output end and second output terminal of fingerprint sensing circuit 63, for subsequent conditioning circuit
It is identified, determines the finger print information of current finger print.
Read mode:
When a certain sensor unit is chosen, addressing signal XY=1 at this time, it is assumed that system configuration mode switching signal M=1
When, to store addressing mode.It should be noted that storage addressing mode is divided into read mode and write mode again, need at this time
Value by setting the first preset signals CK1 distinguishes, and sets the first preset signals CK1 as static dead level signal.
For example, being read mode when the first preset signals CK1=0 of setting, when setting the first preset signals CK1=1, for addressing is written
Mode.
When sensor unit provided by the embodiment is in read mode, it is preferable that system is by reference voltage VR1 and ginseng
It examines voltage VR2 and is set as Floating state.First preset signals CK1 of default output is 0, at this point, third switching tube
53 and the 5th switching tube 55 turn off, further isolation because of reference voltage VR1 and reference voltage VR2 long range cabling and is in
The noise that may be brought under Floating state, also, due to CK1=0, M=1, so that the first NAND gate exports 1, and addressing
Signal XY=1, so that second exports 1 with door, and then the control terminal of first switch 13 receives Continuity signal, there is electric current Is inflow
To differential amplifier circuit 20, work normally differential amplifier circuit 20.
At this point, shift register gating circuit 40 carries out shifting processing according to the second default clock signal CK2, characterization is generated
For the word-line signal of selected bit line unit then after the amplification of differential amplifier circuit 20, the first of output to fingerprint sensing circuit 61 is defeated
Outlet and second output terminal determine the content information of current selected bit line unit 30 so that subsequent conditioning circuit is identified, realize
The readings of data.
Wherein, the second default clock signal CK2 can make shift register gating circuit 40 generate 100---000,
010---000,001---000, ----, 000---100,000---010, the output signal WL of 000---001, for bit line unit
30 receive.
Write mode:
When sensor unit is in write mode, addressing signal XY=1, mode switching signal M=1, and, first is default
Signal CK1=1.
CK1=1, M=1, so that the first NAND gate output 0, so that second exports 0, and then the control of first switch 13 with door
System termination receives shutdown signal, and first switch 13 is closed, and electric current Is is isolated with differential amplifier circuit 20, makes differential amplifier circuit 20
It does not work.Simultaneously as CK1=1, M=1, the first and door output are 1, so that first switch tube 51 and second switch 52
Closure, at this point, the first output end 21 and second output terminal 22 of differential amplifier circuit 20 can be poured into difference by peripheral circuit is counter
The first input end of amplifying circuit 20 and the second input terminal, carry out the write-in of data.
At this point, external write-in signal counter can be poured into the first input end (at 11 in figure) and the of fingerprint sensing circuit 61
Two input terminals (at 12 in figure), then shift register gating circuit 40 generates characterization choosing according to the second default clock signal CK2
The word-line signal of position line unit 30 is realized to the selected of bit line unit 30, preset data are written.
Further, sensor unit provided in this embodiment, inventor is it is considered that carrying out the reading of SRAM and writing
Fashionable, in order to avoid increasing signal lead, the multiplexing scheme in the present embodiment uses original signal wire as far as possible.It needs to illustrate
, the read mode and write mode of SRAM sets addressing signal XY and mode switching signal M is 1, unlike,
It is different that the first preset signals CK1 is received under both of which.Then at this time:
M=0 is fingerprint sensing mode (Sensing Mode)；
M=1, CK1=0 are SRAM read mode (SRAM Mode, Read)；
M=1, CK1=1 are that SRAM write enters mode (SRAM Mode, Write).It is poor as the first preset signals CK1=1
The first input end of amplifying circuit 20 is divided directly to be connected to the first reference voltage VR1, the second input terminal of differential amplifier circuit 20
It is directly connected to the second reference voltage VR2, therefore, the present embodiment exists the first reference voltage VR1 and the second reference voltage VR2
SRAM read and write mode under, suspension joint current potential (or: in Floating state) is set as, so that the first reference voltage
VR1 and the second reference voltage VR2 do not interfere with the input terminal of difference amplifier 20.
To sum up, the sensor unit that the present embodiment proposes, fingerprint sensing operation and the operation timesharing of memory addressing carry out,
Avoid the noise jamming that memory addressing operation operates fingerprint sensing；Relatively and in the memory addressing of the prior art, word
The case where line signal bracing wire is too long, influences SRAM reading speed, the present embodiment is also equivalent to have carried out effective cutting to bracing wire, helps
Reduce the read access time of SRAM.
Except this, the present embodiment additionally provides a kind of schematic diagram of the signal transmission end of sensor unit, as shown in fig. 6, packet
It includes:
First reference voltage signal transmission end (in Fig. 6 VR1 indicate), the second reference voltage signal transmission end (VR2 in Fig. 6
Mark), the first preset signals transmission end (in Fig. 6 CK1 indicate), the second default clock signal transmission end (CK2 is indicated in Fig. 6) with
And mode switching signal transmission end (M is indicated in Fig. 6), the first output signal transmission end (OUT1 is indicated in Fig. 6), the second output letter
Number transmission end (OUT2 is indicated in Fig. 6), predetermined current signal transmission end (Is is indicated in Fig. 6), two addressing signal transmission end (figures
X, Y are indicated in 6).
Wherein, the first reference voltage signal transmission end is connected to first reference voltage input terminal, for receiving
The first reference voltage VR1 that outside provides.
The second reference voltage signal transmission end is connected to second reference voltage input terminal, is mentioned for receiving outside
The the second reference voltage VR2 supplied.
The first preset signals transmission end is used to receive the first preset signals CK1 of external offer.
The second default clock signal transmission end is used to receive the second default clock signal CK2 of external offer.
The mode switching signal transmission end is used to receive the mode switching signal M of system sending.
First output signal transmission end connects the first output end OUT1 of the sensor unit.
Second output signal transmission end connects the second output terminal OUT2 of the sensor unit.
Predetermined current signal transmission end is connected to the input terminal of the first switch 13, receives the external electric current Is provided.
The addressing signal transmission end that X is indicated in Fig. 6 transmits an input subsignal of the addressing signal XY.
The addressing signal transmission end that Y is indicated in Fig. 6 transmits the another input subsignal of the addressing signal XY.
It should be noted that in the present embodiment, the biography of the signal transmission end of the sensor unit compared to the prior art
The signal transmission end of sensor cell only increases a mode switching signal transmission end (end M in Fig. 6).
The present embodiment additionally provides a kind of fingerprint sensor, and the fingerprint sensor includes sensor array, described
Sensor array includes in the sensor unit 110 of two-dimensional array arrangement, and the sensor unit 110 includes fingerprint sensing electricity
Pole, fingerprint sensing circuit and memory addressing circuit, the memory addressing circuit are connected to the fingerprint sensing electrode, are used
In the determining position by touch fingerprint sensing electrode.
The fingerprint sensor further comprises addressing circuit, AFE circuitry, analog circuit and digital circuit.
It include an addressing circuit 210 (XY Decoder) in existing fingerprint recognition sensing chip incorporated by reference to Fig. 1, it should
Addressing circuit is only used for realizing the addressing to finger sensing arrays, while also including specific addressing circuit in SRAM circuit 300.
The present embodiment is then the addressing circuit for being multiplexed finger sensing arrays in the prior art, so that the addressing circuit is realizing fingerprint sensing
The memory addressing circuit for arranging in pairs or groups again newly-increased while addressing realizes memory addressing again.
On the basis of the above embodiments, the present embodiment additionally provides a kind of electronic equipment, including above-mentioned fingerprint sensing
Chip, circuit operation principle refer to above-described embodiment.
In conclusion the present invention provides a kind of sensor unit, fingerprint sensor and electronic equipment, the sensor
Unit includes: fingerprint sensing electrode, fingerprint sensing circuit and memory addressing circuit.Wherein, fingerprint sensing circuit includes ginseng
Examine voltage input end, differential amplifier circuit and first switch, memory addressing circuit include shift register gating circuit with
And multiple bit line units arranged side by side.Wherein, shift register gating circuit according to the addressing signal, mode switching signal and
Second default clock signal carries out shifting processing, generates multiple word-line signals, and the word-line signal is exported to the bit line
Unit.According to mode switching signal, the addressing circuit and differential amplifier circuit being multiplexed in fingerprint sensing circuit, then arrange in pairs or groups newly-increased
Memory addressing circuit will need the SRAM circuit being independently arranged to be arranged in sensor array in the prior art, so that fingerprint passes
The size reduction of sense chip.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.To the upper of the disclosed embodiments
It states bright, enables those skilled in the art to implement or use the present invention.Various modifications to these embodiments are to ability
Will be apparent for the professional technician in domain, the general principles defined herein can not depart from it is of the invention
In the case where spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. a kind of sensor unit, which is characterized in that be applied to fingerprint recognition sensing chip, comprising: fingerprint sensing electrode, fingerprint
Sensing circuit and memory addressing circuit；
The fingerprint sensing circuit includes reference voltage input terminal, differential amplifier circuit and first switch；
The first input end of the differential amplifier circuit connects the fingerprint sensing electrode, and connects with the reference voltage input terminal
It is logical, and the first input end as the fingerprint sensing circuit, the second input terminal of the differential amplifier circuit and the reference
Voltage input end connection, and the second input terminal as the fingerprint sensing circuit, the first output of the differential amplifier circuit
The first output end as the fingerprint sensing circuit is held, the second output terminal of the differential amplifier circuit is as the fingerprint sense
The second output terminal of slowdown monitoring circuit；
The first switch controls the difference according to the addressing signal, mode switching signal and the first preset signals received
The starting of amplifying circuit；
The memory addressing circuit includes at least one bit line unit and shift register gating circuit, the bit line unit
It is connected in parallel between the first input end and the second input terminal of the fingerprint sensing circuit, and the position of the bit line unit is chosen
Signal input part is connected to the shift register gating circuit, and the shift register gating circuit is believed according to the addressing
Number, mode switching signal and the second default clock signal carry out shifting processing, generate multiple word-line signals, and by the wordline
Signal chooses signal as the position of the bit line unit；
The mode switching signal is used to control the difference in fingerprint sensing circuit described in the memory addressing circuit time-sharing multiplex
Divide amplifying circuit.
2. sensor unit according to claim 1, which is characterized in that further include: the first logic circuit, the second logic electricity
Road and third logic circuit,
First logic circuit is used to control the first input end and the first output end and differential amplification of differential amplifier circuit
Second input terminal of circuit and the conducting of second output terminal；First logic circuit have first input end, the second input terminal,
First output end, second output terminal, third output end and the 4th output end, the first input end connect the described first default letter
Number, second input terminates the mode switching signal, and the first of first output end and the differential amplifier circuit is defeated
Enter end connection, the second output terminal is connected to the first output end of the differential amplifier circuit, the third output end and institute
State the second input terminal connection of differential amplifier circuit, the second output terminal company of the 4th output end and the differential amplifier circuit
It is logical；
Second logic circuit is used to control the starting of differential amplifier circuit；Second logic circuit has the first input
End, the second input terminal, third input terminal and output end, the first input end connect first preset signals, and described second
Input terminates the mode switching signal, and the third input terminates the addressing signal, and the output end is as described first
The control terminal of switch；
The third logic circuit is used to control the starting of shift register gating circuit；The third logic circuit has first
Input terminal, the second input terminal and output end, the first input end connect the addressing signal, and described second inputs described in termination
Mode switching signal, the output end are connected to the reset signal end of the shift register gating circuit.
3. sensor unit according to claim 2, which is characterized in that
First logic circuit includes first and door, first switch tube and second switch, described first with one of door
Input terminates first preset signals, and described first terminates described mode switching signal with another input of door, and described the
One is connected to the first end of the first end of the first switch tube and the second switch respectively with the output end of door, described
First output end of the second end of first switch tube as first logic circuit, the third end conduct of the first switch tube
The second output terminal of first logic circuit, third of the second end of the second switch as first logic circuit
Output end, fourth output end of the third end of the second switch as first logic circuit；
Second logic circuit includes second and door and the first NAND gate, a termination described first of first NAND gate
Preset signals, another termination mode switching signal of first NAND gate, the output end of first NAND gate and institute
Second is stated to be connected to an input terminal of door, described second terminates the addressing signal with another input of door, described second with
Output end of the output end of door as second logic circuit；
The third logic circuit includes third and door, a termination addressing signal of the third and door, another termination institute
State mode switching signal, output end of the output end as the third logic circuit.
4. sensor unit according to claim 1, which is characterized in that the reference voltage input terminal includes the first reference
The first of voltage input end and the second reference voltage input terminal, first reference voltage input terminal and the differential amplifier circuit
Input terminal connection, second reference voltage input terminal are connected to the second input terminal of the differential amplifier circuit.
5. sensor unit according to claim 4, which is characterized in that further include reference voltage input circuit, the ginseng
Examining voltage input circuit includes third switching tube and the 5th switching tube；
The input terminal of the third switching tube is as first reference voltage input terminal, for receiving the first reference voltage, institute
The output end for stating third switching tube is connected to the first input end of the differential amplifier circuit；
The input terminal of 5th switching tube is as second reference voltage input terminal, for receiving the second reference voltage, institute
The output end for stating the 5th switching tube is connected to the second input terminal of the differential amplifier circuit；
The control of the control terminal of the third switching tube and the 5th switching tube terminates first preset signals.
6. sensor unit according to claim 5, which is characterized in that the reference voltage input circuit further includes the 4th
Switching tube and the 6th switching tube；
4th switching tube is connected to the output end of the third switching tube and the first input end of the differential amplifier circuit
Between；
6th switching tube is connected to the output end of the 5th switching tube and the second input terminal of the differential amplifier circuit
Between；
The control terminal of 4th switching tube and the control of the 6th switching tube terminate the second default clock signal.
7. sensor unit according to claim 1, which is characterized in that first preset signals are Static Electro ordinary mail
Number.
8. sensor unit according to claim 1, which is characterized in that first preset signals are default with described second
Clock signal inverting clock signal each other.
9. a kind of fingerprint sensor characterized by comprising
Sensor array, the sensor array include the biography as described in any one of claim 1-8 being arranged in array
Sensor cell.
10. a kind of electronic equipment, which is characterized in that including fingerprint sensor as claimed in claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710909129.8A CN109596958B (en) | 2017-09-29 | 2017-09-29 | Sensor unit, fingerprint sensing chip and electronic equipment |
| PCT/CN2018/108561 WO2019062889A1 (en) | 2017-09-29 | 2018-09-29 | Sensor unit, fingerprint sensing chip and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710909129.8A CN109596958B (en) | 2017-09-29 | 2017-09-29 | Sensor unit, fingerprint sensing chip and electronic equipment |
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| CN109596958A true CN109596958A (en) | 2019-04-09 |
| CN109596958B CN109596958B (en) | 2021-06-25 |
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| CN109596958B (en) | 2021-06-25 |
| WO2019062889A1 (en) | 2019-04-04 |
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