WO2019062889A1 - Sensor unit, fingerprint sensing chip and electronic device - Google Patents

Abstract

A sensor unit (110'), a fingerprint sensing chip (10) and an electronic device. The sensor unit (110') comprises: a fingerprint sensing electrode (60), a fingerprint sensing circuit (61) and a memory addressing circuit (62), wherein the fingerprint sensing circuit (61) comprises reference voltage input ends (VR1, VR2), a differential amplifier circuit (20) and a first switch (13), and the memory addressing circuit (62) comprises a shift register gating circuit (40) and a plurality of parallel bit line units (30). The shift register gating circuit (40) performs shift processing according to an addressing signal (XY), a mode switching signal (M) and a second pre-set clock signal (CK2), so as to generate a plurality of word line signals (WL(1), WL(2), …, WL(N)), and outputs the word line signals (WL(1), WL(2), …, WL(N)) to the bit line units (30). According to the mode switching signal (M), the addressing circuit and the differential amplifier circuit (20) in the fingerprint sensing circuit (61) are multiplexed and are then combined with a newly added memory addressing circuit (62), and an SRAM circuit (300) needing to be arranged independently in the prior art is arranged in a sensor array (100), such that the size of the fingerprint sensing chip (10) is reduced.

Description

Sensor unit, fingerprint sensor chip, and electronic device

This application claims the priority of the domestic application filed on September 29, 2017, the Chinese Patent Office, the application number is 201710909129.8, the invention name is "sensor unit, fingerprint sensor chip and electronic device", the entire contents of which are incorporated herein by reference. In the application.

Technical field

The present invention relates to the field of semiconductor technology, and more particularly to a sensor unit, a fingerprint sensor chip, and an electronic device.

Background technique

With the continuous development of technology, users have higher and higher requirements for safety performance. Biometrics has developed rapidly due to the uniqueness of its biological characteristics.

Among them, fingerprint recognition is a major branch of biometric identification. At present, fingerprint recognition is implemented by a fingerprint recognition sensor chip. As shown in FIG. 1 , the fingerprint recognition sensor chip 10 includes a sensor array 100 and peripheral circuits, and the peripheral circuit The analog front end circuit 120 (hereinafter referred to as AFE circuit), the analog to digital conversion circuit 130 (hereinafter referred to as ADC circuit), the address circuit 210 (hereinafter referred to as XY Decoder), the digital control circuit 220 (hereinafter referred to as: Digital control), and the MCU circuit 230 and a static storage circuit 300 (hereinafter referred to as SRAM circuit), wherein the sensor array 100 includes a plurality of sensor units 110 arranged in an array. The SRAM circuit is a separately designed module that includes components such as addressing circuits and amplifiers. Therefore, the combined fingerprint recognition sensor chip 10 has a large area, which does not conform to the trend that current semiconductor devices tend to be miniaturized.

In summary, how to provide a sensor unit, a fingerprint sensor chip, and an electronic device, which can reduce the size of the fingerprint sensor chip is a major technical problem that those skilled in the art hope to continuously improve.

Summary of the invention

In view of this, the present invention provides a sensor unit, a fingerprint sensing chip, and an electronic device, which can multiplex a positioning circuit and a differential amplifying circuit in a fingerprint sensing circuit according to a mode switching signal, and then cooperate with a newly added memory addressing circuit. The SRAM circuit that needs to be independently set in the prior art is disposed in the sensor array, so that the size of the fingerprint sensing chip is reduced.

To achieve the above object, the present invention provides the following technical solutions:

A sensor unit is applied to a fingerprint recognition sensor chip, comprising: a fingerprint sensing electrode, a fingerprint sensing circuit and a memory addressing circuit;

The fingerprint sensing circuit includes a reference voltage input terminal, a differential amplifying circuit, and a first switch;

a first input end of the differential amplifying circuit is connected to the fingerprint sensing electrode, and is connected to the reference voltage input end, and serves as a first input end of the fingerprint sensing circuit, and a second An input end is connected to the reference voltage input end, and as a second input end of the fingerprint sensing circuit, a first output end of the differential amplifying circuit is used as a first output end of the fingerprint sensing circuit, a second output end of the differential amplifying circuit serves as a second output end of the fingerprint sensing circuit;

The first switch controls activation of the differential amplifying circuit according to the received addressing signal, the mode switching signal, and the first preset signal;

The memory addressing circuit includes at least one bit line unit and a shift register gating circuit, the bit line unit being connected in parallel between the first input end and the second input end of the fingerprint sensing circuit, and the bit line The position selection signal input end of the unit is connected to the shift register strobe circuit, and the shift register strobe circuit performs shift processing according to the address signal, the mode switching signal and the second preset clock signal to generate a plurality of a word line signal, and using the word line signal as a position selection signal of the bit line unit;

The mode switching signal is used to control the memory addressing circuit to time-multiplex the differential amplifying circuit in the fingerprint sensing circuit.

Optionally, the method further includes: a first logic circuit, a second logic circuit, and a third logic circuit,

The first logic circuit is configured to control conduction between the first input end and the first output end of the differential amplifying circuit and the second input end and the second output end of the differential amplifying circuit; the first logic circuit has a first input end a second input end, a first output end, a second output end, a third output end, and a fourth output end, the first input end is connected to the first preset signal, and the second input end is connected to the a mode switching signal, the first output end is in communication with a first input end of the differential amplifying circuit, and the second output end is in communication with a first output end of the differential amplifying circuit, the third output end is a second input end of the differential amplifying circuit is in communication, and the fourth output end is in communication with a second output end of the differential amplifying circuit;

The second logic circuit is configured to control activation of the differential amplification circuit; the second logic circuit has a first input terminal, a second input terminal, a third input terminal, and an output terminal, and the first input terminal is connected to the first a preset signal, the second input terminal is connected to the mode switching signal, the third input terminal is connected to the address signal, and the output end is used as a control end of the first switch;

The third logic circuit is configured to control activation of a shift register gating circuit; the third logic circuit has a first input end, a second input end, and an output end, and the first input end is connected to the address signal, The second input terminal is coupled to the mode switching signal, and the output terminal is in communication with a reset signal terminal of the shift register gating circuit.

Optionally, the first logic circuit includes a first AND gate, a first switch tube, and a second switch tube, and an input terminal of the first AND gate is connected to the first preset signal, the first The other input terminal of the gate is connected to the mode switching signal, and the output end of the first AND gate is respectively connected to the first end of the first switch tube and the first end of the second switch tube, the first a second end of the first switching circuit is used as a first output end of the first logic circuit, a third end of the first switching circuit is used as a second output end of the first logic circuit, and the second switching tube is The second end serves as a third output end of the first logic circuit, and the third end of the second switch tube serves as a fourth output end of the first logic circuit;

The second logic circuit includes a second AND gate and a first NAND gate. One end of the first NAND gate is connected to the first preset signal, and the other end of the first NAND gate is connected to the mode. Switching a signal, the output of the first NAND gate is in communication with an input of the second AND gate, and the other input of the second AND gate is connected to the address signal, the second AND gate The output end serves as an output end of the second logic circuit;

The third logic circuit includes a third AND gate, one end of the third AND gate is connected to the address signal, the other end is connected to the mode switching signal, and the output end is used as an output end of the third logic circuit.

Optionally, the reference voltage input end includes a first reference voltage input end and a second reference voltage input end, and the first reference voltage input end is in communication with the first input end of the differential amplifying circuit, the second The reference voltage input is in communication with the second input of the differential amplifier circuit.

Optionally, the method further includes a reference voltage input circuit, where the reference voltage input circuit includes a third switch tube and a fifth switch tube;

The input end of the third switch tube serves as the first reference voltage input end for receiving a first reference voltage, and the output end of the third switch tube is in communication with the first input end of the differential amplifying circuit;

The input end of the fifth switch tube is used as the second reference voltage input end for receiving a second reference voltage, and the output end of the fifth switch tube is connected to the second input end of the differential amplifying circuit;

The control end of the third switch tube and the control end of the fifth switch tube are connected to the first preset signal.

Optionally, the reference voltage input circuit further includes a fourth switch tube and a sixth switch tube;

The fourth switch tube is connected between an output end of the third switch tube and a first input end of the differential amplifier circuit;

The sixth switch tube is connected between an output end of the fifth switch tube and a second input end of the differential amplifier circuit;

The control end of the fourth switch tube and the control end of the sixth switch tube are connected to the second preset clock signal.

Optionally, the first preset signal is a static level signal.

Optionally, the first preset signal and the second preset clock signal are mutually inverted clock signals.

A fingerprint sensing chip comprising:

A sensor array comprising any one of the above described sensor units arranged in an array.

An electronic device includes the above-described fingerprint sensing chip.

Compared with the prior art, the technical solution provided by the present invention has the following advantages:

The invention provides a sensor unit, a fingerprint sensing chip and an electronic device. The sensor unit comprises: a fingerprint sensing electrode, a fingerprint sensing circuit and a memory addressing circuit. The fingerprint sensing circuit includes a reference voltage input terminal, a differential amplifying circuit and a first switch. The memory addressing circuit includes a shift register gating circuit and a plurality of parallel bit line units. The shift register gating circuit performs shift processing according to the address signal, the mode switching signal, and the second preset clock signal, generates a plurality of word line signals, and outputs the word line signals to the bit. Line unit. According to the mode switching signal, the addressing circuit and the differential amplifying circuit in the fingerprint sensing circuit are multiplexed, and the newly added memory addressing circuit is used to set the SRAM circuit that needs to be independently set in the prior art in the sensor array, so that the fingerprint sensing is performed. The size of the chip is reduced.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can obtain other drawings according to the provided drawings without any creative work.

1 is a circuit block diagram of a fingerprint recognition sensor chip in the prior art;

2 is a circuit block diagram of a conventional SRAM circuit of a fingerprint recognition sensor chip in the prior art;

3 is a circuit structural diagram of a sensor unit according to an embodiment of the present invention;

4 is a schematic diagram of shifting a clock signal into a word line signal according to an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a shift register gating circuit in a sensor unit according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic diagram of a signal transmission end of a sensor unit according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

As shown in FIG. 1 , the fingerprint recognition sensor chip 10 includes a sensor array 100 and peripheral circuits including an AFE circuit 120, an ADC circuit 130, and addressing. The circuit 210, the digital control circuit 220, the MCU circuit 230, and the SRAM circuit 300, wherein the sensor array 100 includes a plurality of sensor units 110 arranged in an array, the sensing electrodes of the plurality of sensor units 110 are in the fingerprint recognition sensor chip 10 surface.

In the prior art, the SRAM circuit 300 is a separately designed module, as shown in FIG. 2, including a bit line cell array Bit-CellArray 310, a word line decoder X-Decoder 320, a bit line decoder Y-Decoder 330, and Sense Amplifier 340.

Due to the system level requirements of fingerprint recognition, the occupancy width of the sensor unit 110 in the fingerprint recognition sensor chip is usually 50 um. Therefore, in addition to the fingerprint sensing circuit, the sensor unit 110 has extra space. Therefore, the present solution will be prior art. The SRAM circuit 300 is disassembled and integrated into the sensor unit 110, thereby reducing the footprint of the entire fingerprint recognition sensor chip.

Specifically, as shown in FIG. 3, an embodiment of the present invention provides a sensor unit 110', which is applied to a fingerprint recognition sensor chip, and the sensor unit 110' includes: a fingerprint sensing electrode 60, a fingerprint sensing circuit 61, and Memory addressing circuit 62.

The fingerprint sensing circuit 61 includes a reference voltage input terminal (the input terminals of VR1 and VR2 in the figure), a differential amplifying circuit 20, and a first switch 13. In this embodiment, the reference voltage input terminal includes a first reference voltage input. And a second reference voltage input terminal, wherein the first reference voltage input terminal and the second reference voltage input terminal respectively receive the first reference voltage VR1 and the second reference voltage VR2. It should be noted that, in this embodiment, the first reference voltage VR1 may be the same as the voltage value of the second reference voltage VR2. At this time, the reference voltage input terminal may be a reference voltage input terminal, that is, the first reference voltage input. The terminal is at the same end as the second reference voltage input terminal.

In addition, in the embodiment, the first reference voltage input end and the second reference voltage input end can respectively receive the first reference voltage VR1 and the second reference voltage VR2 having different voltage values, so as to facilitate fingerprint sensing. . Specifically, the first reference voltage input end is in communication with the first input end of the differential amplifying circuit, and the second reference voltage input end is in communication with the second input end of the differential amplifying circuit.

The first input end (11 in the figure) of the differential amplifying circuit 20 is connected to the fingerprint sensing electrode 60 and is in communication with the first reference voltage input terminal (wherein, the communication represents the first reference voltage input end and the difference The first input end of the amplifying circuit 20 can perform electrical signal transmission, but the first reference voltage input terminal is not necessarily directly connected to the first input end of the differential amplifying circuit 20, and serves as the fingerprint sensing circuit 61. a second input end (12 in the figure) of the differential amplifying circuit 20 is connected to the second reference voltage input end, and serves as a second input end of the fingerprint sensing circuit 61. a first output end of the differential amplifying circuit 20 (ie, 21 in the figure, that is, OUT1) is used as a first output end of the fingerprint sensing circuit 61, and a second output end of the differential amplifying circuit 20 (at 22 in the figure) That is, OUT2) serves as the second output terminal of the fingerprint sensing circuit 61.

The first switch 13 controls the activation of the differential amplifying circuit according to the received address signal XY, the mode switching signal M, and the first preset signal CK1. Specifically, when the first switch 13 is turned on, the preset current Is flows into the differential amplifying circuit 20, and at this time, the differential amplifying circuit 20 is in the operating mode. When the first switch 13 is turned off, the preset current Is cannot flow into the differential amplifying circuit 20, and at this time, the differential amplifying circuit 20 is in the power-off inoperative mode.

The memory addressing circuit 62 includes at least one bit line unit 30 and a shift register strobe circuit 40.

The bit line unit 30 is connected in parallel between the first input end (11 in the figure) and the second input end (12 in the figure) of the fingerprint sensing circuit 63, and the position of the bit line unit 30 is selected. The signal input terminal is connected to the shift register strobe circuit 40, and the shift register strobe circuit 40 performs shift processing according to the address signal XY, the mode switching signal M, and the second preset clock signal CK2 to generate a plurality of word line signals [WL(1), WL(2), ..., WL(N-1), and WL(N)], and the word line signals [WL(1), WL(2), ..., WL(N-1) and WL(N)] are used as the position selection signals of the bit line unit 30, so that the bit line unit 30 selects the bit line unit 30 for reading and writing operations.

Specifically, as shown in FIG. 4, assuming that the waveform diagram of the second preset clock signal CK2 is as shown in the square wave waveform, the plurality of word line signals generated by the shift register strobe circuit 40 are high level The timing is shifted, and a plurality of word line signals WL(1), WL(2), ..., WL(N-1), and WL(N) are sequentially generated.

The mode switching signal M is used to control the memory addressing circuit 62 to time-multiplex the differential amplifying circuit 20 in the fingerprint sensing circuit 61, and the amplification circuit that needs to be separately set in the SRAM circuit 300 in the prior art is omitted. And setting the Bit-Cell Array of the SRAM circuit 300 in the prior art to the spare space of the sensor unit, so that the size of the fingerprint sensing chip is reduced.

Specifically, the addressing principle of the sensor unit 110' provided by this embodiment is as follows:

When the address signal XY = 0 is set, the sensing unit 110' is not addressed. At this time, the signal input from the reset signal terminal of the shift register gate circuit 40 is 0, so the shift register gate circuit 40 does not operate, and the first switch 13 is turned off, so that the preset current Is cannot flow into the differential amplifier. 20, that is, at this time, the differential amplifier 20 is in the power-off inoperative mode.

When the address signal XY=1, the sensing unit 110' enters the address state. Since the sensing unit addressing and storage addressing in the sensor unit provided in this embodiment are the same addressing circuit multiplexed, the address signal XY=1 is At the same time, it is necessary to further control the value of the mode switching signal M to ensure fingerprint sensing and storage address time-sharing action.

Specifically, in this embodiment, when the mode switching signal M=0 is set, the sensor unit is in a fingerprint sensing mode. At this time, since the mode switching signal M=0, the address signal XY=1, therefore, the first switch 13 is turned on, and the differential amplifying circuit 20 is in an operating state. At the same time, the shift register strobe circuit 40 does not operate. At this time, when the fingerprint sensing electrode 60 has a finger approaching or touching, the voltage signal input by the first input end and the second input end of the differential amplifying circuit 20 may change with respect to the reference voltage VR1 and the reference voltage VR2, and the differential amplifying circuit After being amplified, 20 is output to the first output end and the second output end of the fingerprint sensing circuit 61 for fingerprint recognition by the subsequent circuit to determine whether the current finger fingerprint can pass the security authentication.

When the mode switching signal M=1 is set, the sensor unit is in the storage addressing mode. It should be noted that the storage addressing mode is further divided into a read mode and a write mode. In this case, the first preset signal CK1 needs to be distinguished. In this embodiment, the first preset signal CK1 is set to be a static static level signal. For example, when the first preset signal CK1=0 is set, it is the read mode, and when the first preset signal CK1=1 is set, it is the write mode.

Then, when the sensor unit is in the read mode, the address signal XY=1, the mode switching signal M=1, and the first preset signal CK1=0, at this time, the first switch 13 is turned on, and the differential amplifying circuit 20 is at Working status. At the same time, the shift register strobe circuit 40 has an input signal, and therefore, the shift register strobe circuit 40 is also in an active state. At this time, the shift register strobe circuit 40 performs shift processing according to the second preset clock signal CK2, generates a word line signal representing the selected locating line unit, and then is amplified by the differential amplifying circuit 20, and then output to the fingerprint sensing circuit 61. The first output end and the second output end are used for subsequent circuit identification, determining the position information of the currently selected positioning line unit 30, and realizing data reading.

Similarly, when the sensor unit is in the write addressing mode, the address signal XY=1, the mode switching signal M=1, and the first preset signal CK1=1, at this time, the first switch 13 is turned off, the differential amplifying circuit 20 is in a state of power failure. At this time, the shift register strobe circuit 40 has an input signal, and therefore, the shift register strobe circuit 40 is in an active state. At this time, the external write signal can be backed up to the first input end of the fingerprint sensing circuit 61 (11 in the figure) and the second input end (12 in the figure), and then the shift register strobe circuit 40 is according to the second The preset clock signal CK2 performs a shift process to generate a word line signal characterizing the selected bit line unit 30, thereby realizing the selection of the bit line unit 30 to write the preset data.

It should be noted that, in the sensor unit provided in this embodiment, a combination of one fingerprint sensing electrode 60 and a plurality of bit line units 30 is preferably selected. Since it is assumed that one fingerprint sensing electrode 60 corresponds to only one bit line unit 30, the storage capacity of the entire sensor unit is small. Therefore, in this embodiment, it is preferable to set each fingerprint sensing electrode 60 to correspond to multiple bits. The line unit 30, for example, may be such that one fingerprint sensing electrode 60 corresponds to eight or 16 bit line units 30.

In summary, the storage addressing in this embodiment is performed by first determining one or more fingerprint sensing electrodes 60, and then by using the shift register gating circuit 40 for a plurality of bit lines corresponding to the fingerprint sensing electrodes 60. Unit 30 performs a site-by-site.

On the basis of the foregoing embodiment, the embodiment further provides a specific structure circuit of the fingerprint sensing unit. Referring to FIG. 3, the first logic circuit 31 and the second logic circuit 32 are added to the fingerprint sensing unit. The third logic circuit 33.

The first logic circuit 31 is configured to control conduction between the first input end and the first output end of the differential amplifying circuit and the second input end and the second output end of the differential amplifying circuit. The first logic circuit 31 has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal, and the first input terminal is connected to the first a signal CK1 is provided, the second input terminal is connected to the mode switching signal M, and the first output terminal 70 is connected to a first input end (11 in the figure) of the differential amplifying circuit, and the second output end is Connected with the first output end 21 of the differential amplifying circuit, the third output end is in communication with a second input end of the differential amplifying circuit (12 in the figure), and the fourth output end is amplified by the differential The second output 22 of the circuit is in communication.

Specifically, as shown in FIG. 3, the first logic circuit 31 includes a first AND gate, a first switch tube 51, and a second switch tube 52, and an input terminal of the first AND gate is connected to the first pre- a signal CK1 is provided, the other input end of the first AND gate is connected to the mode switching signal M, and the output end 70 of the first AND gate is respectively connected to the first end of the first switch tube 51 and the first The first end of the second switch tube 52 is connected to the first end of the first switch circuit 51, and the third end of the first switch circuit is the first end. a second output end of the logic circuit 31, a second end of the second switch tube 52 as a third output end of the first logic circuit 31, and a third end of the second switch tube 52 as the first A fourth output of logic circuit 31.

The second logic circuit 32 is used to control the startup of the differential amplification circuit. The second logic circuit 32 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is connected to the first preset signal CK1, and the second input terminal is connected to the second input terminal. The mode switching signal M, the third input terminal is connected to the address signal XY, and the output terminal is used as a control end of the first switch 13.

Specifically, as shown in FIG. 3, the second logic circuit 32 includes a second AND gate and a first NAND gate, and one end of the first NAND gate is connected to the first preset signal CK1, where the The other end of a NAND gate is connected to the mode switching signal M, the output of the first NAND gate is in communication with an input end of the second AND gate, and the other input terminal of the second AND gate is connected The address signal XY, the output of the second AND gate is the output of the second logic circuit 32.

The third logic circuit 33 is used to control the startup of the shift register gating circuit. The third logic circuit 33 has a first input terminal, a second input terminal, and an output terminal, the first input terminal is connected to the address signal XY, and the second input terminal is connected to the mode switching signal M, The output is in communication with a reset signal terminal of the shift register strobe circuit 40 for outputting a reset signal to the shift register.

Specifically, as shown in FIG. 3, the third logic circuit 33 includes a third AND gate, one end of the third AND gate is connected to the address signal XY, and the other end is connected to the mode switching signal M, and the output end is used as The output of the third logic circuit 33.

It should be noted that the first logic circuit 31, the second logic circuit 32, and the third logic circuit 33 provided in this embodiment are for illustrative purposes only, and the embodiment is not limited to the specific structure of the foregoing circuit, as long as the foregoing The circuit function of the embodiment is sufficient.

In addition, the embodiment further provides a specific circuit of the reference voltage input circuit. In conjunction with FIG. 3, the reference voltage input circuit 34 includes a third switch tube 53 and a fifth switch tube 55.

The input end of the third switch tube 53 serves as the first reference voltage input end 61 for receiving the first reference voltage VR1, and the output end of the third switch tube 53 and the differential amplifier circuit 20 The first input is connected.

The input end of the fifth switch tube 55 serves as the second reference voltage input terminal 62 for receiving the second reference voltage VR2, and the output end of the fifth switch tube 55 and the second end of the differential amplifier circuit 20 The input is connected.

Moreover, the control end of the third switch tube 53 and the control end of the fifth switch tube 55 are connected to the first preset signal CK1.

Optionally, in order to further eliminate charge injection, the fourth switch tube 54 and the sixth switch tube 56 are further added to the reference voltage input circuit.

The fourth switch tube 54 is connected between the output end of the third switch tube 53 and the first input end of the differential amplifier circuit 20.

The sixth switch tube 56 is connected between the output end of the fifth switch tube 55 and the second input end of the differential amplifier circuit 20.

Moreover, the control end of the fourth switch tube 54 and the control end of the sixth switch tube 56 are connected to the second preset clock signal CK2.

In this embodiment, the input end of the fourth switch tube 54 is connected to the output end, the input end of the fourth switch tube 54 is connected to the output end of the third switch tube 53, and the output end of the fourth switch tube 54 is connected to the output end. a first input end of the differential amplifying circuit; an input end of the sixth switch tube 56 is connected to the output end; an input end of the sixth switch tube 56 is connected to an output end of the fifth switch tube 55, and an output end of the sixth switch tube 56 is connected The second input of the differential amplifier circuit.

In addition, the embodiment further provides a specific implementation circuit of the shift register gating circuit 40. As shown in FIG. 5, the shift register gating circuit 40 includes a plurality of D flip-flops.

The plurality of the D flip-flops are cascaded, and the CK ends of the plurality of D flip-flops are connected to the second preset clock signal CK2, and the R ends of the plurality of D flip-flops are the same as the third The output of the logic circuit 33 is connected, and the output of the D flip-flop is sequentially used as the output of the shift register gate circuit 40.

The working principle of the sensor unit provided in this embodiment is described in conjunction with the specific circuit structure described above:

Fingerprint sensing mode:

When no sensor unit is selected, the address signal XY=0 at this time, and the output of the third AND gate outputs 0, the shift register strobe circuit 40 does not operate, and all outputs of the shift register strobe circuit 40 at this time The received word line signal WL is 0, and the output end of the first logic circuit is 0, and the first switch 13 is turned off. At this time, both the bit line unit 30 and the differential amplifying circuit 20 do not operate.

When a certain sensor unit is selected, the address signal XY=1 is assumed at this time, and it is assumed that the system sets the mode switching signal M=0 to be the fingerprint recognition mode. In the fingerprint sensing mode, the first preset signal CK1 and the second preset clock signal CK2 are set as clock signals that are mutually inverted. The third switching transistor 53 and the fifth switching transistor 55 are controlled by the first preset signal CK1. The switching states of the fourth switching transistor 54 and the sixth switching transistor 56 are controlled by the second preset clock signal CK2. Since the fourth switching transistor 54 and the sixth switching transistor 56 are constantly turned on, and the second preset clock signal CK2 is inverted from the first preset signal CK1, charge injection can be eliminated.

Since the address signal XY=1, the output terminal WL of the shift register strobe circuit 40 is 0, and at this time, the bit line unit 30 has no signal transmission. At the same time, since the mode switching signal M=0, the output terminal 70 of the first AND gate is 0, so that the first switching transistor 51 and the second switching transistor 52 are turned off. Moreover, since the first preset signal CK1=1 is set, the mode switching signal M=0, so that the first NAND gate outputs 1 and the address signal XY=1, so that the second AND gate outputs 1, and thus the first switch 13 The control terminal receives the closing signal, so that the first switch 13 is turned on, and the current Is flows into the differential amplifying circuit 20, so that the differential amplifying circuit 20 operates normally.

In this embodiment, by setting the values of the first preset signal CK1 and the second preset clock signal CK2, the input states of the control reference voltage VR1 and the reference voltage VR2 are realized, when the fingerprint sensing electrode 60 is caused by the fingerprint ridge valley. When the capacitance changes, the voltage input signal input to the first input end and the second input end of the differential amplifying circuit 20 changes, and after being amplified by the differential amplifying circuit 20, the output is output to the first output end and the second output of the fingerprint sensing circuit 63. End, for subsequent circuit identification, to determine the fingerprint information of the current fingerprint.

Read mode:

When a certain sensor unit is selected, the address signal XY=1 is set at this time, and it is assumed that the system sets the mode switching signal M=1 to store the address mode. It should be noted that the storage addressing mode is further divided into a read mode and a write mode. In this case, it is necessary to distinguish the value of the first preset signal CK1, and set the first preset signal CK1 to be a static static level. signal. For example, when the first preset signal CK1=0 is set, in the read mode, when the first preset signal CK1=1 is set, the address mode is written.

When the sensor unit provided by the present embodiment is in the read mode, preferably, the system sets the reference voltage VR1 and the reference voltage VR2 to a floating state. The first preset signal CK1 of the system setting output is 0. At this time, the third switch tube 53 and the fifth switch tube 55 are turned off, further isolating due to the long distance of the reference voltage VR1 and the reference voltage VR2, and is in a floating state. Possible noise, and since CK1=0, M=1, the first NAND gate outputs 1 and the address signal XY=1, so that the second AND gate outputs 1, and thus the control terminal of the first switch 13 receives To the on signal, a current Is flows into the differential amplifying circuit 20, causing the differential amplifying circuit 20 to operate normally.

At this time, the shift register strobe circuit 40 performs shift processing according to the second preset clock signal CK2, generates a word line signal representing the selected locating line unit, and then is amplified by the differential amplifying circuit 20, and then output to the fingerprint sensing circuit 61. The first output end and the second output end are used for subsequent circuit identification, determining content information of the currently selected positioning line unit 30, and realizing data reading.

The second preset clock signal CK2 can cause the shift register strobe circuit 40 to generate 100---000, 010---000, 001---000, ---, 000---100,000- The output signal WL of -010,000---001 is received by the bit line unit 30.

Write mode:

When the sensor unit is in the write mode, the address signal XY=1, the mode switching signal M=1, and the first preset signal CK1=1.

CK1=1, M=1, so that the first NAND gate outputs 0, so that the second AND gate outputs 0, and thus the control terminal of the first switch 13 receives the shutdown signal, the first switch 13 is turned off, the current Is and the differential amplifying circuit 20 is isolated so that the differential amplifying circuit 20 does not operate. Meanwhile, since CK1=1, M=1, the first AND gate output is 1, so that the first switching transistor 51 and the second switching transistor 52 are closed, at this time, the first output terminal 21 and the second output of the differential amplifying circuit 20 The terminal 22 can be backfilled by the peripheral circuit to the first input terminal and the second input terminal of the differential amplifying circuit 20 to perform data writing.

At this time, the external write signal can be backed up to the first input end of the fingerprint sensing circuit 61 (11 in the figure) and the second input end (12 in the figure), and then the shift register strobe circuit 40 is according to the second The preset clock signal CK2 generates a word line signal characterizing the selected bit line unit 30 to implement selection of the bit line unit 30 to write preset data.

Further, in the sensor unit provided by the embodiment, the inventor considers that, in order to avoid adding signal traces during reading and writing of the SRAM, the multiplexing scheme in this embodiment uses the original signal as much as possible. line. It should be noted that both the read mode and the write mode of the SRAM set the address signal XY and the mode switch signal M to be 1, except that the first preset signal CK1 is different in the two modes. Then at this time:

M=0 is the fingerprint sensing mode (Sensing Mode);

M=1, CK1=0 is the SRAM read mode (SRAMMode, Read);

M=1, CK1=1 is the SRAM write mode (SRAMMode, Write). When the first preset signal CK1=1, the first input end of the differential amplifying circuit 20 is directly connected to the first reference voltage VR1, and the second input end of the differential amplifying circuit 20 is directly connected to the second reference voltage VR2, therefore, The embodiment sets the first reference voltage VR1 and the second reference voltage VR2 to a floating potential (or in a floating state) in the SRAM read and write mode to make the first reference voltage VR1 and the second reference voltage VR2 does not interfere with the input of differential amplifier 20.

In summary, the sensor unit provided in the embodiment, the fingerprint sensing operation and the memory addressing operation are performed in a time-sharing manner, thereby avoiding noise interference of the memory addressing operation on the fingerprint sensing operation; and the word line in the memory addressing relative to the prior art. The signal pull line is too long, which affects the SRAM read speed. This embodiment is also equivalent to effectively cutting the pull line, which helps to reduce the read time of the SRAM.

In addition, the embodiment further provides a schematic diagram of a signal transmission end of the sensor unit, as shown in FIG. 6, including:

The first reference voltage signal transmission end (indicated by VR1 in FIG. 6), the second reference voltage signal transmission end (indicated by VR2 in FIG. 6), the first preset signal transmission end (indicated by CK1 in FIG. 6), and the second preset clock The signal transmission end (indicated by CK2 in Fig. 6) and the mode switching signal transmission end (marked by M in Fig. 6), the first output signal transmission end (indicated by OUT1 in Fig. 6), and the second output signal transmission end (indicated by OUT2 in Fig. 6) ), the preset current signal transmission end (Is is marked in Fig. 6), and two address signal transmission ends (indicated by X and Y in Fig. 6).

The first reference voltage signal transmission end is in communication with the first reference voltage input end for receiving an externally provided first reference voltage VR1.

The second reference voltage signal transmitting end is in communication with the second reference voltage input end for receiving an externally provided second reference voltage VR2.

The first preset signal transmission end is configured to receive an externally provided first preset signal CK1.

The second preset clock signal transmission end is configured to receive an externally provided second preset clock signal CK2.

The mode switching signal transmission end is configured to receive a mode switching signal M sent by the system.

The first output signal transmitting end is connected to the first output end OUT1 of the sensor unit.

The second output signal transmitting end is connected to the second output end OUT2 of the sensor unit.

The preset current signal transmitting end is in communication with the input end of the first switch 13, and receives an externally supplied current Is.

The address signal transmission end indicated by X in Fig. 6 transmits an input sub-signal of the address signal XY.

The address signal transmission end indicated by Y in Fig. 6 transmits a further input sub-signal of the address signal XY.

It should be noted that, in this embodiment, the signal transmission end of the sensor unit only adds a mode switching signal transmission end (the M end in FIG. 6) compared with the signal transmission end of the sensor unit in the prior art.

The embodiment further provides a fingerprint sensing chip, the fingerprint sensing chip comprising a sensor array, the sensor array comprising a sensor unit 110 arranged in a two-dimensional array, the sensor unit 110 comprising a fingerprint sensing electrode, A fingerprint sensing circuit and a memory addressing circuit, the memory addressing circuit being in communication with the fingerprint sensing electrode for determining a position of the touched fingerprint sensing electrode.

The fingerprint sensing chip further includes an addressing circuit, an AFE circuit, an analog circuit, and a digital circuit.

Referring to FIG. 1 , the existing fingerprint recognition sensor chip includes an addressing circuit 210 (XY Decoder), which is only used to address the fingerprint sensing array, and the SRAM circuit 300 also includes a specific addressing circuit. . In this embodiment, the addressing circuit of the fingerprint sensing array in the prior art is reused, so that the addressing circuit realizes the fingerprint sensing address and the newly added memory addressing circuit realizes the memory addressing.

On the basis of the foregoing embodiments, the embodiment further provides an electronic device, including the above-mentioned fingerprint sensing chip. For the working principle of the circuit, refer to the above embodiment.

In summary, the present invention provides a sensor unit, a fingerprint sensing chip, and an electronic device. The sensor unit includes a fingerprint sensing electrode, a fingerprint sensing circuit, and a memory addressing circuit. The fingerprint sensing circuit includes a reference voltage input terminal, a differential amplifying circuit and a first switch. The memory addressing circuit includes a shift register gating circuit and a plurality of parallel bit line units. The shift register gating circuit performs shift processing according to the address signal, the mode switching signal, and the second preset clock signal, generates a plurality of word line signals, and outputs the word line signals to the bit line unit. . According to the mode switching signal, the addressing circuit and the differential amplifying circuit in the fingerprint sensing circuit are multiplexed, and the newly added memory addressing circuit is used to set the SRAM circuit that needs to be independently set in the prior art in the sensor array, so that the fingerprint sensing is performed. The size of the chip is reduced.

The various embodiments in the present specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same similar parts between the various embodiments may be referred to each other. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but the scope of the invention is to be accorded

Claims (10)

1. A sensor unit, comprising: a fingerprint sensing sensor chip, comprising: a fingerprint sensing electrode, a fingerprint sensing circuit, and a memory addressing circuit;

   The fingerprint sensing circuit includes a reference voltage input terminal, a differential amplifying circuit, and a first switch;

   a first input end of the differential amplifying circuit is connected to the fingerprint sensing electrode, and is connected to the reference voltage input end, and serves as a first input end of the fingerprint sensing circuit, and a second An input end is connected to the reference voltage input end, and as a second input end of the fingerprint sensing circuit, a first output end of the differential amplifying circuit is used as a first output end of the fingerprint sensing circuit, a second output end of the differential amplifying circuit serves as a second output end of the fingerprint sensing circuit;

   The first switch controls activation of the differential amplifying circuit according to the received addressing signal, the mode switching signal, and the first preset signal;

   The memory addressing circuit includes at least one bit line unit and a shift register gating circuit, the bit line unit being connected in parallel between the first input end and the second input end of the fingerprint sensing circuit, and the bit line The position selection signal input end of the unit is connected to the shift register strobe circuit, and the shift register strobe circuit performs shift processing according to the address signal, the mode switching signal and the second preset clock signal to generate a plurality of a word line signal, and using the word line signal as a position selection signal of the bit line unit;

   The mode switching signal is used to control the memory addressing circuit to time-multiplex the differential amplifying circuit in the fingerprint sensing circuit.
2. The sensor unit according to claim 1, further comprising: a first logic circuit, a second logic circuit, and a third logic circuit,

   The first logic circuit is configured to control conduction between the first input end and the first output end of the differential amplifying circuit and the second input end and the second output end of the differential amplifying circuit; the first logic circuit has a first input end a second input end, a first output end, a second output end, a third output end, and a fourth output end, the first input end is connected to the first preset signal, and the second input end is connected to the a mode switching signal, the first output end is in communication with a first input end of the differential amplifying circuit, and the second output end is in communication with a first output end of the differential amplifying circuit, the third output end is a second input end of the differential amplifying circuit is in communication, and the fourth output end is in communication with a second output end of the differential amplifying circuit;

   The second logic circuit is configured to control activation of the differential amplification circuit; the second logic circuit has a first input terminal, a second input terminal, a third input terminal, and an output terminal, and the first input terminal is connected to the first a preset signal, the second input terminal is connected to the mode switching signal, the third input terminal is connected to the address signal, and the output end is used as a control end of the first switch;

   The third logic circuit is configured to control activation of a shift register gating circuit; the third logic circuit has a first input end, a second input end, and an output end, and the first input end is connected to the address signal, The second input terminal is coupled to the mode switching signal, and the output terminal is in communication with a reset signal terminal of the shift register gating circuit.
3. The sensor unit according to claim 2, wherein

   The first logic circuit includes a first AND gate, a first switching transistor, and a second switching transistor, wherein one input terminal of the first AND gate is connected to the first preset signal, and the other of the first AND gate Inputting the mode switching signal, the output end of the first AND gate is respectively connected to the first end of the first switch tube and the first end of the second switch tube, the first switch tube The second end serves as a first output end of the first logic circuit, the third end of the first switch tube serves as a second output end of the first logic circuit, and the second end of the second switch tube serves as a second end a third output end of the first logic circuit, and a third end of the second switch circuit as a fourth output end of the first logic circuit;

   The second logic circuit includes a second AND gate and a first NAND gate. One end of the first NAND gate is connected to the first preset signal, and the other end of the first NAND gate is connected to the mode. Switching a signal, the output of the first NAND gate is in communication with an input of the second AND gate, and the other input of the second AND gate is connected to the address signal, the second AND gate The output end serves as an output end of the second logic circuit;

   The third logic circuit includes a third AND gate, one end of the third AND gate is connected to the address signal, the other end is connected to the mode switching signal, and the output end is used as an output end of the third logic circuit.
4. The sensor unit according to claim 1, wherein the reference voltage input terminal comprises a first reference voltage input terminal and a second reference voltage input terminal, the first reference voltage input terminal and the differential amplification circuit The first input terminal is in communication, and the second reference voltage input terminal is in communication with the second input end of the differential amplifying circuit.
5. The sensor unit according to claim 4, further comprising a reference voltage input circuit, wherein the reference voltage input circuit comprises a third switch tube and a fifth switch tube;

   The input end of the third switch tube serves as the first reference voltage input end for receiving a first reference voltage, and the output end of the third switch tube is in communication with the first input end of the differential amplifying circuit;

   The input end of the fifth switch tube is used as the second reference voltage input end for receiving a second reference voltage, and the output end of the fifth switch tube is connected to the second input end of the differential amplifying circuit;

   The control end of the third switch tube and the control end of the fifth switch tube are connected to the first preset signal.
6. The sensor unit according to claim 5, wherein the reference voltage input circuit further comprises a fourth switch tube and a sixth switch tube;

   The fourth switch tube is connected between an output end of the third switch tube and a first input end of the differential amplifier circuit;

   The sixth switch tube is connected between an output end of the fifth switch tube and a second input end of the differential amplifier circuit;

   The control end of the fourth switch tube and the control end of the sixth switch tube are connected to the second preset clock signal.
7. The sensor unit of claim 1 wherein said first predetermined signal is a static level signal.
8. The sensor unit according to claim 1, wherein the first preset signal and the second preset clock signal are mutually inverted clock signals.
9. A fingerprint sensing chip, comprising:

   A sensor array comprising the sensor unit of any of claims 1-8 arranged in an array.
10. An electronic device comprising the fingerprint sensing chip of claim 9.

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