CN109585556B - 半导体器件性能改进 - Google Patents

半导体器件性能改进 Download PDF

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Publication number
CN109585556B
CN109585556B CN201810920220.4A CN201810920220A CN109585556B CN 109585556 B CN109585556 B CN 109585556B CN 201810920220 A CN201810920220 A CN 201810920220A CN 109585556 B CN109585556 B CN 109585556B
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hydrogen
dielectric layer
layer
gate dielectric
gate
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CN109585556A (zh
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栾洪发
张惠政
赵晟博
顾文昱
陈毅帆
彭峻彦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US15/952,714 external-priority patent/US10504735B2/en
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Abstract

本文描述的实施例在高压退火工艺之后提供热处理工艺以将氢保持在场效应晶体管中的沟道区与栅介电层之间的界面处，同时从栅介电层的主体部分去除氢。热处理工艺可以减小由高压退火引起的阈值电压偏移量。高压退火和热处理工艺可以在形成栅介电层之后的任何时间实施，因此不会中断现有的工艺流程。本发明的实施例还涉及半导体器件性能改进。

Description

半导体器件性能改进
技术领域
本发明的实施例涉及半导体器件性能改进。
背景技术
随着半导体工业进入纳米技术工艺节点以追求更高的器件密度、更高的性能和更低的成本，来自制造和设计问题的挑战已经引起三维设计的发展，诸如鳍式场效应晶体管(FinFET)。FinFET器件通常包括具有高高宽比的半导体鳍，并且在半导体鳍中形成沟道和源极/漏极区。利用沟道的增大的表面积的优点，在鳍结构的侧面上方并且沿着侧面形成(例如，包裹)栅极，以产生更快、更可靠且更好控制的半导体晶体管器件。然而，随着按比例缩小，呈现了新的挑战。
发明内容
本发明的实施例提供了一种半导体结构，包括：有源区，位于衬底上，所述有源区具有沟道区；栅极结构，位于所述有源区的所述沟道区上方，其中，所述栅极结构包括：界面层，位于所述有源区上方；栅介电层，位于所述界面层上方；和栅电极层，位于所述界面层上方；并且其中，所述界面层中的氢的峰值浓度与所述栅介电层中的氢的峰值浓度的比率在0.1至10的范围内。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：对具有栅介电层的结构实施高压退火工艺，以将氢引入至所述栅介电层和沟道区之间的界面，其中，所述栅介电层形成在有源区的沟道区上方；以及在实施所述高压退火工艺之后，实施退火后处理以减少所述栅介电层中的氢。
本发明的又一实施例提供了一种形成半导体器件的方法，包括：在有源区的沟道区上方形成栅极结构，其中，所述栅极结构包括位于所述有源区上方的栅介电层；在第一压力下退火所述栅极结构以将氢引入到所述栅介电层与所述沟道区之间的界面；以及在第二压力下对所述栅极结构实施退火后处理以减少所述栅介电层中的氢，其中，所述第一压力高于所述第二压力。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图1C、图2A至图2B、图3A至图3B、图4A至图4B、图5A至图5B、图6A至图6B、图7A至图7B和图8A至图8B是根据一些实施例的在形成半导体器件的示例工艺中的中间阶段的各个中间结构的各种视图。
图9是根据一些实施例的在高压退火工艺之后的晶体管器件的沟道区的截面图。
图10是根据一些实施例的在退火后处理工艺之后的晶体管器件的沟道区的截面图。
图11包括根据一些实施例的在具有和没有示例性退火后处理工艺的情况下形成的器件中的示例氢浓度分布。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不表示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。术语“氢”可以包括氢(H)、氘(D)以及氢的其他同位素。
本文描述了形成诸如包括鳍式场效应晶体管(FinFET)的半导体器件的方法以及由该方法形成的结构。特别地，本发明的实施例提供了通过高压退火工艺和用于阈值电压恢复的退火后处理工艺来改进FinFET性能的方法。
在形成FinFET上的栅极结构的上下文中描述本文描述的示例实施例。本发明的一些方面的实现可以用于其他工艺中、其他器件中和/或其他层中。例如，其他示例器件可以包括平面FET、横向全环栅(HGAA)FET、垂直全环栅(VGAA)FET以及其他器件。描述了示例方法和结构的一些变型。本领域普通技术人员将容易地理解在其他实施例的范围内可以预期的其他修改。虽然方法实施例可以以特定顺序描述，但是各种其他方法实施例可以按照任何逻辑顺序实施，并且可以包括比在此描述的更少或更多的步骤。
图1A-图1C至图8A-图8B是根据一些实施例的在形成半导体器件的示例工艺中的中间阶段处的各个中间结构的视图。特别地，图1A-图1C至图8A-图8B描述了用替换栅极工艺形成FinFET结构的阶段。
图1A、图1B和图1C示出了根据一些实施例的在形成半导体器件的示例工艺中的阶段处的中间结构的不同视图。图1A和图1B是中间结构的不同截面图，而图1C是中间结构的立体图。
鳍74位于半导体衬底70上。隔离区78位于半导体衬底70上并且设置在相邻的鳍74之间。每个鳍74位于隔离区78之上并且从相邻的隔离区78之间突出。沿着鳍74的侧壁并且在鳍74的顶面上方形成栅极堆叠件(或更一般地说，栅极结构)，其中每个栅极堆叠件包括界面电介质80、伪栅极层82和掩模84。源极/漏极区52a-f设置在鳍74的相应的区域中。
图1C进一步示出了在其他图中使用的参考截面。截面A-A位于沿着例如相对的源极/漏极区52a-c之间的一个鳍74中的沟道的平面中。截面B-B处于与截面A-A垂直的平面中，并且跨过相邻鳍74中的源极/漏极区52a和源极/漏极区52d。以“A”标记结尾的图示出了对应于截面A-A的处理在各种情况下的截面图，并且以“B”标记结尾的图示出了对应于截面B-B的处理在各种情况下的截面图。在一些图中，可以省略其中示出的组件或部件的一些附图标记以避免模糊其他组件或部件；这是为了便于描述图。
半导体衬底70可以是或包括可以掺杂(例如，用p型或n型掺杂剂)或未掺杂的块状半导体衬底、绝缘体上半导体(SOI)衬底等。半导体衬底70的半导体材料可以包括包含硅(Si)或锗(Ge)的元素半导体；化合物半导体；合金半导体；或它们的组合。
诸如通过在鳍74之间蚀刻沟槽，鳍74可以由半导体衬底70形成。隔离区78可以形成在鳍74之间的沟槽中。隔离区78可以包括或者可以是绝缘材料，诸如氧化物(诸如氧化硅)、氮化物等或它们的组合。鳍74从相邻的隔离区78之间突出，这可以至少部分地由此将鳍74描绘为半导体衬底70上的有源区。鳍74和隔离区78可以通过任何可接受的工艺形成并且可以包括任何可接受的材料。在一些实例中，鳍74可以包括异质外延结构(例如，与半导体衬底70的半导体材料晶格失配的材料)或其他结构。
栅极堆叠件位于鳍74上方并且垂直于鳍74横向延伸。可以通过顺序地形成各个层，然后将这些层图案化成栅极堆叠件来形成用于栅极堆叠件的界面电介质80、伪栅极层82和掩模84。界面电介质80可以包括或者可以是氧化硅、氮化硅等或它们的多层。伪栅极层82可以包括或者可以是硅(例如多晶硅)或另一种材料。掩模84可以包括或是氮化硅、氮氧化硅、碳氮化硅等或它们的组合。可以使用任何可接受的工艺来沉积和然后图案化用于界面电介质80、伪栅极层82和掩膜84的层，以形成用于每个栅极堆叠件的掩膜84、伪栅极层82和界面电介质80。
图2A和图2B示出了沿着栅极堆叠件的栅极间隔件86、鳍74中的外延源极/漏极区92、各个组件上方的接触蚀刻停止层(CESL)96以及CESL96上方的第一层间电介质(ILD)100的形成。沿着栅极堆叠件的侧壁(例如，界面电介质80、伪栅极层82和掩模84的侧壁)以及在鳍74上方形成栅极间隔件86。例如，取决于隔离区78之上的鳍74的高度，剩余的栅极间隔件86可以沿着鳍74的侧壁保留。例如，可以通过共形地沉积用于栅极间隔件86的一个或多个层并且各向异性地蚀刻该一个或多个层来形成栅极间隔件86。用于栅极间隔件86的一个或多个层可以包括或是碳氧化硅、氮化硅、氮氧化硅、碳氮化硅等、它们的多层或它们的组合。
在形成栅极间隔件86之后，使用栅极堆叠件和栅极间隔件86作为掩模在鳍74中形成凹槽，并且在凹槽中外延生长外延源极/漏极区92。凹槽以及因此外延源极/漏极区92形成在栅极堆叠件的相对侧上的鳍74中。凹槽可以通过蚀刻工艺形成，并且由于蚀刻工艺的性质，凹槽可以具有各种截面轮廓。外延源极/漏极区92可以包括或可以是硅锗、碳化硅、硅磷、纯或基本上纯的锗、III-V族化合物半导体、II-VI族化合物半导体等。外延源极/漏极区92可以延伸超出鳍74的侧壁和顶面(例如，凸起)并且可以具有小平面，该小平面对应于半导体衬底70的晶面。
本领域普通技术人员还将容易地理解，可以省略凹槽和源极/漏极区92的外延生长，并且可以通过使用栅极堆叠件和栅极间隔件86作为掩模，将掺杂剂注入到鳍74中来形成源极/漏极区。在实现外延源极/漏极区92的一些实例中，也可以例如通过在外延生长期间的原位掺杂和/或通过在外延生长之后将掺杂剂注入到外延源极/漏极区92来掺杂外延源极/漏极区92。因此，如果合适的话，可以通过掺杂(例如，如果合适的话，通过注入和/或外延生长期间的原位掺杂)和/或通过外延生长来描绘源极/漏极区，掺杂和/或外延生长可以进一步描绘有源区，在有源区中描绘源极/漏区。
CESL96共形地沉积在外延源极/漏极区92的表面、栅极间隔件86的侧壁和顶面、掩模84的顶面和隔离区78的顶面上。通常，蚀刻停止层可以在形成例如接触件或通孔时提供停止蚀刻工艺的机制。蚀刻停止层可以由与相邻层或组件具有不同蚀刻选择性的介电材料形成。CESL 96可以包括或是氮化硅、碳氮化硅、碳氮化物等或它们的组合。然后在CESL 96上方沉积第一ILD 100。第一ILD 100可以包括或是二氧化硅、低k介电材料(例如具有比二氧化硅低的介电常数的材料，诸如氮氧化硅)、磷硅酸盐(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、有机硅酸盐玻璃(OSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物等或它们的组合。
图3A和图3B示出去除第一ILD 100的部分、CESL 96层的部分和掩模84以暴露伪栅极层82。第一ILD 100和CESL 96形成为具有与伪栅极层82的顶面共面的顶面。可以实施诸如CMP的平坦化工艺以使第一ILD 100和CESL 96的顶面与伪栅极层82的顶面平齐。CMP还可以去除伪栅极层82上的掩模84(并且在一些情况下，栅极间隔件86的上部)。因此，伪栅极层82的顶面通过第一ILD 100和CESL 96暴露。
图4A和图4B示出了在伪栅极层82已经通过第一ILD 100和CESL 96暴露之后，诸如通过一个或多个蚀刻工艺去除伪栅极层82。可以通过对伪栅极层82具有选择性的蚀刻工艺来去除伪栅极层82，其中界面电介质80用作蚀刻停止层。在栅极间隔件86之间形成凹槽101。
在一些实例中，可以通过对界面电介质80具有选择性的蚀刻工艺来去除界面电介质80，并且鳍74的沟道区通过凹槽101暴露。随后可以在鳍74的沟道区上方的凹槽101中形成另一个替换界面电介质80。在一些实施例中，替换界面电介质80可以是在鳍74上方形成的原生氧化物，诸如氧化硅。在一些实施例中，替换界面电介质80可以包括或可以是氧化硅、氮化硅等或它们的多层，并且可以在鳍74上热和/或化学地生长，或者诸如通过PECVD、ALD或其他沉积技术共形地沉积。
在一些实例中，界面电介质80不被去除并且保留，使得各个替换栅极结构形成在界面电介质80上，如随后所述。随后的描述可以涉及界面电介质80，随后的描述可以应用于如图1A至图1C所述形成的界面电介质80，和/或上述替换界面电介质80。
图5A和图5B示出了形成在凹槽101中的栅介电层120。栅介电层120可以共形地沉积在去除栅极堆叠件的凹槽101中(例如，在隔离区78的顶面上、沿着沟道区并且位于鳍74上方的界面电介质80的侧壁和顶面以及栅极间隔件86的侧壁)以及第一ILD 100、CESL 96和栅极间隔件86的顶面上。栅介电层120可以是或可以包括氧化硅(SiO2)、氮氧化硅(SiON)、氮化硅(SiN)、高k介电材料、它们的多层或其他介电材料。高k介电材料可具有大于约7.0的k值。高k介电材料可以包括Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或金属硅酸盐或它们的组合。可以通过ALD、PECVD、MBD或其他沉积技术沉积栅介电层120。在一些实施例中，栅介电层120可以包括在鳍74的沟道区上方的界面电介质80的正上方形成的高k介电层。
在形成栅介电层120之后，可以实施退火工艺和/或退火后处理工艺。可以在形成栅介电层120之后和/或在形成栅介电层120之后的任何工艺之后立即实施退火工艺和/或退火后处理工艺。示例退火工艺和退火后处理工艺的其他细节在下面进一步描述。
然后，一个或多个共形层121可以共形地沉积在栅介电层120上。一个或多个共形层121可以包括一个或多个阻挡层、覆盖层和材料功函数调节层的任何组合。在适当的情况下，每个实现的共形层121可以共形地沉积在栅介电层120上或先前的共形层121上。阻挡层、覆盖层和材料功函数调节层可以各自包括或者可以是钽、氮化钽、钛、氮化钛等或它们的组合，并且可以通过ALD、PECVD、MBD或其他沉积技术沉积。
在一个或多个共形层121上方填充导电材料122，或者在栅介电层120上填充导电材料122。导电材料122可以填充去除栅极堆叠件处的剩余凹槽101。导电材料122可以是或包括含金属材料，诸如Co、Ru、Al、W、Cu、它们的多层或它们的组合。导电材料122可以通过ALD、PECVD、MBD、PVD或其他沉积技术沉积填充。
通过如CMP的平坦化工艺去除第一ILD 100、CESL 96和栅极间隔件86的顶面之上的过量导电材料122、一个或多个共形层121和栅介电层120。因此，如图6A和图6B所示，形成替换栅极结构，每个替换栅极结构包括栅介电层120和栅电极，其中栅电极被认为包括导电材料122和一个或多个共形层121。
在第一ILD 100、替换栅极结构、栅极间隔件86和CESL 96上方形成第二ILD 130。虽然未示出，但在一些实例中，可以在第一ILD 100等上沉积蚀刻停止层(ESL)，并且第二ILD 130可以沉积在ESL上方。蚀刻停止层可以包括或是氮化硅、碳氮化硅、碳氧化硅、碳氮化物等或它们的组合，并且可以通过CVD、PECVD、ALD或其他沉积技术来沉积。第二ILD 130可以包括或是二氧化硅、低k介电材料(诸如氧氮化硅)、PSG、BSG、BPSG、USG、FSG、OSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物等或它们的组合。可以通过旋涂、CVD、FCVD、PECVD、PVD或其他沉积技术来沉积第二ILD 130。
如图7A和图7B所示，导电部件134形成为穿过第二ILD 130和第一ILD 100至外延源极/漏极区92。例如，导电部件134可以包括粘合层和/或阻挡层以及位于粘合层和/或阻挡层上的导电材料。在一些实例中，如图所示，导电部件134可以包括位于外延源极/漏极区92上的硅化物区136。粘合层和/或阻挡层可以共形地沉积在暴露外延源极/漏极区92的开口中和第二ILD 130上方。粘合层和/或阻挡层可以是或包括钛、氮化钛、氧化钛、钽、氮化钽、氧化钽等或它们的组合，并且可以通过ALD、CVD或其他沉积技术来沉积。通过使外延源极/漏极区92的上部与粘合层和/或阻挡层反应，可以在外延源极/漏极区92的上部形成硅化物区136。可以实施退火以促进外延源极/漏极区92与粘合层和/或阻挡层的反应。导电材料可以沉积在粘合层和/或阻挡层上并且填充开口。导电材料可以是或包括钨、铜、铝、金、银、它们的合金等或它们的组合，并且可以通过CVD、ALD、PVD或其他沉积技术来沉积。在沉积导电部件134的材料之后，可以通过使用诸如CMP的平坦化工艺去除多余材料，使得导电部件134和第二ILD 130的顶面可以共面。导电部件134可以是或可以被称为接触件、插塞等。
随后在多个金属间介电(IMD)层内形成额外的导电部件以实现用于器件的电连接。例如，可以在SRAM器件中的晶体管上方形成十二个IMD层。图8A和图8B示出了在第二ILD130上方形成的后续IMD 140、142。根据器件的设计，诸如通过镶嵌工艺(例如，双镶嵌工艺)在其中形成导电部件144。
根据一些实施例，实施退火工艺和退火后处理工艺以改进器件性能。在一些实施例中，在形成栅介电层120之后的任何时间实施退火工艺和退火后处理工艺。退火工艺和退火后处理工艺可以改进器件中的载流子迁移率。
在一些实施例中，退火工艺是高压退火(HPA)工艺。可以实施高压退火工艺以引入小尺寸的原子以钝化界面处的悬空键以减少界面缺陷。例如，可以将诸如氢或氘的小尺寸原子引入鳍74的沟道区与栅介电层120之间的界面区(例如界面电介质80)以减少界面缺陷并且改进晶体管中的载流子迁移率。
在一些实施例中，在诸如用于处理多个衬底的炉管、单片衬底处理设备或其他合适的热处理设备实施高压退火工艺。在一些实施例中，高压退火工艺可以在氢气(H2)、氘气(D2)、氮气(N2)、氩气(Ar)、氦气(He)或它们的组合的环境中实施。高压退火工艺可以在约5个大气压至约70个大气压的范围内的压力下实施。工艺温度可以在约200℃至约700℃的范围内。在一些实施例中，工艺温度可以在约350℃至约500℃的范围内，例如约400℃。高压退火工艺可以实施约3分钟至约4小时的范围内的持续时间，例如约10分钟至约1小时。
图9是根据一些实施例的在高压退火工艺之后的晶体管器件的鳍74中的沟道区的部分以及替换栅极结构(例如，界面电介质80和栅介电层120)的截面图。将氢150引入到栅介电层120和界面电介质80或引入到鳍74的沟道区与栅介电层120之间的界面。
鳍74中的沟道材料可以是或包括硅、锗、IV族化合物(诸如硅锗(SiGe))、III-V族化合物、另一种半导体材料或它们的组合。
栅介电层120可以是例如FinFET的高k介电层。在一些实施例中，栅介电层120可以包括高k介电材料，诸如Hf、Al、Zr、La、Mg、Ba、Ti、Pb的金属氧化物或金属硅酸盐或它们的组合、氧化硅(SiO2)、氮氧化硅(SiON)、氮化硅(SiN)或它们的组合。在一些实施例中，栅介电层120可以具有从约1nm到约10nm范围内的厚度。
界面电介质80可以包括在鳍74的沟道区上方形成的原生氧化物或者通过热生长、化学生长或共形沉积工艺(诸如ALD、CVD等)形成的氧化硅、氮化硅等。在一些实施例中，界面电介质80可以具有从大于0nm到约5.0nm的范围内的厚度，诸如例如约1.0nm。
界面电介质80中和/或鳍74的沟道区与栅介电层120之间的界面处的氢原子可以减少界面缺陷并且可以改进晶体管中的载流子迁移率。然而，栅介电层120或栅介电层120的主体部分中的氢原子可能导致各种问题，诸如晶体管的阈值电压(Vt)的偏移，特别是在P型晶体管中。
测量表明，在高压退火工艺之后，氢在界面电介质80处具有较高的峰值浓度并且在主体栅介电层120处具有较低的峰值浓度。在主体栅介电层120具有约10nm的厚度并且界面电介质80具有2.5nm的厚度的结构中，主体栅介电层120中的氢原子的总量高于界面电介质80中的氢的总量。在一些实施例中，P-型场效应晶体管具有约0.7伏特的初始阈值电压。在高压退火中引入的氢可能导致阈值电压偏移约120mV。
一些实施例提供退火后处理工艺以恢复由高压退火工艺引起的阈值电压偏移。在一些实施例中，退火后处理工艺是快速热工艺、激光退火工艺等。退火后处理工艺减少了主体栅介电层120中的氢原子，同时维持界面电介质80中的氢浓度。
在一些实施例中，在诸如用于处理多个衬底的炉管、单片衬底处理设备或诸如激光退火设备的其它合适热处理设备实施退火后处理工艺。在一些实施例中，高压退火工艺和退火后处理工艺可以在同一设备中连续实施。
退火后处理工艺可以在包括氮气(N2)、氩气(Ar)、氦气(He)、氢气(H2)、氘气(D2)或它们的组合中的一种或多种的环境中实施。环境的组成可以通过工艺之前的主体栅介电层120和界面电介质80中的氢量来确定。例如，可以包括氮气(N2)、氩气(Ar)、氦气(He)或它们的组合，但不含氢气(H2)或氘气(D2)以降低主体栅介电层120中的氢浓度。例如，环境包括氮气。在另一个实施例中，环境可以包括氮气(N2)、氩气(Ar)、氦气(He)或它们的组合以及一些氢气(H2)或氘气(D2)以保持界面电介质80中的氢浓度。在一些实例中，可以调节环境的组成，例如通过在工艺期间增大或减小H2或D2的比率以实现目标效果，诸如实现界面电介质80中的氢浓度水平。在一些实施例中，处理气体中的H2或D2与总处理气体的体积比率在从约0到约100的范围内。
在一些实施例中，退火后处理工艺在约1毫托至约5个大气压的范围内实施。在一些实施例中，退火后处理工艺在低压下实施，例如在1托至10托的范围内。在一些实施例中，退火后处理工艺可以在正常的气氛中实施，诸如1个大气压。在一些实施例中，退火后处理工艺可以在高压下实施，诸如在1个大气压至5个大气压的范围内。
在一些实施例中，退火后处理工艺的工艺温度在约200℃至约700℃的范围内。如果工艺温度太低，诸如氢原子的原子可能不能获得足够的能量以在介电层中移动。如果工艺温度太高，衬底中的一些层可能熔化或引起不期望的物理或化学反应。在一些实施例中，工艺温度可以在约350℃至约500℃的范围内，例如约400℃。
退火后处理工艺可以实施约5分钟至约150分钟的持续时间。在一些实施例中，退火后处理工艺实施约10分钟至约90分钟的范围内。在一些实施例中，退火后处理工艺的持续时间可以足够长以将氢保留在沟道区和栅介电层120之间的界面处(例如，在界面电介质80中)，同时从栅介电层120的主体部分去除氢。
图10是根据一些实施例的在退火后处理工艺之后的晶体管器件的沟道区的部分和替换栅极结构的截面图。测量表明，在退火后处理工艺之后，氢在界面电介质80处保持在较高峰值浓度，并且在主体栅介电层120处保持在较低峰值浓度。然而，界面电介质80和主体栅介电层120中的氢原子的总量大致相等。在一些实施例中，主体栅介电层120中的氢原子的总量低于界面电介质80中的氢原子的总量。在一些实例中，阈值电压偏移在约10mV至约20mV的范围内。在一些实施例中，高压退火工艺之前的初始阈值电压是约0.7伏特。退火后处理工艺之后的最终阈值电压偏移可以在初始阈值电压的约1.4％至约2.9％的范围内。
在一些实施例中，退火工艺和退火后处理工艺降低主体栅介电层120和界面电介质80中的峰值氢浓度和总氢量。在一些实施例中，退火工艺和退火后处理工艺增大界面电介质80和主体栅介电层120中的峰值浓度和总氢量的比率。在一些实施例中，在实施退火工艺和退火后处理工艺之后，界面电介质80中的氢的峰值浓度与主体栅介电层120中的氢的峰值浓度的比率在约0.1至约10的范围内，例如约2.7。在一些实施例中，界面电介质80中的氢的峰值浓度与主体栅介电层120中的氢的峰值浓度的比率大于2.5，诸如在从大于2.5至约10的范围内。在一些实施例中，界面电介质80中的氢的峰值浓度与主体栅介电层120中的氢的峰值浓度的比率大于或等于约2.7，诸如在约2.7至约5的范围内。在一些实施例中，在实施退火工艺和退火后处理工艺之后，界面电介质80中和主体栅介电层120中的总氢量的比率在约0.1至约5的范围内，例如约1.0。
图11包括具有和不具有退火后处理工艺的器件中的示例氢浓度分布。该分布202示出了在不实施上述退火工艺和退火后处理工艺的情况下的主体栅介电层120和界面介电层80中的氢浓度分布。分布204示出了在实施上述退火工艺和退火后处理工艺之后的主体栅介电层120和界面电介质80中的氢浓度分布。
浓度值P0bulk表示分布202中的主体栅介电层120中的峰值浓度。浓度值P0IL表示分布202中的界面电介质80中的峰值浓度。浓度值Pbulk表示分布204中的主体栅介电层120中的峰值浓度。浓度值PIL表示分布204中的界面电介质80中的峰值浓度。在图11的实例中，当不实施退火工艺和退火后处理工艺时，界面电介质80和主体栅介电层120中的峰值浓度的比率(P0IL：P0bulk)为约2.5；当实施退火工艺和退火后处理工艺时，界面电介质80和主体栅介电层120中的峰值浓度的比率(PIL：Pbulk)为约2.7。当实施退火工艺和退火后处理工艺时，界面电介质80中和主体栅介电层120中的峰值浓度的比率增大约8.0％。
在图11所示的实例中，当不实施退火工艺和退火后处理工艺时，栅介电层120和界面电介质80中的总氢原子分别为约1.13×105和约9.95×104。当实施退火工艺和退火后处理工艺时，栅介电层120和界面电介质80中的总氢原子分别为约1.04×105和约9.63×104。在图11的实例中，当不实施退火工艺和退火后处理工艺时，界面电介质80中和主体栅介电层120中的总氢量的比率为约0.88，并且当实施退火工艺和退火后处理工艺时，界面电介质80中和主体栅介电层120中的总氢量的比率为约1.0。当实施退火工艺和退火后处理工艺时，界面电介质80和主体栅介电层120中的总氢量的比率增大了约13.7％。
发明人已经观察到，界面电介质80和主体栅介电层120中的总氢量或峰值浓度比率的增加可以减小由高压退火工艺引起的阈值电压偏移。
参考图8A，主体栅介电层120覆盖界面电介质80和间隔件86的侧壁。在一些实施例中，主体栅介电层120内的氢浓度在远离界面电介质80的方向上减小。因此，在间隔件86的底部附近的主体栅介电层120中的部分处(靠近外延源极/漏极区92)的氢浓度高于在第二ILD 130附近的主体栅介电层120中的部分处的氢浓度。
在一些实施例中，可以在如图8A和图8B所示的在最顶部IMD中完成导电部件之后实施退火工艺和退火后处理工艺。在另一实施例中，在如图5A和图5B所示的形成栅介电层120之后以及在形成一个或多个共形层121和导电材料122之前实施退火工艺和退火后处理工艺。在另一个实施例中，可以在如图6A和图6B所示的完成替换栅极结构之后实施退火工艺和退火后处理工艺。在另一实施例中，可以在如图7A和图7B所示的在第二ILD 130中形成导电部件之后实施退火工艺和退火后处理工艺。例如，可以在同一工艺设备中连续地实施退火工艺和退火后处理工艺。在一些实例中，可以在适当的时间单独地实施退火工艺和退火后处理工艺。
一些实施例在高压退火工艺之后提供热处理工艺以将氢保持在场效应晶体管中的沟道区与栅介电层之间的界面处，同时从栅介电层的主体部分去除氢。热处理工艺可以减小由高压退火引起的阈值电压偏移量。高压退火和热处理工艺可以在形成栅介电层之后的任何时间实施，因此不会中断现有的工艺流程。
一个实施例提供了一种方法，包括：对具有形成在有源区的沟道区上方的栅介电层的结构实施高压退火工艺，以将氢引入栅介电层和沟道区之间的界面；以及在实施高压退火工艺之后，实施退火后处理以减少栅介电层中的氢。
另一个实施例提供了一种结构。该结构包括衬底上的有源区。有源区具有沟道区。该结构还包括位于有源区的沟道区上方的栅极结构。栅极结构包括位于有源区上方的界面层、位于界面层上方的栅介电层以及位于界面层上方的栅电极层。界面层中的氢的峰值浓度与栅介电层中的氢的峰值浓度的比率在约0.1至约10的范围内。
在上述结构中，其中，所述界面层包括原生氧化物、氧化硅、氮化硅、氮氧化硅或它们的组合。
在上述结构中，其中，所述界面层具有从大于0nm至5nm的范围内的厚度。
在上述结构中，其中，所述栅介电层包括高k介电层、氧化硅层、氮氧化硅层、氮化硅层或它们的组合。
在上述结构中，其中，所述界面层中的氢的峰值浓度与所述栅介电层中的氢的峰值浓度的比率在2.7至5的范围内。
在上述结构中，其中，所述界面层中的总氢量与所述栅介电层中的总氢量的比率在0.1至5的范围内。
在上述结构中，其中，所述栅介电层在接近所述界面层的位置处的氢浓度高于远离所述界面层的位置处的氢浓度。
又一实施例提供了一种方法，包括：在衬底上形成有源区，其中有源区具有沟道区；在有源区的沟道区上方形成伪栅极结构；去除伪栅极结构以暴露有源区的沟道区；在有源区的沟道区上方形成界面层；在界面层上方形成栅介电层；实施高压退火工艺以将氢引入界面层；以及在实施高压退火工艺之后，实施退火后处理以减少栅介电层中的氢。
在上述方法中，其中，实施所述退火后处理包括：将所述结构暴露于包括氮气(N2)、氩气(Ar)、氦气(He)、氢气(H2)、氘气(D2)或它们的组合中的至少一种的环境。
在上述方法中，其中，实施所述退火后处理包括：将所述结构暴露于温度在从200℃至700℃的范围内的环境。
在上述方法中，其中，在从1毫托至5个大气压的范围内的压力处实施所述退火后处理。
在上述方法中，其中，可在同一设备中实施所述高压退火工艺和所述退火后处理。
在上述方法中，其中，也可在不同的设备中实施所述高压退火工艺和所述退火后处理。
在上述方法中，其中，实施所述高压退火工艺包括：将所述结构暴露于氢气(H2)、氘气(D2)、氮气(N2)、氩气(Ar)、氦气(He)或它们的组合的退火环境。
在上述方法中，其中：所述栅介电层和所述沟道区之间的界面包括界面层；并且在实施所述退火后处理之后，所述界面层中的氢的峰值浓度与所述栅介电层中的氢的峰值浓度的比率在从0.1至10的范围内。
在上述方法中，其中：所述栅介电层和所述沟道区之间的界面包括界面层；并且在实施所述退火后处理之后，所述界面层中的总氢量与所述栅介电层中的总氢量的比率在从0.1至5的范围内。
又一实施例提供了一种方法，包括：在有源区的沟道区上方形成栅极结构，其中栅极结构包括位于有源区上方的栅介电层；在第一压力下退火栅极结构以将氢引入到在栅介电层与沟道区之间的界面；以及在第二压力下对栅极结构实施退火后处理以减少栅介电层中的氢，其中第一压力高于第二压力。
在上述方法中，其中，所述第一压力在从5个大气压至70个大气压的范围内，并且所述第二压力在从1毫托至5个大气压的范围内。
在上述方法中，其中，所述退火后处理包括包括氮气(N2)、氩气(Ar)、氦气(He)、氢气(H2)、氘气(D2)或它们的组合的环境。
在上述方法中，其中，所述退火后处理包括包括氮气(N2)、氩气(Ar)、氦气(He)、氢气(H2)、氘气(D2)或它们的组合的环境，其中，所述环境处于从350℃至500℃的范围内的温度。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体结构，包括：
有源区，位于衬底上，所述有源区具有沟道区；
栅极结构，位于所述有源区的所述沟道区上方，其中，所述栅极结构包括：
界面层，位于所述有源区上方；
栅介电层，位于所述界面层上方；和
栅电极层，位于所述界面层上方；并且
其中，所述界面层中的氢的峰值浓度与所述栅介电层中的氢的峰值浓度的比率在0.1至10的范围内。
2.根据权利要求1所述的半导体结构，其中，所述界面层包括原生氧化物、氧化硅、氮化硅、氮氧化硅或它们的组合。
3.根据权利要求1所述的半导体结构，其中，所述界面层具有从大于0nm至5nm的范围内的厚度。
4.根据权利要求1所述的半导体结构，其中，所述栅介电层包括高k介电层、氧化硅层、氮氧化硅层、氮化硅层或它们的组合。
5.根据权利要求1所述的半导体结构，其中，所述界面层中的氢的峰值浓度与所述栅介电层中的氢的峰值浓度的比率在2.7至5的范围内。
6.根据权利要求1所述的半导体结构，其中，所述界面层中的总氢量与所述栅介电层中的总氢量的比率在0.1至5的范围内。
7.根据权利要求1所述的半导体结构，其中，所述栅介电层在接近所述界面层的位置处的氢浓度高于远离所述界面层的位置处的氢浓度。
8.一种形成半导体器件的方法，包括：
对具有界面层和位于所述界面层之上的栅介电层的结构实施高压退火工艺，以将氢引入至所述栅介电层和沟道区之间的界面，其中，所述栅介电层形成在位于有源区的沟道区上方的所述界面层之上；以及
在实施所述高压退火工艺之后，实施退火后处理以减少所述栅介电层中的氢使得所述界面层和所述栅介电层中的氢的峰值浓度比率增加。
9.根据权利要求8所述的方法，其中，实施所述退火后处理包括：
将所述结构暴露于包括氮气(N2)、氩气(Ar)、氦气(He)、氢气(H2)、氘气(D2)或它们的组合中的至少一种的环境。
10.根据权利要求8所述的方法，其中，实施所述退火后处理包括：
将所述结构暴露于温度在从200℃至700℃的范围内的环境。
11.根据权利要求8所述的方法，其中，在从1毫托至5个大气压的范围内的压力处实施所述退火后处理。
12.根据权利要求8所述的方法，其中，在同一设备中实施所述高压退火工艺和所述退火后处理。
13.根据权利要求8所述的方法，其中，在不同的设备中实施所述高压退火工艺和所述退火后处理。
14.根据权利要求8所述的方法，其中，实施所述高压退火工艺包括：
将所述结构暴露于氢气(H2)、氘气(D2)、氮气(N2)、氩气(Ar)、氦气(He)或它们的组合的退火环境。
15.根据权利要求8所述的方法，其中：
所述栅介电层和所述沟道区之间的界面包括界面层；并且
在实施所述退火后处理之后，所述界面层中的氢的峰值浓度与所述栅介电层中的氢的峰值浓度的比率在从0.1至10的范围内。
16.根据权利要求8所述的方法，其中：
所述栅介电层和所述沟道区之间的界面包括界面层；并且
在实施所述退火后处理之后，所述界面层中的总氢量与所述栅介电层中的总氢量的比率在从0.1至5的范围内。
17.一种形成半导体器件的方法，包括：
在有源区的沟道区上方形成栅极结构，其中，所述栅极结构包括位于所述有源区上方的界面层和位于所述界面层上的栅介电层；
在第一压力下退火所述栅极结构以将氢引入到所述栅介电层与所述沟道区之间的界面；以及
在第二压力下对所述栅极结构实施退火后处理以减少所述栅介电层中的氢使得所述界面层和所述栅介电层中的氢的峰值浓度比率增加，其中，所述第一压力高于所述第二压力。
18.根据权利要求17所述的方法，其中，所述第一压力在从5个大气压至70个大气压的范围内，并且所述第二压力在从1毫托至5个大气压的范围内。
19.根据权利要求17所述的方法，其中，所述退火后处理包括氮气(N2)、氩气(Ar)、氦气(He)、氢气(H2)、氘气(D2)或它们的组合的环境。
20.根据权利要求19所述的方法，其中，所述环境处于从350℃至500℃的范围内的温度。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274490B1 (en) * 2000-03-08 2001-08-14 Lucent Technologies Inc. Method of manufacturing semiconductor devices having high pressure anneal
CN102486999A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 栅极氧化层的形成方法
JP2016058658A (ja) * 2014-09-11 2016-04-21 国立研究開発法人産業技術総合研究所 炭化ケイ素半導体装置

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US20020031920A1 (en) * 1996-01-16 2002-03-14 Lyding Joseph W. Deuterium treatment of semiconductor devices
JP6505466B2 (ja) * 2015-02-24 2019-04-24 株式会社東芝 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274490B1 (en) * 2000-03-08 2001-08-14 Lucent Technologies Inc. Method of manufacturing semiconductor devices having high pressure anneal
CN102486999A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 栅极氧化层的形成方法
JP2016058658A (ja) * 2014-09-11 2016-04-21 国立研究開発法人産業技術総合研究所 炭化ケイ素半導体装置

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