CN109585309A - 半导体器件和方法 - Google Patents

半导体器件和方法 Download PDF

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Publication number
CN109585309A
CN109585309A CN201810979949.9A CN201810979949A CN109585309A CN 109585309 A CN109585309 A CN 109585309A CN 201810979949 A CN201810979949 A CN 201810979949A CN 109585309 A CN109585309 A CN 109585309A
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Prior art keywords
dielectric layer
shielding part
conductive shielding
coil
integrated circuit
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CN201810979949.9A
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CN109585309B (zh
Inventor
黄子松
余振华
郭鸿毅
蔡豪益
曾明鸿
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例公开了半导体器件及其形成方法。在一个实施例中，一种半导体器件包括：在第一介电层上的导电屏蔽件；在第一介电层和导电屏蔽件上的第二介电层，第一和第二介电层围绕导电屏蔽件，第二介电层包括：沿着导电屏蔽件的外围设置的第一部分；延伸穿过导电屏蔽件的中心区域的第二部分；以及延伸穿过导电屏蔽件的通道区的第三部分，第三部分将第一部分连接至第二部分；在第二介电层上的线圈，线圈设置在导电屏蔽件上方；在第二介电层上的集成电路管芯，集成电路管芯设置在线圈的外部；以及围绕线圈和集成电路管芯的密封剂，密封剂、集成电路管芯和线圈的顶表面是平齐的。

Description

半导体器件和方法
技术领域
本发明的实施例总体涉及半导体领域，更具体地，涉及半导体器件及其形成方法。
背景技术
作为实例，半导体器件用于各种电子应用，例如个人计算机、手机、数码相机和其他电子设备。通常通过在半导体衬底上方顺序地沉积绝缘或介电层、导电层和半导体材料层以及使用光刻对衬底和/或各种材料层进行图案化或处理以在衬底上形成电路组件和元件并形成集成电路来制造半导体器件。通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割各个管芯。例如，然后将单独的管芯分开封装、在多芯片模块中封装或者在其他类型的封装件中封装。
当在电子设备中使用半导体器件时，诸如电池的电源通常连接管芯以提供电源并且可以通过无线充电系统来充电。在无线充电系统中，电磁场由充电站产生，并且能量被传送到电子设备。电子设备中的感应线圈从电磁场中获取电源并将其转换回电流以对电池进行充电。
发明内容
根据本发明的一个方面，提供了一种形成半导体器件的方法，包括：在第一介电层上沉积导电层；蚀刻所述导电层以在所述第一介电层上形成导电屏蔽件，所述导电屏蔽件包括开口和在所述开口与所述导电屏蔽件的外围之间延伸的第一通道区域；在所述导电屏蔽件上形成第二介电层；在所述第二介电层上形成线圈；将集成电路管芯放置在所述第二介电层上，所述集成电路管芯设置在所述线圈的外部；用密封剂密封所述线圈和所述集成电路管芯；以及在所述线圈、所述集成电路管芯和所述密封剂上形成再分布结构。
根据本发明的另一个方面，提供了一种形成半导体器件的方法，包括：沉积第一介电层；在所述第一介电层上形成导电屏蔽件，所述导电屏蔽件包括开口和在所述开口与所述导电屏蔽件的外围之间延伸的第一通道区域；在所述导电屏蔽件和所述第一介电层上沉积第二介电层；在所述第二介电层上形成线圈，所述第二介电层在所述线圈与所述导电屏蔽件之间连续地延伸；以及用密封剂密封所述线圈，所述密封剂的顶表面和所述线圈的顶表面是平齐的。
根据本发明的又一个方面，提供了一种半导体器件，包括：导电屏蔽件，位于第一介电层上；第二介电层，位于所述第一介电层和所述导电屏蔽件上，所述第一介电层和所述第二介电层围绕所述导电屏蔽件，所述第二介电层包括：第一部分，沿着所述导电屏蔽件的外围设置；第二部分，延伸穿过所述导电屏蔽件的中心区域；和第三部分，延伸穿过所述导电屏蔽件的通道区域，所述第三部分将所述第一部分连接至所述第二部分；线圈，位于所述第二介电层上，所述线圈设置在所述导电屏蔽件上方；集成电路管芯，位于所述第二介电层上，所述集成电路管芯设置在所述线圈的外部；以及密封剂，围绕所述线圈和所述集成电路管芯，所述密封剂、所述集成电路管芯和所述线圈的顶表面是平齐的。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据一些实施例的无线充电系统的框图。
图2是根据一些实施例的接收器的立体图。
图3至图18是根据一些实施例的用于形成接收器的工艺期间的中间步骤的各种视图。
图19A至图19D示出了根据一些其他实施例的顶视图中的导电屏蔽件。
具体实施方式
以下公开内容提供了用于实现本发明的不同特征的许多不同实施例或实例。下面描述了组件和布置的特定实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身并不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，在本文中可以使用诸如“在...之下”、“在...下面”、“下部”、“在...之上”、“上部”等的空间相对术语来描述如图中所示的一个元件或部件与另一个(另一些)元件或部件的关系。除了图中所示的取向之外，空间相对术语旨在包含在使用或操作中的器件的不同取向。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在本文中使用的空间相对描述符同样可以做出相应地解释。
根据一些实施例，导电屏蔽件形成在背侧屏蔽结构中，并且接收线圈(例如，天线)形成在背侧屏蔽结构上。导电屏蔽件具有开口和槽或通道区域，其中，通道区域将开口连接到导电屏蔽件的外围或边缘。由于通道区域和开口的配置，在导电屏蔽件上引生的涡电流可以引生指向接收线圈的次级磁场。这可以增加接收线圈与发射线圈之间的互感，这可以增加接收线圈与发射线圈之间的传输效率。
图1是无线充电系统50的框图。无线充电系统50包括电池52、电源54、发射器56和接收器58。电池52利用无线充电系统50进行充电，无线充电系统50可以是电磁感应型非接触式充电装置，并且可以是个人计算机、手机、平板电脑、数码相机或其他电子设备的部分。
电源54向发射器56提供AC信号。发射器56包括发射电路60，发射电路60接收AC信号并将其提供给发射线圈62。发射线圈62由AC信号产生磁场B1。当接收器58位于预定位置处时，接收线圈64由磁场B1产生AC信号。将AC信号提供给集成电路管芯66。在一些实施例中，集成电路管芯66是AC/DC转换器管芯，AC/DC转换器管芯从接收线圈64接收AC信号，并将AC信号转换为DC信号。DC信号用于给电池52进行充电。
虽然本文在使用非接触式电源传输来对电池52进行充电的环境中描述了实施例，但是应该理解，实施例可以具有其他应用。在一些实施例中，所接收的AC信号用于驱动相应产品的电路。实施例还可以用于除了非接触式电源传输之外的应用。在一些实施例中，所接收的AC信号是无线传输，并且集成电路管芯66可以是通信管芯，例如蓝牙低功耗(BLE)管芯。在这样的实施例中，集成电路管芯66可以连接到外部系统，例如处理器、微控制器等。相应地，接收线圈64也可以被称为天线。
图2是接收器58的立体图，并且结合图1进行描述。根据一些实施例，接收器58还包括其中具有开口70的导电屏蔽件68。开口70和接收线圈64的中心对准，使得大部分磁场B1通过开口70到达接收线圈64的中心。开口70通过通道72连接到导电屏蔽件68的外围。导电屏蔽件68有助于束形(shape)磁场B1的磁通量。具体地，磁场B1在导电屏蔽件68上引生涡流I1。涡流I1的流动方向根据右手定则确定。涡流I1围绕开口70的边缘，沿着通道72的边缘并围绕导电屏蔽件68的外围流动。涡流I1沿着与磁场B1相同的方向引生辅助磁场B2。因此接收线圈64上的磁场强度增加，从而提高了无线充电系统50的充电效率。
在一些实施例中，接收器58还包括伪半导体结构74。例如，伪半导体结构74是可以帮助或减少载体衬底100的晶圆翘曲控制的支撑结构。伪半导体结构74可以是块状半导体，例如硅等。
图3至图18是根据一些实施例的用于形成接收器58的工艺期间的中间步骤的各种视图。图3至图18是截面图。接收器58可以被称为集成扇出(InFO)封装件。
在图3中，示出了处于工艺的中间阶段的接收器58，接收器58包括形成在载体衬底100上的释放层102。示出了用于形成接收器58的封装区域600。尽管仅示出了一个封装区域，但是可以形成很多封装区域。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，使得可以同时在载体衬底100上形成多个封装件。释放层102可以由基于聚合物的材料形成，释放层102可以与载体衬底100一起从将在随后的步骤中形成的覆盖结构处去除。在一些实施例中，释放层102是基于环氧树脂的热释放材料，该热释放材料在加热时丧失其粘合性，例如光热转换(LTHC)释放涂层。在其他实施例中，释放层102可以是紫外(UV)胶，该UV胶在暴露于UV光时丧失其粘合性。释放层102可以以液体分配且固化，可以是层压到载体衬底100上的层压膜，或者可以是类似的。释放层102的顶表面可以是水平的并且可以具有高度的共面性。
在图4中，介电层104形成在释放层102上。介电层104的底表面可以与释放层102的顶表面接触。在一些实施例中，介电层104由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。在其他实施例中，介电层104可由以下物质形成：氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)；等等来形成。介电层104可以通过诸如旋涂、化学汽相沉积(CVD)、层压等或上述的组合的任何可接受的沉积工艺形成。
在图5中，在介电层104上方形成导电层106。在一些实施例中，导电层106是金属层，其可以是单层导电材料或包括由不同导电材料形成的多个子层的复合层。在一些实施例中，导电层106包括钛层和钛层上方的铜层。钛层可以比铜层薄；在一个实施例中，钛层的厚度约为0.1μm，并且铜层的厚度约为0.5μm。可以使用诸如PVD等来形成导电层106。导电层106可以类似于晶种层，并且可以以与晶种层类似的方式来形成。
在图6中，在导电层106上形成掩模108并将其图案化。用于掩模108的材料可以通过旋涂等形成，并且可以暴露于光以进行图案化。用于掩模108的材料可以是光刻胶，例如单层光刻胶、三层光刻胶等。图案化形成穿过掩模108的材料的开口以暴露导电层106。掩模108的图案对应于导电屏蔽件68的图案。例如，掩模108的开口可以对应于每个导电屏蔽件68的开口70和通道72。
在图7中，使用掩模108作为蚀刻掩模来蚀刻导电层106。导电层106的位于掩模108下面的剩余部分形成具有开口70和通道72(在截面图中未示出)的导电屏蔽件68。导电层106可以通过可接受的蚀刻工艺来蚀刻，例如通过湿法蚀刻或干法蚀刻。蚀刻时间取决于蚀刻工艺。在一个实施例中，蚀刻工艺是两步湿法蚀刻工艺，其中，第一蚀刻步骤用于用稀磷酸(H3PO4)来蚀刻导电层106的铜层，并且第二蚀刻步骤用于用氢氟酸(HF)来蚀刻导电层106的钛层。第一蚀刻步骤可以实施从约20秒至约40秒的时间段，并且第二蚀刻步骤可以实施从约20秒至约60秒的时间段。这种两步湿法蚀刻工艺可以允许导电层106(其可以非常薄)被蚀刻而没有实质性的损坏或剥落。
在图8中，掩模108被去除。在掩模108是光刻胶的实施例中，可以通过可接受的灰化或剥离工艺(例如，使用氧等离子体等)来去除掩模108。在去除掩模108之后，导电屏蔽件68保留在介电层104上。值得注意的是，在导电屏蔽层68上不形成其他导电材料。例如，在形成导电屏蔽件68之后以及在去除掩模108之前可以不实施沉积或镀敷工艺。因此，导电屏蔽件68很薄；在一些实施例中，导电屏蔽件68的厚度约为0.5μm。较薄的导电屏蔽件68改善了发射线圈62与接收线圈64之间的互感。发射线圈62与接收线圈64之间的较高互感可以在对电池52进行充电时提高无线电源传输的效率。
在图9中，在导电屏蔽件68和介电层104上形成介电层110。在一些实施例中，介电层110由聚合物形成，聚合物可以是可以使用光刻掩模来图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中，介电层110由以下材料形成：氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等等来形成。介电层110可以通过旋涂、层压、CVD等或上述的组合形成。可以将介电层104和110以及导电屏蔽件68称为背侧屏蔽结构112。在形成之后，介电层104和110围绕导电屏蔽件68。介电层110的各部分设置在导电屏蔽件68的外围周围。此外，介电层110的各部分延伸穿过导电屏蔽件68的中心区域(例如，开口70)和通道区域(例如，通道72)。
介电层110的厚度被选择为使得导电屏蔽件68距离接收线圈64(未示出；随后形成在介电层110上)特定的距离。接收线圈64与导电屏蔽件68之间的距离可以取决于应用(例如，无线充电系统50的工作频率)。介电层110比导电屏蔽件68厚得多；例如，介电层110可以比导电屏蔽件68厚若干(例如，3至4)个数量级。在一个实施例中，介电层110形成为使得介电层110的位于导电屏蔽件68上方的各部分具有从约5μm至约10μm的厚度。
在图10中，通过在介电层110上形成通孔114来形成接收线圈64。介电层104和110围绕导电屏蔽件68并且使其与通孔114间隔开，使得导电屏蔽件68在操作期间与通孔114磁耦合但是与通孔114电隔离。因此，导电屏蔽件68磁耦合至通孔114，但是未电连接至通孔114。介电层110在接收线圈64与导电屏蔽件68之间连续地延伸。
作为形成通孔114的实例，在背侧屏蔽结构112(例如，介电层110)上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。可以使用诸如PVD等来形成晶种层。光刻胶在晶种层上形成并且图案化。光刻胶可以通过旋涂等形成，并且可以暴露于光下进行图案化。光刻胶的图案对应于接收线圈64。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀法形成导电材料。导电材料可以包括金属，类似于铜、钛、钨、铝等。去除光刻胶和晶种层的其上未形成有导电材料的部分。可以通过可接受的灰化或剥离工艺来去除光刻胶，例如使用氧等离子体等。一旦光刻胶被去除，例如通过使用可接受的蚀刻工艺(例如，通过湿法或干法蚀刻)去除晶种层的暴露部分。晶种层和导电材料的剩余部分形成通孔114。通孔114可以连接以形成连续导线(例如，参见图2)，从而形成接收线圈64。
在图11中，集成电路管芯66通过粘合剂116粘附到介电层110。如上所述，集成电路管芯66可以是电源管芯(例如，AC/DC转换器管芯)、或者通信管芯(例如，BLE管芯)。尽管仅示出了一个集成电路管芯66，但是应该理解，可能存在多于一个的集成电路管芯66。例如，在接收器58对电池52进行充电的实施例中，可能存在用于AC/DC转换的第一集成电路管芯66(例如，电源管芯)以及用于调节电池52的充电的第二集成电路管芯66(例如，逻辑管芯)。在一些实施例中，集成电路管芯66可以包括电源功能和逻辑功能。
在集成电路管芯66粘附至介电层110之前，可以根据可应用的制造工艺处理集成电路管芯66以在集成电路管芯66中形成集成电路。例如，集成电路管芯66可以包括诸如掺杂或未掺杂的硅的半导体衬底118、或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底118可以包括其他半导体材料，例如锗；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟的化合物半导体；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的合金半导体；或上述的组合。也可以使用其他衬底，例如多层或渐变衬底。半导体衬底118可以是形成集成电路管芯66的晶圆的部分。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上，并且可以通过由诸如半导体衬底118上的一个或多个介电层中的金属化图案形成的互连结构120进行互连以形成集成电路。互连结构120可以通过诸如双镶嵌工艺形成。
集成电路管芯66还包括诸如铝焊盘的焊盘122，从而形成至焊盘122的外部连接。焊盘122位于可以被称为集成电路管芯66的有源侧(例如，图中朝上的一侧)上，并且可以形成在互连结构120的顶部介电层中。钝化膜124位于集成电路管芯66上以及焊盘122的部分上。开口穿过钝化膜124到达焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中，并且机械地以及电连接至相应的一个焊盘122。管芯连接件126可以通过诸如镀法等形成。管芯连接件126电连接集成电路管芯66的相应的集成电路。在一些实施例中，管芯连接件126可以具有用于管芯测试的焊帽。
介电材料128位于集成电路管芯66的有源侧上，例如，位于钝化膜124和管芯连接件126上。介电材料128横向地封装管芯连接件126，并且介电材料128横向地与集成电路管芯66相连。介电材料128可以最初形成为掩埋或覆盖管芯连接件126；当管芯连接件126被掩埋时，介电材料128的顶表面可以具有不平坦的形貌(未示出)。介电材料128可以是诸如PBO、聚酰亚胺、BCB等的聚合物；诸如氮化硅等的氮化物；诸如氧化硅、PSG、BSG、BPSG等的氧化物；类似物或上述的组合，并且可以通过诸如旋涂、层压、CVD等形成。
粘合剂116位于集成电路管芯66的背侧(例如，图中朝下的一侧)上，并且将集成电路管芯66粘附至背侧屏蔽结构112，例如介电层110。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附着膜(DAF)等。粘合剂116可以被施加至集成电路管芯66的背侧，例如，被施加至形成有集成电路管芯66的晶圆的背侧，或者可以被施加至载体衬底100的表面上方。集成电路管芯66可以通过诸如锯切或切割从晶圆分离，并且使用诸如取放(pick-and-place)工具通过粘合剂116粘附到介电层110。
此外，伪半导体结构74也可以通过粘合剂116粘附到介电层110。粘合剂116可以被施加至伪半导体结构74的背侧。伪半导体结构74设置在导电屏蔽件68的开口70的上方。伪半导体结构74可以使用诸如取放工具通过粘合剂116粘附到介电层110。
在图12中，密封剂130形成在各种部件上。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、传递模塑等来施加。密封剂130可以形成在载体衬底100上方，使得集成电路管芯66的管芯连接件126和/或通孔114被掩埋或覆盖。然后固化密封剂130。
在图13中，对密封剂130实施平坦化工艺以暴露通孔114和管芯连接件126。平坦化工艺还可以研磨介电材料128和伪半导体结构74。在平坦化工艺之后，伪半导体结构74、通孔114、管芯连接件126、介电材料128和密封剂130的顶表面共面。平坦化工艺可以是诸如化学机械抛光(CMP)、研磨工艺等。在一些实施例中，例如，如果通孔114和管芯连接件126已经暴露，则可以省略平坦化。
在图14中，前侧再分布结构132形成在密封剂130、通孔114和管芯连接件126上。前侧再分布结构132包括多个介电层132A、金属化图案132B和通孔132C。例如，前侧再分布结构132可以被图案化为通过各个介电层132A彼此分离的多个离散的金属化图案132B。
在一些实施例中，介电层132A由聚合物形成，聚合物可以是可以使用光刻掩模来图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中，由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG的氧化物；等来形成介电层132A。介电层132A可以通过旋涂、层压、CVD等或上述的组合形成。
在形成之后，介电层132A被图案化以暴露下面的导电部件。底部介电层132A被图案化以暴露通孔114的部分和管芯连接件126的部分，并且中间介电层被图案化以暴露下面的金属化图案132B的部分。图案化可以通过可接受的工艺进行，例如通过当介电层是光敏材料时将介电层132A暴露于光下、或者通过使用诸如各向异性蚀刻来蚀刻。如果介电层132A是光敏材料，则可以在曝光之后对介电层132A进行显影。
具有通孔132C的金属化图案132B形成在每个介电层132A上。晶种层(未示出)形成在每个介电层132A上方以及穿过各个介电层132A的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和钛层上方的铜层。晶种层可以使用诸如PVD等的沉积工艺来形成。然后在晶种层上形成光刻胶并将其图案化。光刻胶可以通过旋涂等形成，并且可以暴露于光下进行图案化。光刻胶的图案对应于金属化图案132B。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中和晶种层的暴露部分上。导电材料可以通过镀法形成，例如电镀或化学镀等。导电材料可以包括金属或金属合金，例如铜、钛、钨、铝等或上述的组合。然后，去除光刻胶和晶种层的其上未形成有导电材料的部分。可以通过可接受的灰化或剥离工艺来去除光刻胶，例如，使用氧等离子体等。一旦光刻胶被去除，例如通过使用可接受的蚀刻工艺(例如，通过湿法或干法蚀刻)去除晶种层的暴露部分。晶种层和导电材料的剩余部分形成用于前侧再分布结构132的一个金属化层的金属化图案132B和通孔132C。
前侧再分布结构132被示出为一个实例。可以在前侧再分布结构132中形成比所示更多或更少的介电层132A和金属化图案132B。本领域普通技术人员将容易地理解哪些步骤和工艺将被省略或重复以形成更多或更少的介电层132A、金属化图案132B和通孔132C。
此外，导电连接器136形成为延伸至前侧再分布结构132的顶部介电层132A中。前侧再分布结构132的顶部介电层132A可以被图案化以暴露金属化图案132B的各部分。在一些实施例中，凸块下金属(UBM)(未示出)可以形成在开口中，延伸到顶部介电层132A中。导电连接件136形成在开口中。导电连接器136可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。导电连接件136可以由金属或金属合金(例如焊料、铜、铝、金、镍、银、钯、锡等或上述的组合)形成。在一些实施例中，导电连接件136通过最初通过诸如蒸发、电镀、印刷、焊料转移、置球等这样的常用方法形成焊料层而形成。一旦在结构上形成了焊料层，就可以实施回流以便将材料定形为所需的凸块形状。在另一实施例中，导电连接件136是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如，铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。导电连接件136电连接至前侧再分布结构132的金属化图案132B。
在图15中，外部器件138附接至前侧再分布结构132。在一些实施例中，外部器件138是诸如集成无源器件(IPD)的表面贴装器件(SMD)。在这样的实施例中，外部器件138可以包括具有形成在其中的一个或多个无源器件的主结构140。主结构140可以是半导体衬底和/或密封剂。在包括半导体衬底的实施例中，衬底可以是诸如掺杂或未掺杂的硅的半导体衬底、或SOI衬底的有源层。无源器件可以包括电容器、电阻器、电感器等或上述的组合。无源器件可以形成在主结构140中和/或上，并且可以通过由诸如主结构上的一个或多个介电层中的金属化图案形成的互连结构互连以形成外部器件138。管芯连接件142形成在主结构140上并且连接至主结构140，形成至管芯连接件142的外部连接。外部器件138的管芯连接件142通过导电连接件136附接至前侧再分布结构132的金属化图案132B。导电连接器136被回流，由此在外部器件138和前侧再分布结构132之间形成焊点。外部器件138电连接至集成电路管芯66。
此外，铁氧体材料144通过诸如粘合剂146附接到前侧再分布结构132。铁氧体材料144可以由锰锌、镍锌等形成。铁氧体材料144在高频下具有相对低的损耗，并且可以帮助增大接收线圈64的互感。铁氧体材料144直接位于接收线圈64上方(例如，重叠)。在一些实施例中，铁氧体材料144的边缘基本上与接收线圈64的边缘共端点(co-terminus)。在一些实施例中，铁氧体材料114比接收线圈64宽。粘合剂146可以类似于粘合剂116。
在图16中，实施载体衬底去结合(debonding)以将载体衬底100从背侧屏蔽结构112处(例如，介电层110)分离(剥离)。根据一些实施例，去结合包括将诸如激光或UV光的光投射在释放层102上，使得释放层102在光的热量下分解从而可以移除载体衬底100。
在图17中，通过沿着划线区域(例如，在相邻的封装区域之间)分割来实施分割工艺。在一些实施例中，分割工艺包括锯切工艺、激光工艺或上述的组合。分割工艺从相邻的封装区域(未示出)来分割封装区域600。示出了在分割之后得到的接收器58，该接收器58可以来自封装区域600。
图18是示出接收器58的一些部件的自顶向下的剖视图。沿着图18中包含线A-A的平面示出图3至图17的截面图。集成电路管芯66设置在接收线圈64的外部。通孔114是形成接收线圈64的环形或螺旋形的单个连续金属材料。具体地说，接收线圈64具有在平面(例如，介电层104的顶表面)上的一系列导电段(例如，通孔114)，这些导电段以距固定的中心点不断增大距离的方式围绕在该点周围。螺旋从接收线圈64的第一端起始，并且终止于接收线圈64的第二端处。接收线圈64通过前侧再分布结构132的一些金属化图案132B电连接至集成电路管芯66。具体地说，接收线圈64的第一和第二端通过金属化图案132B连接至集成电路管芯66。伪半导体结构74设置在接收线圈64的中央。
图19A至图19D示出了根据一些其他实施例的顶视图中的导电屏蔽件68。在图3至图18的实施例中，导电屏蔽件68具有圆形开口70和一个通道72。在图19A至图19D的实施例中，导电屏蔽件68具有针对开口70的不同形状和不同数量的通道72。在图19A中，导电屏蔽件68具有两个通道72。在图19B中，导电屏蔽件68具有四个通道72。在图19C中，导电屏蔽件68具有八个通道72。在图19D中，开口70是正方形。应该理解的是，图19A至图19D的实施例仅仅是实例，并且导电屏蔽件68可以具有任何形状的开口70和/或任何数量的通道72。
实施例可以实现优点。在导电屏蔽件68中形成开口70可以对发射线圈62和接收线圈64之间的磁场的磁通量束形，由此提高无线电源传输效率。形成较薄的导电屏蔽件68可以增加发射线圈62和接收线圈64之间的互感，从而进一步提高无线充电效率。在一个实施例中，将导电屏蔽件68的厚度减小至约0.5μm可以将无线电源传输效率提高多达2％。
其他部件和工艺也可以包括在内。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。例如，测试结构可以包括形成在允许测试3D封装件或3DIC、使用探针和/或探针卡等的再分布层中或衬底上的测试焊盘。可以对中间结构以及最终结构实施验证测试。此外，本文公开的结构和方法可以与包含已知良好管芯的中间验证的测试方法结合使用，以提高产量并且降低成本。
在一个实施例中，一种方法包括：在第一介电层上沉积导电层；蚀刻导电层以在第一介电层上形成导电屏蔽件，导电屏蔽件包括开口和在开口与导电屏蔽件的外围之间延伸的第一通道区域；在导电屏蔽件上形成第二介电层；在第二介电层上形成线圈；将集成电路管芯放置在第二介电层上，集成电路管芯设置在线圈的外部；用密封剂密封线圈和集成电路管芯；以及在线圈、集成电路管芯和密封剂上形成再分布结构。
在一些实施例中，沉积导电层包括：在第一介电层上沉积钛层；以及在钛层上沉积铜层。在一些实施例中，蚀刻导电层包括：用稀磷酸(H3PO4)蚀刻铜层约20秒至约40秒的第一时间段；以及用氢氟酸(HF)蚀刻钛层约20秒至约60秒的第二时间段。在一些实施例中，在导电屏蔽件上形成第二介电层之前，不在导电屏蔽件上形成其他导电材料。在一些实施例中，该方法还包括：在直接位于导电屏蔽件的开口上方的第二介电层上放置伪半导体结构。在一些实施例中，该方法还包括：平坦化密封剂，使线圈、集成电路管芯和密封剂的顶表面平齐。在一些实施例中，在线圈上形成再分布结构包括：在再分布结构中形成金属化图案，金属化图案将集成电路管芯电连接至线圈的第一端和线圈的第二端。在一些实施例中，该方法还包括：将铁氧体材料附接至再分布结构，铁氧体材料直接位于线圈上方。在一些实施例中，该方法还包括：将外部器件附接至再分布结构，外部器件电连接至集成电路管芯。
在一个实施例中，一种方法包括：沉积第一介电层；在第一介电层上形成导电屏蔽件，导电屏蔽件包括开口和在开口与导电屏蔽件的外围之间延伸的第一通道区域；在导电屏蔽件和第一介电层上沉积第二介电层；在第二介电层上形成线圈，第二介电层在线圈与导电屏蔽件之间连续地延伸；以及用密封剂密封线圈，密封剂和线圈的顶表面是水平的。
在一些实施例中，该方法还包括：将集成电路管芯放置在第二介电层上，集成电路管芯设置在线圈的外部，密封剂将线圈与集成电路管芯分开；其中，线圈是连续铜螺旋件，连续铜螺旋件的第一端和第二端电连接至集成电路管芯。
在一个实施例中，一种器件包括：在第一介电层上的导电屏蔽件；在第一介电层和导电屏蔽件上的第二介电层，第一和第二介电层围绕导电屏蔽件，第二介电层包括：沿着导电屏蔽件的外围设置的第一部分；延伸穿过导电屏蔽件的中心区域的第二部分；以及延伸穿过导电屏蔽件的通道区域的第三部分，第三部分将第一部分连接至第二部分；在第二介电层上的线圈，线圈设置在导电屏蔽件上方；在第二介电层上的集成电路管芯，集成电路管芯设置在线圈的外部；以及围绕线圈和集成电路管芯的密封剂，密封剂、集成电路管芯和线圈的顶表面是水平的。
在一些实施例中，集成电路管芯是AC/DC转换器管芯，并且集成电路管芯连接至电池。在一些实施例中，集成电路管芯是通信管芯，并且集成电路管芯连接至外部系统。在一些实施例中，该器件还包括：设置在线圈中心的伪半导体结构。在一些实施例中，导电屏蔽件和线圈的中心对齐，使得伪半导体结构设置在第二介电层的第二部分上方。在一些实施例中，第二介电层的第三部分是第二介电层的多个第三部分中的一个，第二介电层的每个第三部分均延伸穿过导电屏蔽件并且将第一部分连接至第二部分。在一些实施例中，第二介电层的第二部分在顶视图中是圆形的。在一些实施例中，第二介电层的第二部分在顶视图中是正方形的。在一些实施例中，第二介电层将线圈与导电屏蔽件间隔开，使得导电屏蔽件在操作期间磁耦合至线圈并且与线圈电隔离。
以上论述了若干实施例的特征，使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
在第一介电层上沉积导电层；
蚀刻所述导电层以在所述第一介电层上形成导电屏蔽件，所述导电屏蔽件包括开口和在所述开口与所述导电屏蔽件的外围之间延伸的第一通道区域；
在所述导电屏蔽件上形成第二介电层；
在所述第二介电层上形成线圈；
将集成电路管芯放置在所述第二介电层上，所述集成电路管芯设置在所述线圈的外部；
用密封剂密封所述线圈和所述集成电路管芯；以及
在所述线圈、所述集成电路管芯和所述密封剂上形成再分布结构。
2.根据权利要求1所述的方法，其中，沉积所述导电层包括：
在所述第一介电层上沉积钛层；以及
在所述钛层上沉积铜层。
3.根据权利要求2所述的方法，其中，蚀刻所述导电层包括：
用稀磷酸(H3PO4)蚀刻所述铜层约20秒至约40秒的第一时间段；以及
用氢氟酸(HF)蚀刻所述钛层约20秒至约60秒的第二时间段。
4.根据权利要求1所述的方法，其中，在所述导电屏蔽件上形成所述第二介电层之前，没有在所述导电屏蔽件上形成其他导电材料。
5.根据权利要求1所述的方法，还包括：
在直接位于所述导电屏蔽件的开口上方的所述第二介电层上放置伪半导体结构。
6.一种形成半导体器件的方法，包括：
沉积第一介电层；
在所述第一介电层上形成导电屏蔽件，所述导电屏蔽件包括开口和在所述开口与所述导电屏蔽件的外围之间延伸的第一通道区域；
在所述导电屏蔽件和所述第一介电层上沉积第二介电层；
在所述第二介电层上形成线圈，所述第二介电层在所述线圈与所述导电屏蔽件之间连续地延伸；以及
用密封剂密封所述线圈，所述密封剂的顶表面和所述线圈的顶表面是平齐的。
7.根据权利要求6所述的方法，还包括：
将集成电路管芯放置在所述第二介电层上，所述集成电路管芯设置在所述线圈的外部，所述密封剂将所述线圈与所述集成电路管芯分开；
其中，所述线圈是连续铜螺旋件，所述连续铜螺旋件的第一端和第二端电连接至所述集成电路管芯。
8.一种半导体器件，包括：
导电屏蔽件，位于第一介电层上；
第二介电层，位于所述第一介电层和所述导电屏蔽件上，所述第一介电层和所述第二介电层围绕所述导电屏蔽件，所述第二介电层包括：
第一部分，沿着所述导电屏蔽件的外围设置；
第二部分，延伸穿过所述导电屏蔽件的中心区域；和
第三部分，延伸穿过所述导电屏蔽件的通道区域，所述第三部分将所述第一部分连接至所述第二部分；
线圈，位于所述第二介电层上，所述线圈设置在所述导电屏蔽件上方；
集成电路管芯，位于所述第二介电层上，所述集成电路管芯设置在所述线圈的外部；以及
密封剂，围绕所述线圈和所述集成电路管芯，所述密封剂、所述集成电路管芯和所述线圈的顶表面是平齐的。
9.根据权利要求8所述的器件，其中，所述集成电路管芯是AC/DC转换器管芯，并且所述集成电路管芯连接至电池。
10.根据权利要求8所述的器件，其中，所述集成电路管芯是通信管芯，并且所述集成电路管芯连接至外部系统。
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US20210358870A1 (en) 2021-11-18
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US20200006259A1 (en) 2020-01-02
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US11848288B2 (en) 2023-12-19
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