CN109558158A - The device and method of FPGA and DSP program is updated based on network - Google Patents
The device and method of FPGA and DSP program is updated based on network Download PDFInfo
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- CN109558158A CN109558158A CN201910093753.4A CN201910093753A CN109558158A CN 109558158 A CN109558158 A CN 109558158A CN 201910093753 A CN201910093753 A CN 201910093753A CN 109558158 A CN109558158 A CN 109558158A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
Abstract
The device and method of FPGA and DSP program is updated based on network, including field programmable gate array chip and DSP chip, first flash storage of the field programmable gate array chip configured with storage FPGA more new procedures, field programmable gate array chip is connected to the end FMC HPC pin by LVDS interface, and field programmable gate array chip is connected with four-way SFP interface by GTH interface；DSP chip is connected with PHY physical chip, second flash storage of the DSP chip configured with storage DSP more new procedures by SGM interface；Field programmable gate array chip is connected with CPLD Complex Programmable Logic Devices by GPIO interface, and CPLD Complex Programmable Logic Devices connects DSP chip by EMIF interface.It realizes that device product is safeguarded in user strange land and program updates, reduces special equipment and rely on.
Description
Technical field
The present embodiments relate to it is a kind of based on network update FPGA and DSP program device and method, more particularly to
A kind of device and method of the programming device program Solidification on hardware platform and update.
Background technique
Programmable logic device originates from the 1970s, being developed on the basis of specific integrated circuit (ASIC)
A kind of New kind logical component come, is the main hardware platform of current Design of Digital System, main feature be exactly completely by with
Family is configured and is programmed by software, to complete certain specific function, and can be repeatedly erasable.It is modifying and is upgrading
It when PLD, is not required to extraly change PCB circuit board, only modification on computers and more new procedures, becomes hardware design work
Software development work, shortens the period of system design, improves the flexibility of realization and reduce costs, therefore obtains wide
The favor of big Hardware Engineer, forms huge PLD industry size.
It in the prior art, need to be flat to hardware to realize in device context with the emulator of emulator and DSP by FPGA
Programming device (FPGA and DSP) on platform carries out program Solidification and update, carries out program maintenance update to system equipment in this way
When require developer must in device context, and must use dedicated emulator, limit the work of test maintaining personnel
Environment, and the course of work is complex.
Summary of the invention
For this purpose, the embodiment of the present invention provides a kind of device and method for updating FPGA and DSP program based on network, solve to use
Family to the updating maintenance of FPGA in equipment and DSP (TI multicore TMS320C66XX series) program and subtracts in remote (strange land)
Few dependence to special equipment (emulator).
To achieve the goals above, embodiments of the present invention provide the following technical solutions: based on network update FPGA and
The device of DSP program, the field programmable gate array chip including Virtex7 series or Kintex7 series, is based on KeyStone
The DSP chip of more core architectures, the field programmable gate array chip and DSP chip it
Between connected by SRIO serial bus interface or EMIF interface；
The field programmable gate array chip is configured with QDR static random access memory and use for storing data
In the first flash storage of storage FPGA more new procedures, field programmable gate array chip is connected to FMC by LVDS interface
HPC pin is held, field programmable gate array chip is connected with four-way SFP interface by GTH HSSI High-Speed Serial Interface；
The DSP chip is connected with PHY physical chip, digital signal processor core by SGM interface
Piece is configured with DDR3 memory for storing data and the second flash storage for storing DSP more new procedures；
Field programmable gate array chip is connected with CPLD Complex Programmable Logic Devices, the CPLD by GPIO interface
Complex Programmable Logic Devices connects the DSP chip by EMIF interface.
As the preferred embodiment for the device for updating FPGA and DSP program based on network, the PHY physical chip is equipped with two
A, a PHY physical chip is connected with RJ45 interface, another PHY physical chip is connected with ZD connector XP3, institute
It states ZD connector XP3 and the DSP chip is connected by PCIE interface.
It further include that ZD connector XP1 and ZD connect as the preferred embodiment for the device for updating FPGA and DSP program based on network
Device XP2 is met, the ZD connector XP1 connects the field programmable gate through GTH HSSI High-Speed Serial Interface respectively with ZD connector XP2
Array chip.
As based on network update FPGA and DSP program device preferred embodiment, further include CPCI connector J1 and
CPCI connector J5, the CPCI connector J1 are connected to DC-DC electricity by the corresponding DC5V supply input of standard cpci bus
Source module, the CPCI connector J5 connect the field programmable gate array chip with LVDS interface through GPIO interface.
As the preferred embodiment for the device for updating FPGA and DSP program based on network, FPGA and DSP journey is updated based on network
The device of sequence is connected with host computer by ETH interface, and the host computer is for sending DSP and FPGA more new procedures, by upper
Machine sends network connection instruction to the device for updating FPGA and DSP program based on network.
The embodiment of the present invention also provides a kind of method that FPGA and DSP program is updated based on network, comprising the following steps:
Initiation parameter configuration is carried out to DSP chip, initializes DSP chip respectively
External interface and DDR3 memory interface；
After the completion of DSP chip initialization, 0 core of DSP chip guides network server
Service routine waits PC control instruction；
After host computer issues network connection instruction within a preset time, 0 core of DSP chip is switched to clothes
The program that business program schema, the DSP for waiting host computer to be received to issue and FPGA update；
Second flash storage of the program write-in DSP chip connection that DSP is updated, FPGA is updated
Corresponding first flash storage of program write-in field programmable gate array chip.
As the preferred embodiment for the method for updating FPGA and DSP program based on network, when host computer does not issue network connection
When instruction, then DSP chip guides the program of the second flash storage storage, field programmable gate array chip
The program for guiding the first flash storage to store, DSP chip and field programmable gate array chip are transported respectively
Row completes the update of FPGA and DSP program.
As the preferred embodiment for the method for updating FPGA and DSP program based on network, verification data are written the first Flash and deposit
Whether reservoir and the second flash storage succeed, and when failure is written in data, host computer carries out error message and reports；Work as data
When being written successfully, host computer carries out state information report, and DSP chip waits the instruction of host computer.
As the preferred embodiment for the method for updating FPGA and DSP program based on network, user is controlled by upper computer software
Hardware platform is restarted or is switched the update that updated program completes FPGA and DSP program.
Embodiments of the present invention have the advantages that the Virtex7 series developed using Xilinx company and Kintex7
The high performance chips of series, DSP are used using the high-performance processor of the more core architectures of KeyStone of TI company development and production
FPGA+DSP (TI multicore TMS320C66XX series) board hardware；DSP multicore task schedule, 0 core of setting are completed system starting and are matched
It sets, 0 core completes network Server service, and host computer completes the write-in of FPGA and DSP curing document；Software control completes Working mould
Formula switching.Host computer and corollary equipment are completed to update the program of FPGA and DSP in hardware device by network connection, real
Existing user safeguards in strange land to device product and program updates, and reduces the dependence to special equipment (emulator).
Detailed description of the invention
It, below will be to embodiment party in order to illustrate more clearly of embodiments of the present invention or technical solution in the prior art
Formula or attached drawing needed to be used in the description of the prior art are briefly described.It should be evident that the accompanying drawings in the following description is only
It is merely exemplary, it for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer, which is extended, obtains other implementation attached drawings.
Fig. 1 is the apparatus structure schematic diagram based on network update FPGA and DSP program provided in the embodiment of the present invention；
Fig. 2 is the method flow diagram based on network update FPGA and DSP program provided in the embodiment of the present invention；
Fig. 3 is the algorithm block diagram based on network update FPGA and DSP program provided in the embodiment of the present invention；
In figure: 1, field programmable gate array chip；2, DSP chip；3, QDR static random-access is deposited
Reservoir；4, the end FMC HPC pin；5, four-way SFP interface；6, PHY physical chip；7, CPLD Complex Programmable Logic Devices；
8, RJ45 interface；9, DC-DC power module；10, host computer；11, DDR3 memory；12, the first flash storage；13, second
Flash storage.
Specific embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book is understood other advantages and efficacy of the present invention easily, it is clear that described embodiment is the present invention one
Section Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
The present embodiments relate to english abbreviation concrete meaning it is as follows:
FPGA:Field-Programmable Gate Array, field programmable gate array；
DSP:Digital Signal Processing, Digital Signal Processing；
The title of Virtex/Kintex:FPGA product；
In KeyStone:OpenStack Identity Service, OpenStack frame be responsible for management authentication,
The module of service regulation and service token function；
SRIO:Serial Rapid I/O connects the string of application towards serial backplane, DSP and associated serial data plane
Line interface；
EMIF:External Memory Interface, external memory interface；
QDR:Quad Data Rate, 4 haplotype data memories；
LVDS:Low-Voltage Differential Signaling, low-voltage differential signal；
The connection of HPC:Hign Pin Connector, FMC interface high-performance pin；
A kind of GTH: HSSI High-Speed Serial Interface；
The upgraded version of SFP:Small Form-factor Pluggable, GBIC, GBIC (Gigabit Interface
The abbreviation of Converter), it is the interface device that kilomegabit electric signal is converted to optical signal；
The abbreviation of SGM:Serial Gigabit Media Independent Interface, Serial Gigabit medium are only
Vertical interface；
PHY:Port Physical Layer, port physical layer are a common abbreviations to osi model physical layer；
GPIO:General Purpose Input Output, bus extender；
DDR:Double Data Rate, double rate memory；
RJ45:RJ is Registered Jack abbreviation, the socket of registration, in FCC (Federal Communications Commission standard
And regulations) in RJ be describe public telecommunication network interface, the RJ45 of computer network is the custom of 8 modular interfaces of standard
Claim；
The number of J1, J5:CPCI connector is similar to resistance R；
DC-DC:Direct current-Direct current becomes the electric energy of a voltage value in DC circuit
For the device of the electric energy of another voltage value；
CPLD:Complex Programmable Logic Device, Complex Programmable Logic Devices；
PCIE:Peripheral component interconnect express, high speed serialization computer expansion bus
Standard；
XP: connector position number is defined；
CPCI:CompactPCI, the High performance industrial meter that International Industry computer manufacture person federation proposed in 1994
Calculation machine bus standard.
Specific reference to Fig. 1, update the device of FPGA and DSP program based on network, including Virtex7 series or
The field programmable gate array chip 1 of Kintex7 series, the DSP chip based on the more core architectures of KeyStone
2, between the field programmable gate array chip 1 and DSP chip 2 by SRIO serial bus interface or
The connection of EMIF interface.The field programmable gate array chip 1 is configured with QDR static random access memory for storing data
Device 3 and the first flash storage 12 for storing FPGA more new procedures, field programmable gate array chip 1 are connect by LVDS
Mouth is connected to the end FMC HPC pin 4, and field programmable gate array chip 1 is connected with four-way SFP by GTH HSSI High-Speed Serial Interface
Interface 5；The DSP chip 2 is connected with PHY physical chip 6, digital signal processor core by SGM interface
Piece 2 is configured with DDR3 memory 11 for storing data and the second flash storage 13 for storing DSP more new procedures.
Field programmable gate array chip 1 is connected with CPLD Complex Programmable Logic Devices 7 by GPIO interface, and the CPLD complexity can
Programmed logic device 7 connects the DSP chip 2 by EMIF interface.
In the one embodiment for updating the device of FPGA and DSP program based on network, the PHY physical chip 6 is equipped with
Two, a PHY physical chip is connected with RJ45 interface 8, another PHY physical chip is connected with ZD connector XP3,
The ZD connector XP3 connects the DSP chip 2 by PCIE interface.It further include ZD connector XP1 and ZD
Connector XP2, the ZD connector XP1 connect the field-programmable through GTH HSSI High-Speed Serial Interface respectively with ZD connector XP2
Gate array chip 1.
Specifically, PHY is to connect the equipment (MAC) of a data link layer to a physical media, such as optical fiber or copper cable
Line.Typical PHY includes PCS (Physical Coding Sublayer, Physical Coding Sublayer) and PMD (Physical
Media Dependent, physical medium associated sub-layer).PCS raises the price and decodes to the information for being sent and being received, it is therefore an objective to make
Receiver is easier to restore signal.ZD connector can realize high request application purpose, data transmission rate with high data transmission rate
Up to 20 or 25Gbit/s.
Based on network update FPGA and DSP program device one embodiment in, further include CPCI connector J1 and
CPCI connector J5, the CPCI connector J1 are connected to DC-DC electricity by the corresponding DC5V supply input of standard cpci bus
Source module 9, the CPCI connector J5 connect the field programmable gate array chip 1 through GPIO interface with LVDS interface.It adopts
The newest technological achievement of PC machine can be absorbed with CPCI but meet communication and industry application in real time it is necessary it is firmer,
More reliable, modularization easily uses, advantage easy to maintain.DC-DC power module 9 can directly mount on a printed circuit, can
It powers for digital signal processor and field programmable gate array.Small size, high reliability export pressure stabilizing, and precision is high, high sexual valence
Than；A variety of inputs, output voltage；Built-in input filter, low electromagnetic compatibility.
In the one embodiment for updating the device of FPGA and DSP program based on network, FPGA and DSP journey is updated based on network
The device of sequence is connected with host computer 10 by ETH interface, and the host computer 10 passes through for sending DSP and FPGA more new procedures
Host computer 10 sends network connection instruction to the device for updating FPGA and DSP program based on network.
Referring to figure 1, figure 2 and figure 3, the embodiment of the present invention also provides a kind of side that FPGA and DSP program is updated based on network
Method, comprising the following steps:
S1: initiation parameter configuration is carried out to DSP chip 2, initializes digital signal processor core respectively
11 interface of external interface and DDR3 memory of piece 2；
S2: after the completion of DSP chip 2 initializes, the 0 core guidance network clothes of DSP chip 2
Business device service routine, waits 10 control instruction of host computer；
S3: after host computer 10 issues network connection instruction within a preset time, 0 core of DSP chip 2 is cut
Service routine mode is changed to, the program that the DSP and FPGA for waiting host computer 10 to be received to issue update；
S4: the second flash storage 13 that the program write-in DSP chip 2 that DSP updates is connected, it will
Corresponding first flash storage 12 of field programmable gate array chip 1 is written in the program that FPGA updates.
In the one embodiment for updating the method for FPGA and DSP program based on network, connect when host computer 10 does not issue network
When connecing instruction, then DSP chip 2 guides the program of the second flash storage 13 storage, field-programmable gate array
Column chip 1 guides the program of the first flash storage 12 storage, DSP chip 2 and field programmable gate array
Chip 1 is separately operable the update for completing FPGA and DSP program.
In the one embodiment for updating the method for FPGA and DSP program based on network, verification data are written the first Flash and deposit
Whether reservoir 12 and the second flash storage 13 succeed, and when failure is written in data, host computer 10 carries out error message and reports；
When data are written successfully, host computer 10 carries out state information report, and DSP chip 2 waits the finger of host computer 10
It enables.User restarted or switched by 10 software control hardware platform of host computer updated program complete FPGA and
The update of DSP program.
In embodiments of the present invention, wherein 0 core of DSP completes the initiation parameter configuration of DSP by process control, point
Not Chu Shihua DSP external interface (such as serial ports, network interface, SRIO serial bus interface) and plug-in DDR3 memory 11 connect
Mouthful.After the completion of DSP initialization, 0 core guides network Server service routine from Flash, waits 10 control instruction of host computer.On
After position machine 10 issues network connection instruction at the appointed time, 0 core of DSP is switched to service routine mode, waits to be received upper
The program that the DSP and FPGA issued updates, and the program of update is write respectively in the corresponding flash storage of DSP and FPGA.
If host computer 10 does not issue network connection instruction, DSP and FPGA guide the program stored in respective Flash, are loaded.
If data complete write-in under renewal model, and after verifying successfully, user can pass through 10 software control hardware platform of host computer
Restart or directly switch updated program, allows it to complete more new function, and system restarts.The present invention is real
The high performance chips of Virtex7 series and Kintex7 series that example is developed by using Xilinx company are applied, DSP is public using TI
The high-performance processor for taking charge of the more core architectures of KeyStone of development and production, using FPGA+DSP (TI multicore TMS320C66XX system
Column) board hardware；DSP multicore task schedule, 0 core of setting complete system starting configuration, and 0 core completes network Server service, on
Position machine 10 completes the write-in of FPGA and DSP curing document；Software control completes operating mode switching.Host computer 10 and corollary equipment
By network connection, completes to update the program of FPGA and DSP in hardware device, realize user in strange land to device product
It carries out maintenance and program updates, reduce the dependence to special equipment (emulator).
Although above having used general explanation and specific embodiment, the present invention is described in detail, at this
On the basis of invention, it can be made some modifications or improvements, this will be apparent to those skilled in the art.Therefore,
These modifications or improvements without departing from theon the basis of the spirit of the present invention are fallen within the scope of the claimed invention.
Claims (9)
1. updating the device of FPGA and DSP program based on network, which is characterized in that including Virtex7 series or Kintex7 series
Field programmable gate array chip, based on the DSP chip of the more core architectures of KeyStone, the scene can
It programs and is connected between gate array chip and DSP chip by SRIO serial bus interface or EMIF interface；
The field programmable gate array chip is configured with QDR static random access memory for storing data and for depositing
The first flash storage of FPGA more new procedures is stored up, field programmable gate array chip is connected to the end FMC by LVDS interface
HPC pin, field programmable gate array chip are connected with four-way SFP interface by GTH HSSI High-Speed Serial Interface；
The DSP chip is connected with PHY physical chip by SGM interface, and DSP chip is matched
It is equipped with DDR3 memory for storing data and the second flash storage for storing DSP more new procedures；
Field programmable gate array chip is connected with CPLD Complex Programmable Logic Devices by GPIO interface, and the CPLD is complicated
Programmable logic device connects the DSP chip by EMIF interface.
2. the device according to claim 1 for updating FPGA and DSP program based on network, which is characterized in that the PHY object
There are two reason layer chip is set, a PHY physical chip is connected with RJ45 interface, another PHY physical chip is connected with
ZD connector XP3, the ZD connector XP3 connect the DSP chip by PCIE interface.
3. the device according to claim 1 for updating FPGA and DSP program based on network, which is characterized in that further include ZD
Connector XP1 and ZD connector XP2, the ZD connector XP1 are connected through GTH HSSI High-Speed Serial Interface respectively with ZD connector XP2
The field programmable gate array chip.
4. the device according to claim 1 for updating FPGA and DSP program based on network, which is characterized in that further include
CPCI connector J1 and CPCI connector J5, the CPCI connector J1 pass through the corresponding DC5V supply input of standard cpci bus
It is connected to DC-DC power module, the CPCI connector J5 connects the field programmable gate with LVDS interface through GPIO interface
Array chip.
5. the device according to any one of claims 1 to 4 for being updated FPGA and DSP program based on network, feature are existed
In the device for updating FPGA and DSP program based on network is connected with host computer by ETH interface, and the host computer is for sending
DSP and FPGA more new procedures are sent network connection to the device for being updated FPGA and DSP program based on network by host computer and referred to
It enables.
6. updating the method for FPGA and DSP program based on network, which comprises the following steps:
Initiation parameter configuration is carried out to DSP chip, initializes the external of DSP chip respectively
Interface and DDR3 memory interface；
After the completion of DSP chip initialization, 0 core of DSP chip guides network server service
Program waits PC control instruction；
After host computer issues network connection instruction within a preset time, 0 core of DSP chip is switched to service journey
The program that sequence pattern, the DSP for waiting host computer to be received to issue and FPGA update；
Second flash storage of the program write-in DSP chip connection that DSP is updated, the journey that FPGA is updated
Corresponding first flash storage of field programmable gate array chip is written in sequence.
7. the method according to claim 6 for updating FPGA and DSP program based on network, which is characterized in that work as host computer
When not issuing network connection instruction, then DSP chip guides the program of the second flash storage storage, and scene can
Program the program that gate array chip guides the storage of the first flash storage, DSP chip and field programmable gate
Array chip is separately operable the update for completing FPGA and DSP program.
8. the method according to claim 6 for updating FPGA and DSP program based on network, which is characterized in that verification data
The first flash storage is written and whether the second flash storage succeeds, when failure is written in data, host computer carries out mistake
Information reporting；When data are written successfully, host computer carries out state information report, and DSP chip waits host computer
Instruction.
9. the method according to claim 8 for updating FPGA and DSP program based on network, which is characterized in that user passes through
Upper computer software control hardware platform is restarted or is switched updated program and completes FPGA and DSP program more
Newly.
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| CN111142918A (en) * | 2019-12-26 | 2020-05-12 | 天津津航计算技术研究所 | Programmable device program parameter configuration and flow control method |
| CN114237676A (en) * | 2021-12-28 | 2022-03-25 | 湖南云箭智能科技有限公司 | FPGA (field programmable Gate array) logic updating method, device, equipment and readable storage medium |
| CN114979593A (en) * | 2022-04-07 | 2022-08-30 | 华东师范大学 | Video display driving system based on novel high-speed 4K digital micromirror chip |
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