CN1677346A - Programmable device program update method and board card capable of updating program - Google Patents
Programmable device program update method and board card capable of updating program Download PDFInfo
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- CN1677346A CN1677346A CN 200410022188 CN200410022188A CN1677346A CN 1677346 A CN1677346 A CN 1677346A CN 200410022188 CN200410022188 CN 200410022188 CN 200410022188 A CN200410022188 A CN 200410022188A CN 1677346 A CN1677346 A CN 1677346A
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Abstract
A program updating method of programmable device and a program updating boardcard, relating to a storing and updating technique of downloading files of the programmable device on the boardcard of communication equipment. The invention provides a program updating method of programmable device, including the following steps: a. the system informs a processing device to initiate updating by the I2C bus and the processor device prepares; b. the processing device receives and stores data; c. the processing device informs the main system to stop running the programmable device; d. the processing device downloads the new program stored in the step b to the programmable device. The invention provides a boardcard able to update the program. The beneficial effects of the invention: on the condition of increasing the cost of a few materials, it completes program downloading for FPGA as the boardcard is power-on by CPLD and completes program updating by the I2C bus independent of data channels, not only achieving the requirements of high downloading speed and high reliability but also the downloading and updating little occupying system resources.
Description
Technical field
The present invention relates to computer communication technology, particularly the storage of programming device file in download and the technology of renewal on the communication apparatus integrated circuit board.
Background technology
I
2C bus (or claiming iic bus) is a kind of two-wire serial bus by PHILIPS Co.'s exploitation, topmost advantage is its simplicity and validity, its occupation space is very little, thereby has reduced the space of circuit board and the quantity of chip pin, and then has reduced interconnected cost.While I
2C is a kind of general specification, all integrated this bus of most of flush bonding processors, the convenient transplanting on hardware systems.
FPGA (field programmable gate array) is that a kind of structure is flexible, the programming device that internal trigger resource density is big, and the user can change device inside line situation by programming can make it present different functions.Fast development along with EDA (electric design automation) technology, in card insert type communication class product, using FPGA on the veneer has been a very general phenomenon, FPGA is with its jumbo trigger resources, function flexibly, and the mode of upgrading easily, for the deviser provides sizable convenience, in design, more and more be used.And make full use of FPGA flexibly programmable features will be a kind of shortcut that cost seldom but can improve the comprehensive strength of product of paying to the service that the end user provides HardwareUpgring and fault to get rid of.
The general branch done two kinds in the storage that FPGA on the communication apparatus integrated circuit board is downloaded now, download and renewal operation, a kind of storer of taking to be solidificated on the integrated circuit board, power at every turn and initiatively call in data from storer by FPGA, the benefit of this method is to download not rely on the main system participation, speed is fast, and shortcoming is to be difficult for upgrading; And another mode is FPGA to be downloaded leave among the FLASH on the motherboard, by main frame it is read and write, FPGA downloads and finishes by public data channel and conversion chip, the benefit of this kind method is that code update is flexible, and shortcoming is to have taken main system FLASH space, primary processor also must participate in whole downloading process, causes device start slow.
Summary of the invention
Technical matters to be solved by this invention is, provide under a kind of situation that is implemented in the equipment normal operation long-range to the file in download of FPGA upgrade quick, stable, cost is low, the method and the corresponding device thereof of easy transplanting, make upgrade finish after integrated circuit board can continue normal operation and reach integrated circuit board is upgraded or fixed a breakdown.
The present invention solve the technical problem the technical scheme that is adopted, and a kind of program updating method of programmable device is provided, and may further comprise the steps:
A. system passes through I
2C bus notifier processes device initiates to upgrade, and processing apparatus is prepared;
B. processing apparatus receives data, and storage;
C. processing apparatus is notified main system, and system stops the operation of programming device;
The d processing apparatus downloads to programming device with the new procedures of storing among the step b.
Among the described step a, processing apparatus is provided with zone bit and represents ready.Among the described step b, processing apparatus receives data, and format transformation, encrypts.Among the described step b, the memory storage space that processing apparatus uses divides work at least two parts, and a part is deposited and upgraded the program that writes, the old program that another part can normally use before depositing and upgrading.Between described step b and the step c, also has checking procedure.Described checking procedure is: main system is passed through I
2The C bus reads the data that newly write, and verification in addition; If correctly then the renewal of notifier processes device is finished, if incorrect then renewal once more.Described step c comprises: c1. processing apparatus notice main system stops integrated circuit board work; C2. main system stops the operation of programming device, and the unloading driver; Described steps d comprises: the d1. processing apparatus sends heat and inserts interruption; D2. processing apparatus reads the program that newly writes, and according to the application configuration programming device that newly writes, if configuration is unsuccessful, processing apparatus reads old program, according to old application configuration programming device; If configuration successful enters next step; D3. test programming device, if dysfunction, main system is passed through I
2C bus notifier processes device upgrades failure, and processing apparatus reads old program, according to old application configuration programming device.After the described steps d 3, also have steps d 4: main system is exchanged old code segment pointer position and fresh code segment pointer.
Described processing apparatus is CPLD or has I
2The single-chip microcomputer of C interface, described programming device are the programming device of refreshable program code, as FPGA, DSP; Described storer is FLASH.
The present invention also provides a kind of integrated circuit board of refreshable program, comprises slot, processing apparatus, programming device, storer, and processing apparatus, programming device are connected with slot, and processing apparatus is connected with programming device, and processing apparatus also is connected with storer; In being connected of processing apparatus and slot, exist based on I
2The coupling part of C bus architecture.
About " existing based on I
2The coupling part of C bus architecture " be explained as follows: after integrated circuit board is plugged backboard,, have based on I between CPLD and the main system by slot
2The annexation of C bus, when integrated circuit board independence, in other words, when not plugging backboard, being connected between CPLD and the main system isolated, but when slot being considered as parts, (is based on I between CPLD and the main system in the above-mentioned connection
2The connection of C bus), CPLD to the connection of this section of slot be outwardness, therefore " to exist based on I
2The coupling part of C bus architecture " explain it.
The invention has the beneficial effects as follows that under the situation that increases a small amount of cost of raw material, the program of FPGA is downloaded when powering on by using CPLD to finish integrated circuit board, is independent of the I of data channel
2The C bus is finished program updates, has not only reached the high requirement of the fast reliability of speed of download, downloads and upgrades also few occupying system resources, and in communication apparatus integrated level more and more higher today, the advantage of this technology will be embodied more and more.Simultaneously, based on the programmable characteristics of CPLD, this FPGA download and method for updating only need be done a spot of change and just can be transplanted on the system of using other programming devices, have improved development efficiency, have avoided the duplication of labour.
The present invention is further illustrated below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 is the method flow diagram of the specific embodiment of the invention.
Fig. 2 is the device synoptic diagram of the specific embodiment of the invention.
Embodiment
As shown in Figure 1, whole process was divided into for three steps, comprised renewal, verification and activation.During renewal, system passes through I
2The C bus is provided with CPLD one register and initiates the renewal of FPGA file in download, and begins to pass through I
2The C bus sends new data.CPLD receives after the data, and the translation data form through sending it to the data port of storer after the cryptographic algorithm computing, sends data address simultaneously.To divide work two parts for memory storage space, a part is deposited the program that newly writes, the program (program when perhaps dispatching from the factory) that another part can normally use before depositing and upgrading, two sections can be exchanged, and the content that specifically new procedures is written to which section or downloads which section is controlled by the mode that register value is set by main system to FPGA.After data write and finish, CPLD began the state of consults memory, determined whether storer writes to finish, in case finish then the related register value is set; Main system begins regularly to inquire about CPLD simultaneously, finishes information up to reading the storer programming.
Checking procedure is initiated by main system equally, and data are passed through I from storer by deciphering and the format conversion of CPLD
2C-channel is read by main system, finish read in after main system begin checking data, correctly then notify CPLD, otherwise write again.
Finish after above two steps, CPLD stops the communication of current integrated circuit board by simulation hot removal process, simulate hot insertion process afterwards and activate the work of integrated circuit board again, if FPGA can not normally download, then download again to the old program segment of storer, upgrade failure by changing address switchover; If FPGA can normally download, and function can not reach designing requirement, switch to old program segment equally; When the complete operate as normal of FPGA energy, then main system is exchanged old program segment pointer and new program segment pointer, and FPGA program is afterwards downloaded reading of data the program segment that will be defaulted as after upgrading.
Referring to Fig. 2, the invention provides the veneer that a cover works in the card insert type communication product that adopts CompactPCI (abbreviating CPCI as) bus architecture, it comprises the CPLD chip of a slice altera corp fpga chip and a slice Lattice, the FLASH of a slice SST company.As the CPLD of processing apparatus and the I of CPCI slot
2C bus, hot plug signal wire ENUM and HSS, and 5 download signal lines of FPGA (nSTATUS, nCONFIG, DATA0, DCLK, CONF_DONE), the data of FLASH chip, address and read-write chip select line are connected; Integrated circuit board by draw on the MSEL0 with FPGA with drop-down its downloading mode that is provided with of MSEL1 be the passive serial mode.When renewal process began, main system was passed through I
2C bus notice CPLD upgrades beginning and the fresh code segment pointer is set, and CPLD then begins from I
2Receive data on the C bus, write the above-mentioned appointed area of FLASH chip after format transformation and the encryption.Be sent completely back CPLD and read new file in download from FLASH, deciphering, format transformation passes through I
2C gives the main system verification.After verification is correct, CPLD simulation hot removal and hot insertion process send look-at-me to main system, reload driver, the sequential of the passive serial of CPLD simulation afterwards begins new file in download is sent to FPGA, FPGA downloads also not success after the trial of a certain stipulated number, assert that then file in download has damage, CPLD switches to old program storage area and downloads again, waits for main system initiation renewal next time; Otherwise think that program updates is successful.If integrated circuit board can not reach expectation function after the program updates success, can think that then there is mistake in program itself, main system will switch to old program segment and initiate a new FPGA download this moment; When the complete operate as normal of FPGA energy, then main system is exchanged old program segment pointer and new program segment pointer, and FPGA program is afterwards downloaded reading of data the program segment that will be defaulted as after upgrading.
Explanation of nouns:
The CPLD-CPLD;
The quick Erarable Programmable Read only Memory of FLASH-;
The DSP-digital signal processor;
Upgrade-new documentation of program is write the process of FLASH;
The cover bus specification that CompactPCI-one cover is formulated by group of PCI industrial computer manufacturer based on the pci bus function;
Be used for the signal of hot plug interrupt in the ENUM-CPCI bus, low level is effective, and expression has the hot plug action to take place;
Be used to show the signal of hot pluggable condition in the HSS-CPCI bus, different level is represented heat insertion and hot removal;
Download-CPLD sends to FLASH internal processes file the process of FPGA.
Claims (11)
1, program updating method of programmable device may further comprise the steps:
A. system passes through I
2C bus notifier processes device initiates to upgrade, and processing apparatus is prepared;
B. processing apparatus receives data, and storage;
C. processing apparatus reporting system, system stops the operation of programming device;
D. processing apparatus downloads to programming device with the new procedures of storing among the step b.
2, program updating method of programmable device as claimed in claim 1, among the described step a, processing apparatus is provided with zone bit and represents ready.
3, program updating method of programmable device as claimed in claim 1, among the described step b, processing apparatus receives data, and format transformation, encrypts.
4, program updating method of programmable device as claimed in claim 1, among the described step b, the memory storage space that processing apparatus uses divides work at least two parts, and a part is deposited and upgraded the program that writes, the old program that another part can normally use before depositing and upgrading.
5, program updating method of programmable device as claimed in claim 4 between described step b and the step c, also has checking procedure.
6, program updating method of programmable device as claimed in claim 5, described checking procedure is: main system is passed through I
2The C bus reads the data that newly write, and verification in addition; If correctly then the renewal of notifier processes device is finished, if incorrect then renewal once more.
7, program updating method of programmable device as claimed in claim 4, described steps d comprises:
D1. processing apparatus is notified main system;
D2. processing apparatus reads the program that newly writes, and according to the application configuration programming device that newly writes, if configuration is unsuccessful, processing apparatus reads old program, according to old application configuration programming device; If configuration successful enters next step;
D3. test programming device, if dysfunction, main system is passed through I
2C bus notifier processes device upgrades failure, and processing apparatus reads old program, according to old application configuration programming device.
8, program updating method of programmable device as claimed in claim 4 after the described steps d 3, also has steps d 4: main system is exchanged old code segment pointer position and fresh code segment pointer.
9, as the described program updating method of programmable device of above arbitrary claim, described processing apparatus is CPLD or has I
2The single-chip microcomputer of C interface, described programming device are the programming device of refreshable program code.
10, the integrated circuit board of refreshable program comprises slot, processing apparatus, programming device, storer, and processing apparatus, programming device are connected with slot, and processing apparatus is connected with programming device, and processing apparatus also is connected with storer; In being connected of processing apparatus and slot, exist based on I
2The coupling part of C bus architecture.
11, the integrated circuit board of refreshable program as claimed in claim 10, described processing apparatus are CPLD or have I
2The single-chip microcomputer of C interface, described programming device are the programming device of refreshable program code, and described storer is FLASH.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 200410022188 CN1677346A (en) | 2004-04-01 | 2004-04-01 | Programmable device program update method and board card capable of updating program |
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| CN 200410022188 CN1677346A (en) | 2004-04-01 | 2004-04-01 | Programmable device program update method and board card capable of updating program |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426233C (en) * | 2005-12-09 | 2008-10-15 | 中兴通讯股份有限公司 | Method for automatically configurating programmable device by inlaid CPU |
| CN100428160C (en) * | 2006-12-06 | 2008-10-22 | 华为技术有限公司 | Method and system for on-line upgrading logic device |
| CN100432936C (en) * | 2006-09-20 | 2008-11-12 | 华为技术有限公司 | Method and system for loading FPGA target program |
| CN100445950C (en) * | 2006-09-27 | 2008-12-24 | 华为技术有限公司 | Inter-veneer data loading method and system and connection device for veneer loading |
| CN100498753C (en) * | 2007-08-31 | 2009-06-10 | 上海广电（集团）有限公司中央研究院 | Method for accessing on-site programmable gate array internal memory through I2C interface |
| CN1991731B (en) * | 2005-12-26 | 2011-11-09 | 鸿富锦精密工业（深圳）有限公司 | Chip burn-recording system |
| CN102280133A (en) * | 2011-08-16 | 2011-12-14 | 杭州晟元芯片技术有限公司 | Anti-interception code encryption burning method |
| CN104050006A (en) * | 2014-07-02 | 2014-09-17 | 曙光信息产业(北京)有限公司 | Updating system and updating method of FPGA |
| CN106843983A (en) * | 2017-02-09 | 2017-06-13 | 深圳市风云实业有限公司 | The system and method for remote upgrading field programmable gate array |
| CN109491679A (en) * | 2017-09-08 | 2019-03-19 | 迈普通信技术股份有限公司 | A kind of CPLD online upgrading method and device |
| CN109558158A (en) * | 2019-01-30 | 2019-04-02 | 北京昊海雅正科技有限公司 | The device and method of FPGA and DSP program is updated based on network |
| CN111709522A (en) * | 2020-05-21 | 2020-09-25 | 哈尔滨工业大学 | Deep learning target detection system based on server-embedded cooperation |
| CN112306933A (en) * | 2019-07-15 | 2021-02-02 | 栾东海 | Dual-bus control panel card based on PCI and PXIE |
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2004
- 2004-04-01 CN CN 200410022188 patent/CN1677346A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100426233C (en) * | 2005-12-09 | 2008-10-15 | 中兴通讯股份有限公司 | Method for automatically configurating programmable device by inlaid CPU |
| CN1991731B (en) * | 2005-12-26 | 2011-11-09 | 鸿富锦精密工业（深圳）有限公司 | Chip burn-recording system |
| CN100432936C (en) * | 2006-09-20 | 2008-11-12 | 华为技术有限公司 | Method and system for loading FPGA target program |
| CN100445950C (en) * | 2006-09-27 | 2008-12-24 | 华为技术有限公司 | Inter-veneer data loading method and system and connection device for veneer loading |
| CN100428160C (en) * | 2006-12-06 | 2008-10-22 | 华为技术有限公司 | Method and system for on-line upgrading logic device |
| CN100498753C (en) * | 2007-08-31 | 2009-06-10 | 上海广电（集团）有限公司中央研究院 | Method for accessing on-site programmable gate array internal memory through I2C interface |
| CN102280133A (en) * | 2011-08-16 | 2011-12-14 | 杭州晟元芯片技术有限公司 | Anti-interception code encryption burning method |
| CN104050006A (en) * | 2014-07-02 | 2014-09-17 | 曙光信息产业(北京)有限公司 | Updating system and updating method of FPGA |
| CN106843983A (en) * | 2017-02-09 | 2017-06-13 | 深圳市风云实业有限公司 | The system and method for remote upgrading field programmable gate array |
| CN109491679A (en) * | 2017-09-08 | 2019-03-19 | 迈普通信技术股份有限公司 | A kind of CPLD online upgrading method and device |
| CN109558158A (en) * | 2019-01-30 | 2019-04-02 | 北京昊海雅正科技有限公司 | The device and method of FPGA and DSP program is updated based on network |
| CN109558158B (en) * | 2019-01-30 | 2024-05-31 | 北京昊海雅正科技有限公司 | Device and method for updating FPGA and DSP programs based on network |
| CN112306933A (en) * | 2019-07-15 | 2021-02-02 | 栾东海 | Dual-bus control panel card based on PCI and PXIE |
| CN111709522A (en) * | 2020-05-21 | 2020-09-25 | 哈尔滨工业大学 | Deep learning target detection system based on server-embedded cooperation |
| CN111709522B (en) * | 2020-05-21 | 2022-08-02 | 哈尔滨工业大学 | Deep learning target detection system based on server-embedded cooperation |
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