KR20070101590A - Fpga program upgrade device - Google Patents

Abstract

Device for upgrading a FPGA(Field programmable gate array) program is provided to download a FPGA upgrade program over an Ethernet from a FPGA manufacturer homepage by downloading the upgrade program from the control device through a local bus to a flash or to a ROM through a JTAG(Joint test action group) port and rebooting the computer. A device for upgrading a FPGA(Field programmable gate array) program comprises a computer(21) having installed a program for downloading a FPGA program, a JTAG(Joint test action group) port(22) connecting the computer and the memory of the program, a flash or a ROM(23) connected to the JTAG port and storing various programs, a serial port(24) connected to the flash or to the ROM and transferring the program, a FPGA(25) connected to the flash or to the ROM through the serial port and allows a user to arbitrarily program, an Ethernet(26) allowing connection to a FPGA manufacturer homepage and downloading of an upgraded FPGA program, and a control device(27) storing the downloaded FPGA program and controlling the flash or the ROM to store the downloaded FPGA program to the flash or to the ROM.

Description

FPGA Program Update Device {FPGA PROGRAM UPGRADE DEVICE}

1 is a block diagram of a conventional FPM program updater.

Fig. 2 is a block diagram of the FP program updater of the present invention.

* Explanation of symbols for the main parts of the drawings *

21; Computer 22; JTAG port

23; Fresh or rom 24; Serial port

25; FPGA 26; Controller

27; Ethernet

The present invention relates to a FPGA program updating apparatus, and more particularly, to an FPGA program updating apparatus that enables to easily update the FTJI program of a device from a remote location.

In general, a field programmable gate array (FPGA) program (hereinafter referred to as an FPGA) program is stored in a memory (ROM, FLASH MEMORY) of a device (computer), and thus it is virtually impossible for a user to update the program.

Therefore, in order to update the FPGA program, the user must visit a service center or a manufacturer and request the update.

In order to update the FPGA program, as shown in FIG. 1, a computer 11 in which a download program for downloading the FPGA program is installed; A JTAG (Joint Test Action Group) port 12 for connecting the computer 11 and a program memory; A fresh or ROM 13 connected to the JTAG port 12 to store various programs; A serial port 14 connected to the fresh or ROM 13 to transmit a program; It is connected to the fresh or ROM 13 through the serial port 14 to form a highly integrated FPGA (15) in which a large amount of gate logic blocks are constantly arranged so that a user can program at random.

The conventional FPGA program update configured as described above installs the FPGA program in the computer 11 and then downloads the FPGA program installed in the computer 11 to the fresh or ROM 13 through the JTAG port 12. .

Subsequently, when the computer 11 is powered off and on, the FPGA 15 updates the FPGA program by downloading the FPGA program downloaded from the fresh or ROM 13.

As described above, when the FPGA program is to be updated to improve the technical error or performance of the device in use, the user can visit the service center or the manufacturer directly and request it. There is a problem that goes into this.

An object of the present invention is to enable anyone to easily update the FPGA program of the device from a remote location.

In order to achieve the above object, the present invention provides a computer that includes a download program for downloading an FPGA program; A JTAG port for connecting the computer and a program memory; A fresh or rom connected to the JTAG port and storing various programs; A serial port connected to the fresh or ROM to transmit a program; An FPGA that is connected to the fresh or ROM through the serial port and programmed by a user at random; Ethernet for downloading the FPGA program is connected and updated through the manufacturer and the homepage of the FPGA; And a controller for storing the FPGA program downloaded through the Ethernet and controlling the fresh or ROM to store the downloaded FPGA program.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Fig. 2 is a block diagram of the FPM program updating device of the present invention. The present invention is a computer 21, a JTAG port 22, a fresh or ROM 23, a serial port 24, an FPGA 25, a controller. (26), Ethernet (27).

The computer 21 is a device in which a download program for downloading a program required for operation from a manufacturer is installed.

The JTAG port 22 is a standard joint test activity group port that connects the computer 21 and a program memory.

The fresh or ROM 23 is connected to the computer 21 via the JTAG port 22 to store the downloaded FPGA program and to store various programs.

The serial port 24 is a communication port that is connected to the fresh or ROM 23 and transmits the downloaded program.

The FPGA 25 is connected to the fresh or ROM 25 through the serial port 24 to download the downloaded program, and highly integrated with gate logic arranged so that a user can program it arbitrarily. Circuit.

The controller 26 is a controller connected to the fresh or ROM 23 and the FPGA 25 to store a program downloaded to the fresh or ROM 23 and to be downloaded to the FPGA 25.

The Ethernet 27 is a LAN for connecting to the outside Internet and downloading an update program from the manufacturer to the controller 26.

Not described in the drawings The local bus is a data bus for transmitting and receiving data.

According to the present invention configured as described above, after the FPGA program is installed in the computer 21, the FPGA program installed in the computer 21 is downloaded to the fresh or ROM 23 through the JTAG port 22. When the computer 21 is turned off and on, the FPGA 25 downloads the FPGA program downloaded from the fresh or ROM 23.

Subsequently, when the program of the FPGA 25 is to be updated, the controller 27 accesses the manufacturer's homepage through the Ethernet 26, downloads the FPGA program of the FPGA 25 from the manufacturer, and then downloads the local bus. Input to the FPGA 25 through.

The FPGA 25 inputs an FPGA program input from the controller 27 through a local bus to the fresh or ROM 23 through the JTAG port 22.

Subsequently, when the power is rebooted, the FPGA program input to the fresh or ROM 23 is downloaded to the FPGA 25 so that the new FPGA program is updated in the FPGA 25.

As described above, in the present invention, when a new program is updated in an FPGA of a device, a controller connected to Ethernet is connected to the FPGA, and a new FPGA program is input into a memory from a manufacturer of an external FPGA through the Ethernet. By downloading, the hassle and the time-consuming and effortless effort to update the program of the FPGA is provided.

Claims (1)

A computer on which a download program for downloading the FPGA program is installed; A JTAG port for connecting the computer and a program memory; A fresh or rom connected to the JTAG port and storing various programs; A serial port connected to the fresh or ROM to transmit a program; An FPGA that is connected to the fresh or ROM through the serial port and programmed by a user at random; Ethernet for downloading the FPGA program is connected and updated through the manufacturer and the homepage of the FPGA; And a controller for storing the FPGA program downloaded through the Ethernet and controlling the fresh or ROM to store the downloaded FPGA program.

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