CN109547023A - A kind of processing circuitry of intermediate frequency and implementation method - Google Patents
A kind of processing circuitry of intermediate frequency and implementation method Download PDFInfo
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- CN109547023A CN109547023A CN201811376159.8A CN201811376159A CN109547023A CN 109547023 A CN109547023 A CN 109547023A CN 201811376159 A CN201811376159 A CN 201811376159A CN 109547023 A CN109547023 A CN 109547023A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
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Abstract
The present invention relates to the IF signal processing field of electronic measuring instrument, especially a kind of processing circuitry of intermediate frequency and implementation method.Processing circuitry of intermediate frequency includes: intermediate frequency conditioning module, A/D acquisition module, clock generation module, intermediate-freuqncy signal output module and control module.It uses down coversion, multistage-combination filtering, multistage amplification and flatness control technology, and the anti-aliasing filter of A/D sampling may be implemented, reduce costs, power consumption, volume and weight；Using programmable sampling clock generation circuit, the intermediate-freuqncy signal before down coversion or after down coversion can be provided to external treatment.The Dynamic Closed Loop Control circuit of " second amplifying circuit that control module, A/D conversion circuit, flatness adjust circuit, A/D acquisition module " composition is constructed, is overflowed partially for guaranteeing that ADC is not full.
Description
Technical field
The present invention relates to the IF signal processing field of electronic measuring instrument, especially a kind of processing circuitry of intermediate frequency and realization
Method.
Background technique
Currently, handheld instrument (such as spectrum analyzer) because its have the characteristics that it is small in size, light-weight, easy to carry, both
The demand of (such as conventional plant and laboratory) test can be better meet in field, and is had to field testing/field diagnostic
Adaptability has been widely used for each corner of national economy and safety.In order to volume, weight and power consumption etc. by
In the case where limit realize handheld instrument whole design, " IF signal processing " as the analog-to-digital conversion of instrument core it
One, how to be realized under lesser volume, weight and lower power consumption its circuit design be a very challenging property, also very intentionally
The work of justice.
The IF process of existing electronic table measuring instrument mainly directly carries out A/D sampling, i.e., by sampling clock to micro-
The intermediate-freuqncy signal exported after wave/radio frequency frequency conversion is successively filtered with after gain control, is directly sampled by ADC, exports number
Word signal is handled to subsequent DSP or FPGA.
It is sampled using direct A/D and carries out IF process, especially when the higher intermediate-freuqncy signal of processing frequency, direct A/D
Sampling needs higher sampling clock and high-speed ADC chip.How in volume, power consumption and the restricted situation of weight, generate
High speed sampling clock is a problem for handheld instrument；High-speed ADC prevailing price is very high, power consumption is larger, this is to cost
It controls for stringent, the lesser handheld instrument of power consumption, it is difficult to bear；The digital signal output speed that high-speed ADC generates is very fast,
It needs the DSP or FPGA of subsequent processing to configure higher, improves the cost of subsequent module.
Summary of the invention
Therefore, for the present invention precisely in order to solving the problems, such as above and researching and developing, its purpose is to provide one kind to be based on lower change
Frequently, the processing circuitry of intermediate frequency and implementation method of the gain controllable of multistage-combination filtering, multistage amplification, it is intended to solve prior art function
The problems such as larger, possessive volume is larger, weight is larger and higher cost is consumed, is adopted the following technical scheme that
A kind of processing circuitry of intermediate frequency, it is characterised in that: generate mould including intermediate frequency conditioning module, A/D acquisition module, clock
Block, intermediate-freuqncy signal output module and control module；
The intermediate frequency conditioning module is respectively connected with intermediate-freuqncy signal output module and A/D acquisition module, intermediate frequency conditioning module
It is handled for being sent to intermediate-freuqncy signal output module and A/D acquisition module after being improved intermediate-freuqncy signal respectively；
The A/D acquisition module is connected with intermediate-freuqncy signal output module, and A/D acquisition module is used to believe conditioned intermediate frequency
Number down coversion, filtering are carried out, after amplification, intermediate-freuqncy signal output module is given all the way and is handled, another way is defeated after A/D acquisition
External FPGA/DSP is arrived out；
The clock generation module carries out A/D sampling to A/D acquisition module for generating sampling clock；
The intermediate-freuqncy signal output module, the two road signals for selecting intermediate frequency conditioning module and A/D acquisition module to export
In signal all the way, give external interface；
The control module, the flatness for intermediate frequency conditioning module are adjusted, and the gain for A/D acquisition module controls,
For the locking phase parameter of clock generation module, the control of the switch for intermediate-freuqncy signal output module to be arranged.
On that basis of the above technical scheme, the intermediate frequency conditioning module includes the first amplifying circuit, the first bandpass filtering electricity
Road, the second amplifying circuit, flatness adjust circuit, first amplifying circuit, the first bandwidth-limited circuit, the second amplification electricity
Road, flatness adjust circuit and are sequentially connected, and are successively once amplified for the intermediate-freuqncy signal to input, is bandpass filtering, secondary
Amplification and flatness are adjusted.
On that basis of the above technical scheme, the A/D acquisition module includes lower frequency changer circuit, low-pass filter circuit, third
Amplifying circuit, the second bandwidth-limited circuit, the 4th amplifying circuit, the conversion circuit of single-ended-to-difference, differential amplifier circuit, difference
Low-pass filter circuit and A/D conversion circuit, the lower frequency changer circuit, low-pass filter circuit, third amplifying circuit, the filter of the second band logical
Wave circuit, the 4th amplifying circuit, the conversion circuit of single-ended-to-difference, differential amplifier circuit, differential low-pass filter circuit and A/D turn
It changes circuit to be sequentially connected, the signal for the output of centering frequency conditioning module carries out down coversion, multistage amplification, filtering and A/D and adopts
Sample, wherein the 4th amplifying circuit after the second bandwidth-limited circuit, which will export signal all the way, gives intermediate-freuqncy signal output module.
On that basis of the above technical scheme, the clock generation module includes locking phase chip and loop filter, locking phase core
Embedded frequency divider R, frequency divider N, Frequency/Phase Discriminator, charge pump and VCO, the frequency divider R, Frequency/Phase Discriminator, electricity
Lotus pump, loop filter, VCO, frequency divider N are sequentially connected, and frequency divider N is connected to Frequency/Phase Discriminator；For in external timing
When inputting frequency divider R, A/D sampling clock is generated by locking phase, and the clock all the way that VCO is exported gives A/D acquisition module.
On that basis of the above technical scheme, the intermediate-freuqncy signal output module include switching circuit, it is the 5th amplifying circuit, quiet
Electricity and surge protection circuit, the switching circuit, the 5th amplifying circuit, electrostatic and surge protection circuit are sequentially connected, for selecting
Wherein signal all the way in logical intermediate frequency conditioning module and two road signals of A/D acquisition module input, then after amplifying by electrostatic and
Surge protection circuit is connected to external interface.
On that basis of the above technical scheme, the control module is connected with intermediate frequency conditioning module, manages mould for centering frequency modulation
The flatness of block adjusts circuit and is controlled；The control module is connected with A/D acquisition module, for A/D acquisition module
The gain of second amplifying circuit is controlled；The control module is connected with clock generation module, for clock generation module
Frequency divider R, frequency divider N, Frequency/Phase Discriminator, charge pump and VCO parameter be configured；The control module and intermediate frequency are believed
Number output module is connected, and carries out signal gating control for the switching circuit to intermediate frequency signal output module.
A kind of implementation method of IF process uses above-mentioned processing circuitry of intermediate frequency to realize the down coversion, more of intermediate-freuqncy signal
Grade combined filter, multistage amplification and flatness is controllable, A/D sampling comprising following steps:
The initial parameter of step 1) external input each module control is to control module；
Step 2) control module be arranged frequency divider R, frequency divider N, Frequency/Phase Discriminator, charge pump and VCO parameter, it is external
Shi Ji is input to frequency divider R, forms phase-locked loop, and VCO exports sampling clock to the A/D conversion circuit of A/D acquisition module；
Step 3) intermediate-freuqncy signal accesses intermediate frequency conditioning module；
The parameter that flatness adjusts circuit is arranged in step 4) control module；
The intermediate-freuqncy signal of step 5) input successively amplifies in intermediate frequency conditioning module, bandpass filtering, amplification and flat
Degree is adjusted；
Signal after the adjusting of step 6) flatness gives the switching circuit of intermediate-freuqncy signal output module all the way, and another way is to A/D
The lower frequency changer circuit of acquisition module；
The gain parameter of the second amplifying circuit of A/D acquisition module is arranged in step 7) control module；
The signal that step 8) inputs to A/D acquisition module successively carry out down coversion, low-pass filtering, amplification, bandpass filtering and
Amplification, signal then continues to carry out single-ended-to-difference conversion, differential amplification, differential low-pass wave in A/D acquisition module all the way
It is converted with A/D, switching circuit of the another output to intermediate-freuqncy signal output module；
Step 9): the switching circuit of control module control intermediate-freuqncy signal output module；
Step 10): switching circuit gates input signal all the way, amplifies, exports after electrostatic and surge protection circuit
To external interface；
Step 11): A/D conversion circuit generates digital signal to external FPGA/DSP；
Step 12): A/D conversion circuit feeds back the whether full inclined information of ADC to control module；
Step 13): if ADC is full partially, control module resets flatness and adjusts the parameter of circuit, A/D acquisition module
Second amplifying circuit gain parameter, into next step；If ADC is not full partially, it is directly entered next step；
Step 14): check whether outside re-enters the gated information of switching circuit to control module；
Step 15): if 9) the external gated information for re-entering switching circuit is entered step to control module；If
12) gated information that switching circuit is not re-entered in outside is entered step to control module.
The invention has the following advantages that not sampled using direct A/D compared with the technical solution of existing IF process
Scheme, but simple and easy " down coversion+flatness adjustment+filtering+amplification+A/D sampling " mode is used, realize one kind
Solution especially suitable for the higher IF signal processing of frequency；It uses down coversion, multistage-combination filters, multistage is put
The anti-aliasing filter of A/D sampling may be implemented in big and flatness control technology.The lower intermediate frequency letter of the frequency generated after down coversion
Number, filtering when can be more expensive come fictitious hosts using cheap LC combined filter circuit SAW filter；It is sampled in A/D
When, it does not need to reduce the requirement to sample clock frequency using expensive high-speed ADC chip；Therefore, it reduces costs, function
Consumption, volume and weight；Carrying out A/D sampling after down coversion simultaneously can produce compared with the digital signal of low rate to subsequent FPGA/DSP
Chip processing also reduces the pressure of the resource distribution of FPGA/DSP chip, to reduce the cost of subsequent processing.
Present invention employs programmable sampling clock generation circuit, can provide in front of down coversion or after down coversion
Frequency signal is to external treatment.
The present invention construct " control module, A/D conversion circuit, flatness adjust circuit, A/D acquisition module second level put
The Dynamic Closed Loop Control circuit of big circuit " composition overflows partially for guaranteeing that ADC is not full.
Detailed description of the invention
Fig. 1: being the whole hardware block diagram of processing circuitry of intermediate frequency of the invention；
Fig. 2: the hardware structure diagram of processing circuitry of intermediate frequency of the invention；
Specific embodiment
Below according to the attached drawing of the diagram preferred embodiment of the present invention, composition of the invention and effect are described in detail.
As depicted in figs. 1 and 2, a kind of processing circuitry of intermediate frequency, including intermediate frequency conditioning module 101, A/D acquisition module 103, when
Clock generation module 105, intermediate-freuqncy signal output module 102 and control module 104.
The intermediate frequency conditioning module 101 is respectively connected with intermediate-freuqncy signal output module 102 and A/D acquisition module 103, is used for
Intermediate-freuqncy signal output module 102 is sent to after intermediate-freuqncy signal is improved respectively and A/D acquisition module 103 is handled；
The A/D acquisition module 103 is connected with intermediate-freuqncy signal output module 102, for by conditioned intermediate-freuqncy signal into
After row down coversion, filtering, amplification, intermediate-freuqncy signal output module 102 being given all the way and is handled, another way is defeated after A/D acquisition
External FPGA/DSP is arrived out；
The clock generation module 105 carries out A/D sampling to A/D acquisition module 103 for generating sampling clock；
The intermediate-freuqncy signal output module 102, for selecting intermediate frequency conditioning module 101 and A/D acquisition module 103 to export
Signal all the way in two road signals gives external interface；
The control module 104, the flatness for intermediate frequency conditioning module 101 is adjusted, for A/D acquisition module 103
Gain control, the switch control for the locking phase parameter of clock generation module 105 to be arranged, for intermediate-freuqncy signal output module 102.
Further, the intermediate frequency conditioning module 101 include the first amplifying circuit 201, the first bandwidth-limited circuit 202,
Second amplifying circuit 203, flatness adjust circuit 204, first amplifying circuit 201, the first bandwidth-limited circuit 202, the
Two amplifying circuits 203, flatness adjust circuit 204 and are sequentially connected, successively once amplified for the intermediate-freuqncy signal to input,
Bandpass filtering, secondary amplification and flatness are adjusted.
Further, the A/D acquisition module 103 includes lower frequency changer circuit 208, low-pass filter circuit 209, third amplification
Circuit 210, the second bandwidth-limited circuit 211, the 4th amplifying circuit 212, single-ended-to-difference conversion circuit 213, differential amplification
Circuit 214, differential low-pass filter circuit 215 and A/D conversion circuit 216, the lower frequency changer circuit 208, low-pass filter circuit
209, the conversion circuit of third amplifying circuit 210, the second bandwidth-limited circuit 211, the 4th amplifying circuit 212, single-ended-to-difference
213, differential amplifier circuit 214, differential low-pass filter circuit 215 and A/D conversion circuit 216 are sequentially connected, and are used for centering frequency modulation
It manages the signal that module 101 exports and carries out down coversion, multistage amplification and filtering and A/D sampling, wherein the second bandwidth-limited circuit
The 4th amplifying circuit 212 afterwards to export all the way signal to intermediate-freuqncy signal output module 102.
Further, the clock generation module 105 include locking phase chip and loop filter 222, locking phase chip again by
Frequency divider R 217, frequency divider N 218, Frequency/Phase Discriminator 219, charge pump 220 and VCO 221 are formed, the frequency divider R
217, Frequency/Phase Discriminator 219, charge pump 220, loop filter 222, VCO 221, frequency divider N 218 are sequentially connected, frequency divider
N 218 is connected to Frequency/Phase Discriminator 219；For generating A/D by locking phase when external timing inputs frequency divider R 217
Sampling clock, and the clock all the way that VCO 221 is exported is to A/D acquisition module 103.
Further, the intermediate-freuqncy signal output module 102 includes switching circuit 205, the 5th amplifying circuit 206, electrostatic
With surge protection circuit 207, the switching circuit 205, the 5th amplifying circuit 206, electrostatic and surge protection circuit 207 successively phase
Even, it for gating the wherein signal all the way in the two road signals that intermediate frequency conditioning module 101 and A/D acquisition module 103 input, is putting
External interface is connected to by electrostatic and surge protection circuit 207 after big；
Further, the control module 104 is connected with intermediate frequency conditioning module 101, for the flat of centering frequency conditioning module
Smooth degree adjusts circuit 204 and is controlled；The control module 104 is connected with A/D acquisition module 103, for A/D acquisition module
The gain of second amplifying circuit (third amplifying circuit 210 and the 4th amplifying circuit 212) controlled；The control module
104 are connected with clock generation module 105, for frequency divider R 217, frequency divider N 218, the frequency discrimination/mirror to clock generation module
The parameter of phase device 219, charge pump 220 and VCO 221 is configured；The control module 104 and intermediate-freuqncy signal output module 102
It is connected, carries out signal gating control for the switching circuit 205 to intermediate frequency signal output module 102.
In conclusion may be implemented through the invention a kind of based on down coversion, multistage-combination filtering, multistage amplification and flat
Spend controllable processing circuitry of intermediate frequency.The circuit can amplify to the higher intermediate-freuqncy signal of the frequency of input, filter peace
After smooth degree is adjusted, down coversion is carried out, so that the higher intermediate-freuqncy signal of frequency is converted to the lower intermediate-freuqncy signal of frequency, then through multistage
Amplification, multiple-stage filtering, the conversion of single-ended-to-difference, differential amplification, differential low-pass wave and A/D sampling, generate digital signal and give
Subsequent digital signal processing apparatus (such as FPGA/DSP chip) processing.
On the basis of above-mentioned processing circuitry of intermediate frequency, as depicted in figs. 1 and 2, the present invention provides a kind of realities of IF process
Existing method, for being based on down coversion, multistage group to the higher intermediate-freuqncy signal of the frequency of input (such as intermediate-freuqncy signal of 140MHz)
Filtering, multistage amplification and flatness control are closed, then carries out A/D sampling and generate digital signal giving subsequent digital signal processing apparatus
(such as FPGA/DSP chip) processing.Wherein, comprising the following steps:
Step 1): the initial parameter of each module control of external input to control module 104；
Step 2): frequency divider R 217, frequency divider N 218, Frequency/Phase Discriminator 219, charge pump is arranged in control module 104
The parameter of 220 and VCO 221, external timing are input to frequency divider R 217, form phase-locked loop, and VCO 221 exports sampling clock
To the A/D conversion circuit 216 of A/D acquisition module 103；Such as when external timing is 10MHz, frequency divider R=10, frequency dividing are set
Device N=100, VCO export 100MHz sampling clock and give A/D conversion circuit；
Step 3): intermediate-freuqncy signal (such as intermediate-freuqncy signal of 140MHz) accesses intermediate frequency conditioning module 101；
Step 4): the parameter that flatness adjusts circuit 204 is arranged in control module 104；
Step 5): the intermediate-freuqncy signal of input successively amplifies in intermediate frequency conditioning module 101, bandpass filtering, amplification and
Flatness is adjusted；
Step 6): flatness adjust after signal (signal of 140MHz) opening to intermediate-freuqncy signal output module 102 all the way
Powered-down road 205, another way (intermediate-freuqncy signal of 140MHz) give the lower frequency changer circuit 208 of A/D acquisition module 103；
Step 7): the gain parameter of the second amplifying circuit 210 and 212 of A/D acquisition module 103 is arranged in control module 104；
Step 8): input to A/D acquisition module 103 signal successively carry out down coversion (such as with local oscillator 109MHz carry out
Down coversion), low-pass filtering, amplification, bandpass filtering and amplification, then signal (intermediate-freuqncy signal of 31MHz) continuation is adopted in A/D all the way
Collect and carry out single-ended-to-difference conversion, differential amplification, differential low-pass wave and A/D conversion in module 103, another way is (in 31MHz
Frequency signal) it is output to the switching circuit 205 of intermediate-freuqncy signal output module 102；
Step 9): the switching circuit 205 of the control intermediate-freuqncy signal output module 102 of control module 104；
Step 10): switching circuit 205 gates (intermediate-freuqncy signal of 140MHz or 31MHz) input signal all the way, is put
Greatly, external interface is output to after electrostatic and surge protection circuit 207；
Step 11): A/D conversion circuit 216 generate digital signal (such as 16 LVDS signals and 2 LVDS with when
Clock) to external FPGA/DSP；
Step 12): A/D conversion circuit 216 feeds back the whether full inclined information of ADC to control module 104.
Step 13): if ADC is full partially, the parameter that control module 104 resets flatness adjusting circuit 204 is (such as right
The intermediate-freuqncy signal of 140MHz decays 5dB), the gain parameter of the second amplifying circuit 210 and 212 of A/D acquisition module 103 it is (such as right
The gain amplifier of the intermediate-freuqncy signal of 31MHz respectively reduces 5dB), into next step；If ADC is not full partially, it is directly entered down
One step；
Step 14): check whether outside re-enters the gated information of switching circuit 205 to control module 104；
Step 15): if the external gated information for re-entering switching circuit 205 is entered step to control module 104
9)；If 12) gated information that switching circuit 205 is not re-entered in outside is entered step to control module 104.
Above for the convenience of explanation, attached drawing mark is assigned to the composition occurred in the attached drawing and attached drawing of preferred illustrated embodiment
Note and title are illustrated, but this is as an embodiment of the present invention, must not be confined to the shape occurred on attached drawing and tax
The title given explains its interest field, the change for the varied shapes that can be predicted from the explanation of invention and plays phase same-action structure
At simple displacement, also in practitioner in order to easily implement in modifiable range, this is self-evident.
Claims (8)
1. a kind of processing circuitry of intermediate frequency, it is characterised in that: including intermediate frequency conditioning module, A/D acquisition module, clock generation module,
Intermediate-freuqncy signal output module and control module.
2. a kind of processing circuitry of intermediate frequency as described in claim 1, it is characterised in that: the intermediate frequency conditioning module and intermediate-freuqncy signal
Output module and A/D acquisition module are respectively connected with, intermediate frequency conditioning module for being sent to after being improved intermediate-freuqncy signal respectively in
Frequency signal output module and A/D acquisition module are handled；
The A/D acquisition module is connected with intermediate-freuqncy signal output module, A/D acquisition module be used for by conditioned intermediate-freuqncy signal into
After row down coversion, filtering, amplification, intermediate-freuqncy signal output module being given all the way and is handled, another way is output to after A/D acquisition
External FPGA/DSP；
The clock generation module carries out A/D sampling to A/D acquisition module for generating sampling clock；
The intermediate-freuqncy signal output module, for selecting in intermediate frequency conditioning module and two road signals of A/D acquisition module output
Signal all the way gives external interface；
The control module, the flatness for intermediate frequency conditioning module are adjusted, and the gain for A/D acquisition module controls, and are used for
The locking phase parameter of clock generation module, the control of the switch for intermediate-freuqncy signal output module are set.
3. a kind of processing circuitry of intermediate frequency as claimed in claim 1 or 2, it is characterised in that: the intermediate frequency conditioning module includes the
One amplifying circuit, the first bandwidth-limited circuit, the second amplifying circuit, flatness adjust circuit, first amplifying circuit, first
Bandwidth-limited circuit, the second amplifying circuit, flatness adjust circuit and are sequentially connected, and successively carry out for the intermediate-freuqncy signal to input
Primary amplification, bandpass filtering, secondary amplification and flatness are adjusted.
4. a kind of processing circuitry of intermediate frequency as claimed in claim 1 or 2, it is characterised in that: the A/D acquisition module includes lower change
Frequency circuit, low-pass filter circuit, third amplifying circuit, the second bandwidth-limited circuit, the 4th amplifying circuit, single-ended-to-difference turn
Change circuit, differential amplifier circuit, differential low-pass filter circuit and A/D conversion circuit, the lower frequency changer circuit, low-pass filtering electricity
Road, third amplifying circuit, the second bandwidth-limited circuit, the 4th amplifying circuit, the conversion circuit of single-ended-to-difference, differential amplification electricity
Road, differential low-pass filter circuit and A/D conversion circuit are sequentially connected, and the signal for the output of centering frequency conditioning module carries out lower change
Frequently, multistage amplification, filtering and A/D sampling, wherein the 4th amplifying circuit after the second bandwidth-limited circuit will export and believe all the way
Number give intermediate-freuqncy signal output module.
5. a kind of processing circuitry of intermediate frequency as claimed in claim 1 or 2, it is characterised in that: the clock generation module includes lock
Phase chip and loop filter are integrated with frequency divider R, frequency divider N, Frequency/Phase Discriminator, charge pump and VCO, institute in locking phase chip
It states frequency divider R, Frequency/Phase Discriminator, charge pump, loop filter, VCO, frequency divider N to be sequentially connected, frequency divider N is connected to mirror
Frequently/phase discriminator；For generating A/D sampling clock by locking phase when external timing inputs frequency divider R, and VCO is exported
Clock gives A/D acquisition module all the way.
6. a kind of processing circuitry of intermediate frequency as claimed in claim 1 or 2, it is characterised in that: the intermediate-freuqncy signal output module packet
Include switching circuit, the 5th amplifying circuit, electrostatic and surge protection circuit, the switching circuit, the 5th amplifying circuit, electrostatic and wave
It gushes protection circuit to be sequentially connected, wherein one in two road signals for gating intermediate frequency conditioning module and the input of A/D acquisition module
Road signal, then external interface is connected to by electrostatic and surge protection circuit after amplifying.
7. a kind of processing circuitry of intermediate frequency as described in claim 1 to 6 any one, it is characterised in that: the control module with
Intermediate frequency conditioning module is connected, and the flatness for centering frequency conditioning module adjusts circuit and controlled；The control module and A/D
Acquisition module is connected, and the gain for the second amplifying circuit to A/D acquisition module controls；The control module and clock
Generation module be connected, for clock generation module frequency divider R, frequency divider N, Frequency/Phase Discriminator, charge pump and VCO ginseng
Number is configured；The control module is connected with intermediate-freuqncy signal output module, for the switch electricity to intermediate frequency signal output module
Road carries out signal gating control.
8. a kind of implementation method of IF process uses processing circuitry of intermediate frequency as claimed in any one of claims 1 to 7 real
The down coversion of existing intermediate-freuqncy signal, multistage-combination filter, multistage amplification and flatness are controllable, A/D sampling comprising following steps:
The initial parameter of step 1) external input each module control is to control module；
Step 2) control module be arranged frequency divider R, frequency divider N, Frequency/Phase Discriminator, charge pump and VCO parameter, external timing
It is input to frequency divider R, forms phase-locked loop, VCO exports sampling clock to the A/D conversion circuit of A/D acquisition module；
Step 3) intermediate-freuqncy signal accesses intermediate frequency conditioning module；
The parameter that flatness adjusts circuit is arranged in step 4) control module；
The intermediate-freuqncy signal of step 5) input successively amplifies in intermediate frequency conditioning module, bandpass filtering, amplification and flatness tune
Section；
Signal after the adjusting of step 6) flatness gives the switching circuit of intermediate-freuqncy signal output module all the way, and another way gives A/D to acquire
The lower frequency changer circuit of module；
The gain parameter of the second amplifying circuit of A/D acquisition module is arranged in step 7) control module；
The signal that step 8) inputs to A/D acquisition module successively carries out down coversion, low-pass filtering, amplification, bandpass filtering and amplification,
Signal then continues to carry out single-ended-to-difference conversion, differential amplification, differential low-pass wave and A/D in A/D acquisition module all the way
Conversion, switching circuit of the another output to intermediate-freuqncy signal output module；
Step 9): the switching circuit of control module control intermediate-freuqncy signal output module；
Step 10): switching circuit gates input signal all the way, amplifies, and is output to after electrostatic and surge protection circuit outer
Portion's interface；
Step 11): A/D conversion circuit generates digital signal to external FPGA/DSP；
Step 12): A/D conversion circuit feeds back the whether full inclined information of ADC to control module；
Step 13): if ADC is full partially, control module reset flatness adjust the parameter of circuit, A/D acquisition module two
The gain parameter of grade amplifying circuit, into next step；If ADC is not full partially, it is directly entered next step；
Step 14): check whether outside re-enters the gated information of switching circuit to control module；
Step 15): if 9) the external gated information for re-entering switching circuit is entered step to control module；If external
The gated information of switching circuit is not re-entered to control module, is entered step 12).
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102323600A (en) * | 2011-07-01 | 2012-01-18 | 上海迦美信芯通讯技术有限公司 | System architecture of dual-channel navigation radio-frequency receiver |
| CN204103932U (en) * | 2014-11-06 | 2015-01-14 | 南京长峰航天电子科技有限公司 | Phase amplitude-matched multi-channel radio frequency simulator |
| CN107144733A (en) * | 2017-06-07 | 2017-09-08 | 中国电子科技集团公司第四十研究所 | A kind of device and method that spectrum analysis function is realized on vector network analyzer |
| CN107196673A (en) * | 2017-06-05 | 2017-09-22 | 中国电子科技集团公司第四十研究所 | A kind of signal analysis device and method based on any variable number intermediate frequency |
-
2018
- 2018-11-19 CN CN201811376159.8A patent/CN109547023B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102323600A (en) * | 2011-07-01 | 2012-01-18 | 上海迦美信芯通讯技术有限公司 | System architecture of dual-channel navigation radio-frequency receiver |
| CN204103932U (en) * | 2014-11-06 | 2015-01-14 | 南京长峰航天电子科技有限公司 | Phase amplitude-matched multi-channel radio frequency simulator |
| CN107196673A (en) * | 2017-06-05 | 2017-09-22 | 中国电子科技集团公司第四十研究所 | A kind of signal analysis device and method based on any variable number intermediate frequency |
| CN107144733A (en) * | 2017-06-07 | 2017-09-08 | 中国电子科技集团公司第四十研究所 | A kind of device and method that spectrum analysis function is realized on vector network analyzer |
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