CN109545675B - Preparation method of thin film transistor array substrate - Google Patents
Preparation method of thin film transistor array substrate Download PDFInfo
- Publication number
- CN109545675B CN109545675B CN201811259129.9A CN201811259129A CN109545675B CN 109545675 B CN109545675 B CN 109545675B CN 201811259129 A CN201811259129 A CN 201811259129A CN 109545675 B CN109545675 B CN 109545675B
- Authority
- CN
- China
- Prior art keywords
- film
- layer
- copper
- carbon composite
- composite film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 80
- 239000010409 thin film Substances 0.000 title claims abstract description 53
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 466
- 238000000034 method Methods 0.000 claims abstract description 85
- 238000000151 deposition Methods 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 273
- 239000002131 composite material Substances 0.000 claims description 150
- AHADSRNLHOHMQK-UHFFFAOYSA-N methylidenecopper Chemical compound [Cu].[C] AHADSRNLHOHMQK-UHFFFAOYSA-N 0.000 claims description 135
- 238000009832 plasma treatment Methods 0.000 claims description 58
- 238000004519 manufacturing process Methods 0.000 claims description 42
- 239000011521 glass Substances 0.000 claims description 36
- 150000001875 compounds Chemical class 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 229910015269 MoCu Inorganic materials 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- -1 MoNb Inorganic materials 0.000 claims description 4
- 229910016027 MoTi Inorganic materials 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 239000010949 copper Substances 0.000 description 132
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 239000007787 solid Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
Abstract
The embodiment of the invention discloses a preparation method of a thin film transistor array substrate. The method comprises the step of depositing a C film on the Cu metal film layer after the Cu metal film layer is formed on the grid electrode layer and before a yellow light process and an etching process. In the embodiment of the invention, the Cu film is isolated from the outside, and the oxidation of the Cu film in the subsequent yellow light process and etching process can be avoided, so that the surface resistivity of the Cu film is reduced, the ESD phenomenon generated by the Cu film is avoided, and the display effect of the thin film transistor array substrate is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor materials, in particular to a preparation method of a thin film transistor array substrate.
Background
With the development of flat panel display technology, people pursue higher and higher display size, resolution and picture refresh rate, so copper is adopted to replace aluminum as a conductive metal material.
In the existing array substrate process method, after the deposition of a Cu film is finished, a yellow light process and an etching process are carried out, the Cu film is exposed in the air, the surface layer of the Cu film is partially oxidized, the Cu film is exposed in the air for more than 30min, the surface resistivity of the Cu film is increased by more than 30%, and thus the resistivity of the Cu line is increased; and CuO generated on the Cu filmxAnd Cu (OH)xAn Electro-Static discharge (ESD) phenomenon may be caused, which affects the display effect of the TFT device; the thicker the Cu film, the larger the grain size, the larger the surface roughness, and the larger the gap of the grain boundary, so that part of O will be formed in the subsequent process2And H2O permeates into the film layer along the grain boundary gap, the oxidation of the surface Cu film is accelerated, electrostatic breakdown is generated or local parasitic capacitance is generated, and the display effect of the TFT device is further influenced.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a thin film transistor array substrate, which can prevent a Cu film from being oxidized during a subsequent yellow light process and an etching process, thereby reducing the surface resistivity of the Cu film, preventing the Cu film from generating an ESD (electro-static discharge) phenomenon and improving the display effect of the thin film transistor array substrate.
In order to solve the above problems, a first aspect of the present application provides a method for manufacturing a thin film transistor array substrate, the method including a step of depositing a C film on a Cu metal thin film layer after forming the Cu metal thin film layer on a gate electrode layer and before a photolithography process and an etching process.
Further, the method comprises:
depositing a grid electrode layer on a glass substrate, and depositing a Cu film above the grid electrode layer;
and depositing a C film on the Cu film to serve as a Cu film protective layer.
Further, the method further comprises:
processing the C film to form a copper-carbon composite film layer;
carrying out plasma treatment on the copper-carbon composite film layer to remove a C film above a Cu film in the copper-carbon composite film layer;
depositing to form a gate insulating layer;
and sequentially manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer.
Further, the processing the C film to manufacture the copper-carbon composite film layer includes:
manufacturing a photoresist pattern;
carrying out plasma treatment on the C film on the glass substrate, so that the C film without the protection of the photoresist generates a gas compound;
and carrying out wet etching on the Cu film and photoresist removing process to form the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
h is carried out on the copper-carbon composite film layer2And performing plasma treatment to enable the C film and H + above the Cu film in the copper-carbon composite film layer to generate gasified C-H compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
performing N on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and the N + above the Cu film in the copper-carbon composite film layer to generate gasified N-C compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
carrying out O treatment on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and O + above the Cu film in the copper-carbon composite film layer to generate a gasified O-C compound so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of depositing to form a gate insulation layer includes:
and removing the C film on the Cu film in the copper-carbon composite film layer, and performing gate insulation layer deposition after the Cu film is exposed.
Further, the step of depositing a gate electrode layer on the glass substrate and depositing a Cu film on the gate electrode layer includes:
and depositing a MoCu composite film layer on the glass substrate, wherein the Mo film is arranged below the Cu film, the Mo film is used as a grid electrode layer, and the Cu film is used as a conductive function layer.
Further, the material of the gate electrode layer is MoTi, MoNb, Ti, Ta or W.
Further, the step of depositing the MoCu composite film layer on the glass substrate includes:
and depositing the MoCu composite film layer on the glass substrate by using a Physical Vapor Deposition (PVD) sputtering process.
Further, the step of depositing a C film as a Cu film protection layer on the Cu film includes:
depositing a layer of C film on the Cu film by a sputtering process to serve as a Cu film protective layer, wherein the thickness of the C film is
Further, the Mo film thickness is 100-500 angstroms.
In a second aspect, the present application provides a method for manufacturing a thin film transistor array substrate, the method comprising:
depositing a grid electrode layer on a glass substrate, and depositing a Cu film above the grid electrode layer;
depositing a layer of C film on the Cu film to serve as a Cu film protective layer;
processing the C film to form a copper-carbon composite film layer;
carrying out plasma treatment on the copper-carbon composite film layer to remove a C film above a Cu film in the copper-carbon composite film layer;
depositing to form a gate insulating layer;
and sequentially manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer.
Further, the processing the C film to manufacture the copper-carbon composite film layer includes:
manufacturing a photoresist pattern;
carrying out plasma treatment on the C film on the glass substrate, so that the C film without the protection of the photoresist generates a gas compound;
and carrying out wet etching on the Cu film and photoresist removing process to form the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
h is carried out on the copper-carbon composite film layer2And performing plasma treatment to enable the C film and H + above the Cu film in the copper-carbon composite film layer to generate gasified C-H compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
performing N on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and the N + above the Cu film in the copper-carbon composite film layer to generate gasified N-C compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes:
carrying out O treatment on the copper-carbon composite film layer2Plasma treatment is carried out, so that a C film and O + above a Cu film in the copper-carbon composite film layer generate gasified O-C compoundsSo as to remove the C film on the Cu film in the copper-carbon composite film layer.
Further, the step of depositing a gate electrode layer on the glass substrate and depositing a Cu film on the gate electrode layer includes:
and depositing a MoCu composite film layer on the glass substrate, wherein the Mo film is arranged below the Cu film, the Mo film is used as a grid electrode layer, and the Cu film is used as a conductive function layer.
The method comprises the step of depositing a C film on the Cu metal film layer after the Cu metal film layer is formed on the grid electrode layer and before a yellow light process and an etching process. In the embodiment of the invention, the Cu film is isolated from the outside, and the oxidation of the Cu film in the subsequent yellow light process and etching process can be avoided, so that the surface resistivity of the Cu film is reduced, the ESD phenomenon generated by the Cu film is avoided, and the display effect of the thin film transistor array substrate is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating an embodiment of a method for manufacturing a thin film transistor array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a thin film transistor array substrate according to a method for manufacturing the thin film transistor array substrate according to an embodiment of the present invention after depositing a MoCu composite film layer on a glass substrate;
fig. 3 is a schematic structural diagram of a thin film transistor array substrate according to a method for manufacturing the thin film transistor array substrate provided by the embodiment of the present invention, in which a C film is deposited on a Cu film as a Cu film protection layer;
fig. 4 is a schematic diagram illustrating a copper-carbon composite film layer in a method for manufacturing a thin film transistor array substrate according to an embodiment of the present invention2Plasma treatment is carried out, so that C film and H + above the Cu film in the copper-carbon composite film layer generate gasified C-H compounds to removeA structure schematic diagram of a C film on a Cu film in the copper-carbon composite film layer;
fig. 5 is a schematic structural diagram illustrating a Cu film wet etching process and a photoresist removal process performed in the method for manufacturing a thin film transistor array substrate according to the embodiment of the present invention after a copper-carbon composite film layer is formed;
fig. 6 is a schematic diagram illustrating a copper-carbon composite film layer in a method for manufacturing a thin film transistor array substrate according to an embodiment of the present invention2Plasma treatment is carried out to remove the C film on the Cu film in the copper-carbon composite film layer;
fig. 7 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present invention after a gate insulating layer is deposited.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Thin-film transistors (TFTs) are one type of field effect transistors and are typically fabricated by depositing various Thin films, such as semiconductor active layers, dielectric layers, and metal electrode layers, on a substrate. The thin film transistor has a very important role in the operation performance of the display device.
The embodiment of the invention provides a preparation method of a thin film transistor array substrate, which comprises the step of depositing a C film on a Cu metal thin film layer after the Cu metal thin film layer is formed on a grid electrode layer and before a yellow light process and an etching process.
The method comprises the step of depositing a C film on the Cu metal film layer after the Cu metal film layer is formed on the grid electrode layer and before a yellow light process and an etching process. In the embodiment of the invention, the Cu film is isolated from the outside, and the oxidation of the Cu film in the subsequent yellow light process and etching process can be avoided, so that the surface resistivity of the Cu film is reduced, the ESD phenomenon generated by the Cu film is avoided, and the display effect of the thin film transistor array substrate is improved.
Further, the method in the embodiment of the invention comprises the following steps: depositing a grid electrode layer on a glass substrate, and depositing a Cu film above the grid electrode layer; and depositing a C film on the Cu film to serve as a Cu film protective layer.
Further, the method in the embodiment of the present invention further includes: processing the C film to form a copper-carbon composite film layer; carrying out plasma treatment on the copper-carbon composite film layer to remove a C film above a Cu film in the copper-carbon composite film layer; depositing to form a gate insulating layer; and sequentially manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer.
Further, the processing the C film to manufacture the copper-carbon composite film layer includes: manufacturing a photoresist pattern; carrying out plasma treatment on the C film on the glass substrate, so that the C film without the protection of the photoresist generates a gas compound; and carrying out wet etching on the Cu film and photoresist removing process to form the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: h is carried out on the copper-carbon composite film layer2And performing plasma treatment to enable the C film and H + above the Cu film in the copper-carbon composite film layer to generate gasified C-H compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: performing N on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and the N + above the Cu film in the copper-carbon composite film layer to generate gasified N-C compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: carrying out O treatment on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and O + above the Cu film in the copper-carbon composite film layer to generate a gasified O-C compound so as to remove the C film above the Cu film in the copper-carbon composite film layer.
Further, the step of depositing to form a gate insulation layer includes: and removing the C film on the Cu film in the copper-carbon composite film layer, and performing gate insulation layer deposition after the Cu film is exposed.
Furthermore, the manufacturing method of the source drain electrode layer is consistent with the manufacturing method of the grid electrode layer.
Further, the step of depositing a gate electrode layer on the glass substrate and depositing a Cu film on the gate electrode layer includes: and depositing a MoCu composite film layer on the glass substrate, wherein the Mo film is arranged below the Cu film, the Mo film is used as a grid electrode layer, and the Cu film is used as a conductive function layer.
Further, the material of the gate electrode layer is MoTi, MoNb, Ti, Ta or W. Further, the Mo film thickness is 100-500 angstroms.
Further, the step of depositing the MoCu composite film layer on the glass substrate includes: and depositing the MoCu composite film layer on the glass substrate by using a Physical Vapor Deposition (PVD) sputtering process.
Further, the step of depositing a C film as a Cu film protection layer on the Cu film includes: depositing a layer of C film on the Cu film by a sputtering process to serve as a Cu film protective layer, wherein the thickness of the C film is
As shown in fig. 1, which is a schematic view of an embodiment of a method for manufacturing a thin film transistor array substrate according to an embodiment of the present invention, the method includes:
s101, depositing and forming a gate electrode layer on the glass substrate, and depositing and forming a Cu film above the gate electrode layer.
Wherein, the step of depositing a gate electrode layer on the glass substrate, and depositing a Cu film on the gate electrode layer may further include: and depositing the MoCu composite film layer on the glass substrate.
Further, as shown in fig. 2, the step of depositing the MoCu composite film layer on the glass substrate may specifically include: the MoCu composite film layer was deposited on the glass substrate using a Physical Vapor Deposition (PVD) sputtering process. Wherein, the Mo film is under the Cu film, the Mo film is used as the gate electrode layer, and the thickness of the Mo film can be 100-500 angstroms. The Cu film is a conductive functional layer, and the thickness is not limited, and may be a Cu film thickness conventionally used in the art. The gate electrode layer material may be MoTi, MoNb, Ti, Ta, or W, but is not limited thereto.
S102, depositing a C film on the Cu film to serve as a Cu film protective layer.
Specifically, as shown in fig. 3, a C film may be deposited as a Cu film protective layer on the Cu film by a sputtering process, the C film having a thickness
The sputtering process is a process of bombarding the surface of a solid with particles (ions or neutral atoms, molecules) with certain energy, so that the atoms or molecules near the surface of the solid obtain enough energy to finally escape from the surface of the solid. Sputtering can only be performed under a certain vacuum condition. The sputtering process is a conventional technique in the art and how to deposit a C film on top of a Cu film using the sputtering process is not described in detail herein.
In addition, in the embodiment of the present invention, in order to achieve a good effect of protecting the Cu film and avoid increasing difficulty of the C film being gasified into the gaseous compound at the later stage, the C film thickness is preferably selected
And S103, processing the C film to form a copper-carbon composite film layer.
Wherein, should handle C membrane, form the step of copper carbon composite film layer and include: manufacturing a photoresist pattern; carrying out plasma treatment on the C film on the glass substrate, so that the C film without the protection of the photoresist generates a gas compound; and carrying out wet etching on the Cu film and photoresist removing process to form the copper-carbon composite film layer.
Further, in the step of plasma treating the C film on the glass substrate so that the C film without the resist protection generates a gas compound, H may be used2Plasma treatment, N2Plasma treatment or O2Plasma treatment, etc.
Specifically, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer may include: h is carried out on the copper-carbon composite film layer2And performing plasma treatment to enable the C film and H + above the Cu film in the copper-carbon composite film layer to generate gasified C-H compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer, as shown in fig. 4. Or, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: carrying out N on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and the N + above the Cu film in the copper-carbon composite film layer to generate gasified N-C compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer. Or, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer includes: carrying out O treatment on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and O + above the Cu film in the copper-carbon composite film layer to generate a gasified O-C compound so as to remove the C film above the Cu film in the copper-carbon composite film layer.
After the C film without the protection of the photoresist is made to generate a gaseous compound, as shown in fig. 5, a Cu film wet etching and photoresist removal process is performed to form a copper-carbon composite film layer, at this time, the Cu film and the C film in the channel above the glass substrate are etched away, and the Cu film and the C film at both ends of the channel are retained.
And S104, carrying out plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer.
Similarly, the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer may also use H2Plasma treatment, N2Plasma treatment or O2And (4) carrying out plasma treatment. Specifically, the C film on the glass substrate may be plasma-treated in step S103 so that there is no lightThe implementation of the step of generating the gas compound by the resist-protected C film is not described herein. As shown in fig. 6, the copper-carbon composite film layer is again subjected to H2And (3) performing plasma treatment to remove the C film on the Cu film in the copper-carbon composite film layer.
And S105, depositing to form a gate insulating layer.
The gate insulating layer is referred to as a GI layer, which is formed by Deposition of a GI Deposition process in LTPS. GI is an insulating layer between the Gate metal and the semiconductor Si in the TFT, usually SiNx/SiOx called Gate Insulator.
Specifically, as shown in fig. 7, after the C film on the Cu film in the copper-carbon composite film layer is removed and the Cu film is exposed, the gate insulating layer is deposited.
And S106, manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer in sequence.
In the embodiment of the present invention, the steps of manufacturing the semiconductor layer, the source/drain electrode layer, the passivation layer, and the pixel electrode layer may refer to the prior art, and are not limited herein. And sequentially manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer to form the thin film transistor array substrate.
The method comprises the steps of depositing a C film on the Cu metal thin film layer after the Cu metal thin film layer is formed on the grid electrode layer and before a yellow light process and an etching process, and gasifying and reacting the C film by utilizing the characteristic that the C film can be gasified and reacted, so that the C film cannot be remained on a product, the surface resistivity of the Cu film is reduced, the phenomenon that the Cu film generates ESD (electro-static discharge) is avoided, and the display effect of the thin film transistor array substrate is improved.
The above detailed description is provided for the method for manufacturing the thin film transistor array substrate according to the embodiment of the present invention, and the specific examples are applied herein to explain the principle and the embodiment of the present invention, and the description of the above embodiments is only used to help understanding the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (17)
1. The preparation method of the thin film transistor array substrate is characterized by comprising the steps of depositing a C film on a Cu metal thin film layer after the Cu metal thin film layer is formed on a grid electrode layer and before a yellow light process and an etching process;
the preparation method of the thin film transistor array substrate comprises the following steps:
depositing a grid electrode layer on a glass substrate, and depositing a Cu film above the grid electrode layer;
depositing a layer of C film on the Cu film to serve as a Cu film protective layer;
the preparation method of the thin film transistor array substrate further comprises the following steps:
processing the C film to form a copper-carbon composite film layer;
carrying out plasma treatment on the copper-carbon composite film layer to remove a C film above a Cu film in the copper-carbon composite film layer;
depositing to form a gate insulating layer;
and sequentially manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer.
2. The method for manufacturing the thin film transistor array substrate according to claim 1, wherein the step of processing the C film to manufacture the copper-carbon composite film layer comprises:
manufacturing a photoresist pattern;
carrying out plasma treatment on the C film on the glass substrate, so that the C film without the protection of the photoresist generates a gas compound;
and carrying out wet etching on the Cu film and photoresist removing process to form the copper-carbon composite film layer.
3. The method for manufacturing a thin film transistor array substrate according to claim 1, wherein the step of performing plasma treatment on the copper-carbon composite film layer to remove a C film on a Cu film in the copper-carbon composite film layer comprises:
h is carried out on the copper-carbon composite film layer2And performing plasma treatment to enable the C film and H + above the Cu film in the copper-carbon composite film layer to generate gasified C-H compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
4. The method for manufacturing a thin film transistor array substrate according to claim 1, wherein the step of performing plasma treatment on the copper-carbon composite film layer to remove a C film on a Cu film in the copper-carbon composite film layer comprises:
performing N on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and the N + above the Cu film in the copper-carbon composite film layer to generate gasified N-C compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
5. The method for manufacturing a thin film transistor array substrate according to claim 1, wherein the step of performing plasma treatment on the copper-carbon composite film layer to remove a C film on a Cu film in the copper-carbon composite film layer comprises:
carrying out O treatment on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and O + above the Cu film in the copper-carbon composite film layer to generate a gasified O-C compound so as to remove the C film above the Cu film in the copper-carbon composite film layer.
6. The method for manufacturing a thin film transistor array substrate according to any one of claims 3 to 5, wherein the step of depositing and forming a gate insulating layer comprises:
and removing the C film on the Cu film in the copper-carbon composite film layer, and performing gate insulation layer deposition after the Cu film is exposed.
7. The method for preparing a thin film transistor array substrate of claim 1, wherein the step of depositing a gate electrode layer on a glass substrate and depositing a Cu film over the gate electrode layer comprises:
and depositing a MoCu composite film layer on the glass substrate, wherein the Mo film is arranged below the Cu film, the Mo film is used as a grid electrode layer, and the Cu film is used as a conductive function layer.
8. The method of claim 1, wherein the gate electrode layer is made of MoTi, MoNb, Ti, Ta or W.
9. The method for manufacturing a thin film transistor array substrate according to claim 7, wherein the step of depositing the MoCu composite film layer on the glass substrate comprises:
and depositing the MoCu composite film layer on the glass substrate by using a Physical Vapor Deposition (PVD) sputtering process.
10. The method for manufacturing a thin film transistor array substrate of claim 1, wherein the step of depositing a C film as a Cu film protection layer on the Cu film comprises:
and depositing a layer of C film on the Cu film by using a sputtering process to serve as a Cu film protection layer, wherein the thickness of the C film is 50A-200A.
11. The method as claimed in claim 7, wherein the thickness of the Mo film is 100-500 angstroms.
12. A preparation method of a thin film transistor array substrate is characterized by comprising the following steps:
depositing a grid electrode layer on a glass substrate, and depositing a Cu film above the grid electrode layer;
depositing a layer of C film on the Cu film to serve as a Cu film protective layer;
processing the C film to form a copper-carbon composite film layer;
carrying out plasma treatment on the copper-carbon composite film layer to remove a C film above a Cu film in the copper-carbon composite film layer;
depositing to form a gate insulating layer;
and sequentially manufacturing the semiconductor layer, the source drain electrode layer, the passivation layer and the pixel electrode layer.
13. The method for manufacturing a thin film transistor array substrate according to claim 12, wherein the C film is processed to manufacture a copper-carbon composite film layer, comprising:
manufacturing a photoresist pattern;
carrying out plasma treatment on the C film on the glass substrate, so that the C film without the protection of the photoresist generates a gas compound;
and carrying out wet etching on the Cu film and photoresist removing process to form the copper-carbon composite film layer.
14. The method for manufacturing a thin film transistor array substrate according to claim 12, wherein the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer comprises:
h is carried out on the copper-carbon composite film layer2And performing plasma treatment to enable the C film and H + above the Cu film in the copper-carbon composite film layer to generate gasified C-H compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
15. The method for manufacturing a thin film transistor array substrate according to claim 12, wherein the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer comprises:
performing N on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and the N + above the Cu film in the copper-carbon composite film layer to generate gasified N-C compounds so as to remove the C film above the Cu film in the copper-carbon composite film layer.
16. The method for manufacturing a thin film transistor array substrate according to claim 12, wherein the step of performing plasma treatment on the copper-carbon composite film layer to remove the C film on the Cu film in the copper-carbon composite film layer comprises:
carrying out O treatment on the copper-carbon composite film layer2And (3) carrying out plasma treatment to enable the C film and O + above the Cu film in the copper-carbon composite film layer to generate a gasified O-C compound so as to remove the C film above the Cu film in the copper-carbon composite film layer.
17. The method for preparing a thin film transistor array substrate of claim 12, wherein the step of depositing a gate electrode layer on a glass substrate and depositing a Cu film over the gate electrode layer comprises:
and depositing a MoCu composite film layer on the glass substrate, wherein the Mo film is arranged below the Cu film, the Mo film is used as a grid electrode layer, and the Cu film is used as a conductive function layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811259129.9A CN109545675B (en) | 2018-10-26 | 2018-10-26 | Preparation method of thin film transistor array substrate |
| PCT/CN2019/071847 WO2020082624A1 (en) | 2018-10-26 | 2019-01-16 | Method for preparing thin film transistor array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811259129.9A CN109545675B (en) | 2018-10-26 | 2018-10-26 | Preparation method of thin film transistor array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109545675A CN109545675A (en) | 2019-03-29 |
| CN109545675B true CN109545675B (en) | 2020-10-13 |
Family
ID=65845730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811259129.9A Active CN109545675B (en) | 2018-10-26 | 2018-10-26 | Preparation method of thin film transistor array substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109545675B (en) |
| WO (1) | WO2020082624A1 (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001135822A (en) * | 1999-11-04 | 2001-05-18 | Matsushita Electric Ind Co Ltd | Thin film transistor, manufacturing method thereof and liquid crystal display device |
| US8043891B2 (en) * | 2009-06-05 | 2011-10-25 | Shanghai Lexvu Opto Microelectronics Technology Co., Ltd. | Method of encapsulating a wafer level microdevice |
| US20150295058A1 (en) * | 2012-12-28 | 2015-10-15 | Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) | Thin-film transistor and manufacturing method therefor |
| TWI503276B (en) * | 2013-03-13 | 2015-10-11 | Academia Sinica | Method for manufacturing graphene film and graphene channel of transistor |
| KR102169861B1 (en) * | 2013-11-07 | 2020-10-26 | 엘지디스플레이 주식회사 | A array substrate and method of fabricating the same |
| CN103545221B (en) * | 2013-11-14 | 2018-10-09 | 广州新视界光电科技有限公司 | Metal oxide thin-film transistor and preparation method thereof |
| DE102016109349A1 (en) * | 2016-05-20 | 2017-11-23 | Infineon Technologies Ag | CHIP HOUSING, METHOD FOR MAKING A CHIP HOUSING, AND METHOD FOR FORMING ELECTRICAL CONTACT |
| CN106876451A (en) * | 2017-03-07 | 2017-06-20 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte |
| CN108110060A (en) * | 2017-12-12 | 2018-06-01 | 合肥京东方显示技术有限公司 | Thin film transistor (TFT) and preparation method thereof, array substrate and display device |
-
2018
- 2018-10-26 CN CN201811259129.9A patent/CN109545675B/en active Active
-
2019
- 2019-01-16 WO PCT/CN2019/071847 patent/WO2020082624A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| CN109545675A (en) | 2019-03-29 |
| WO2020082624A1 (en) | 2020-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9666727B2 (en) | Display device | |
| KR20140037808A (en) | Method for fabricating array substrate, array substrate and display device | |
| US10818706B2 (en) | Production method of thin-film transistor, thin-film transistor, array substrate, and display panel | |
| US10090414B2 (en) | TFT substrate manufacture method | |
| JP2007220816A (en) | Thin-film transistor and manufacturing method thereof | |
| CN106684037A (en) | Preparation method for TFT array for optimizing 4M process | |
| US9741751B2 (en) | Array substrate fabricating method | |
| US10431694B2 (en) | Thin film transistor, display apparatus having the same, and fabricating method thereof | |
| CN110867458A (en) | Metal oxide semiconductor thin film transistor array substrate and manufacturing method thereof | |
| US20160351725A1 (en) | Thin film transistor and method of manufacturing the same | |
| CN105633170A (en) | Metal oxide thin film transistor and preparation method therefor, array substrate and display apparatus | |
| US9159746B2 (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| US10593807B2 (en) | Array substrate and fabricating method thereof | |
| CN109712930A (en) | Display base plate and preparation method thereof, display device | |
| CN102738243B (en) | Transistor, array base palte and manufacture method, liquid crystal panel and display device | |
| WO2020252955A1 (en) | Array substrate preparation method and array substrate preparation system | |
| US9508762B2 (en) | Array substrate, method of manufacturing array substrate and display device | |
| US20200220020A1 (en) | Thin-film transistor and method for preparing the same, display substrate and display device | |
| CN107369719B (en) | Oxide thin film transistor pure copper composite structure source-drain electrode and preparation method thereof | |
| US20180175178A1 (en) | Method of manufacturing oxide thin film transistor | |
| CN109545675B (en) | Preparation method of thin film transistor array substrate | |
| WO2019095408A1 (en) | Array substrate, manufacturing method thereof, and display panel | |
| CN109616418B (en) | Thin film transistor, display substrate, manufacturing method of display substrate and display device | |
| CN107425077B (en) | Thin film transistor, manufacturing method thereof and display device | |
| JPS6083373A (en) | Thin film transistor array and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |