CN109525243B - Frequency divider circuit with anti-radiation function - Google Patents
Frequency divider circuit with anti-radiation function Download PDFInfo
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- CN109525243B CN109525243B CN201811434619.8A CN201811434619A CN109525243B CN 109525243 B CN109525243 B CN 109525243B CN 201811434619 A CN201811434619 A CN 201811434619A CN 109525243 B CN109525243 B CN 109525243B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/002—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
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Abstract
The invention discloses a frequency divider circuit with an anti-irradiation function, which comprises more than three frequency divider units and a voter unit, wherein the output end of each frequency divider unit is respectively connected with the input end of the voter unit, and the output end of the voter unit is connected to the input end of each frequency divider unit in a feedback manner. The invention has the advantages of simple structure, low cost, irradiation resistance, low soft error rate and the like.
Description
Technical Field
The invention relates to the technical field of frequency dividers, in particular to a frequency divider circuit with an anti-radiation function.
Background
In order to meet the demands for higher integration, more functions and lower power integrated circuits, the feature size and operating voltage of the integrated circuits are continuously reduced, resulting in a drastic increase in the radiation sensitivity of the circuits. The frequency divider is used as an important component of an integrated circuit, the frequency divider in the prior art generally does not have an anti-irradiation function, and once the output of the frequency divider is influenced by a single event effect due to the influence of irradiation to cause an error, the performance of the circuit can be seriously influenced. Therefore, it is desirable to provide a frequency divider circuit with an anti-radiation function to improve the anti-radiation performance of the frequency divider and reduce the soft error rate.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the frequency divider circuit with the anti-radiation function, which has the advantages of simple structure, low cost, anti-radiation function and low soft error rate.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a frequency divider circuit with an anti-radiation function comprises more than three frequency divider units and a voter unit, wherein the output end of each frequency divider unit is respectively connected with the input end of the voter unit, and the output end of the voter unit is connected to the input end of each frequency divider unit in a feedback mode.
As a further improvement of the invention: and the frequency divider units respectively receive input signals, divide the frequency of the input signals and output the signals to the voter units, the voter units shield frequency division signals which are different from other signals in the frequency division signals output by the frequency divider units, and final frequency division signals are output and fed back to the frequency divider units respectively.
As a further improvement of the invention: and the input end of the frequency divider unit is connected with the output end.
As a further improvement of the invention: the frequency divider unit comprises a trigger circuit and a NAND gate circuit, and the output end of the trigger circuit is connected to the input end of the trigger circuit through the NAND gate circuit.
As a further improvement of the invention: the trigger circuit comprises a plurality of D triggers which are connected in sequence.
As a further improvement of the invention: the voter unit receives three paths of frequency division signals output by the three frequency division units, and outputs the same two paths of frequency division signals as final frequency division signals to shield different paths of frequency division signals.
As a further improvement of the invention: the voting unit comprises three transistor branches and an inverter circuit, wherein the upper branch of each transistor branch comprises two PMOS (P-channel metal oxide semiconductor) tubes connected in series, the lower branch of each transistor branch comprises two NMOS (N-channel metal oxide semiconductor) tubes connected in series, and a middle node between the upper branch and the lower branch of each transistor branch is connected to the input end of the inverter circuit.
As a further improvement of the invention: and each transistor branch is respectively connected with two paths of signals in the three paths of frequency division signals.
As a further improvement of the invention: the phase inverter circuit comprises a PMOS tube and an NMOS tube which are connected in series.
Compared with the prior art, the invention has the advantages that: the frequency divider circuit with the irradiation resistance function can realize a frequency divider which is forcedly updated based on a negative feedback structure by forming a closed loop by a plurality of frequency divider units and a voter unit, can output a correct state by the voter unit when high-energy particles hit a certain frequency divider unit, and can feed back the correct state to an incorrect frequency divider unit, so that the state of the incorrect frequency divider unit can be updated to the correct state, the single event effect of the frequency divider circuit caused by irradiation is effectively inhibited, and the soft error rate is reduced.
Drawings
Fig. 1 is a schematic diagram of the structural principle of the frequency divider circuit with the radiation-resistant function according to the present embodiment.
Fig. 2 is a schematic circuit structure diagram of a specific application embodiment of the frequency divider circuit with an anti-radiation function according to the present invention.
Fig. 3 is a schematic diagram of a circuit structure of a frequency divider unit used in an embodiment of the present invention.
Fig. 4 is a schematic circuit diagram of a voter unit employed in an embodiment of the present invention.
Illustration of the drawings: 1. a frequency divider unit; 2. a voter unit.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
As shown in fig. 1, the frequency divider circuit with an anti-radiation function in this embodiment includes three or more frequency divider units 1 and one voter unit 2, the output end of each frequency divider unit 1 is connected to the input end of the voter unit 2, the output end of the voter unit 2 is connected to the input end of each frequency divider unit 1 in a feedback manner, and the voter unit 2 shields the frequency-divided signals, which are different from the other signals, in each frequency-divided signal output by each frequency divider unit 1.
In the embodiment, a plurality of frequency divider units 1 and a voter unit 2 form a frequency divider circuit, the output of each frequency divider unit 1 is input to the voter unit 2, and the output of the voter unit 2 is fed back to the input end of each frequency divider unit 1 to form a closed loop, so that a frequency divider with forced update can be realized based on a negative feedback structure, when high-energy particles hit any one frequency divider unit 1, since other frequency divider units 1 are in a normal working state, a correct state can be output through the voter unit 2, and simultaneously, the correct state can be fed back to the wrong frequency divider unit 1, so that the state of the wrong frequency divider unit 1 can be updated to the correct state, a single event effect caused by irradiation of the frequency divider circuit can be effectively inhibited, and the soft error rate of the frequency divider circuit can be reduced.
In this embodiment, each frequency divider unit 1 receives an input signal, divides the frequency of the input signal, and outputs the divided frequency signal to the voter unit 2, the voter unit 2 shields the frequency-divided signals, which are different from other signals, in each frequency-divided signal output by each frequency divider unit 1, and outputs the final frequency-divided signals and feeds the final frequency-divided signals back to each frequency divider unit 1, so that a single event effect caused by irradiation in a circuit can be suppressed.
In this embodiment, the input end and the output end of the frequency divider unit 1 are connected, the frequency divider unit 1 may adopt a required frequency divider according to actual requirements, and specifically may adopt a frequency divider composed of a flip-flop circuit and a nand gate circuit, the flip-flop circuit is composed of a plurality of sequentially connected flip-flops (e.g., D flip-flops, etc.), and the output end of the flip-flop circuit is connected to the input end of the flip-flop circuit through the nand gate circuit. By connecting the input and output of the frequency divider, the differential input signal of the clock signals clk and clk _ b in the frequency divider can be reduced.
As shown in fig. 2, in the embodiment of the present invention, there are specifically three frequency divider units 1, each frequency divider unit 1 operates independently, the voter unit 2 receives three frequency division signals output by the three frequency division units 1, masks frequency division signals different from the other two frequency division signals, and outputs final frequency division signals, where the frequency divider unit 1 specifically adopts frequency dividers (DIV 1, DIV2, and DIV 3) of frequency division 5, and the voter unit 2 specifically adopts a voter of three inputs in the prior art, and certainly, frequency dividers and voters of other structures may also be adopted according to actual requirements. The output ends OUT of the three frequency dividers are respectively connected to the input ends A, B and C of the voter, the output end OUT of the voter is fed back to the input end IN of each frequency divider to form a closed loop, the clock ends clk and clk _ B of each frequency divider are connected into a differential input signal formed by clock signals clk and clk _ B, the outputs of the frequency dividers DIV1, DIV2 and DIV3 are d5_1, d\ 5 u 2 and d5_3 respectively, all the outputs are input into the voter, and the voter outputs d5_ TMR signals to be fed back to the input ends of the three frequency dividers; when high-energy particles hit one frequency divider, other frequency dividers are in normal working states, and due to the action of the voter, the correct state is fed back to the wrong frequency divider, the state of the wrong frequency divider can be updated to the correct state, and the implementation cost is further reduced based on the three frequency divider structures.
As shown IN fig. 3, the frequency divider IN this embodiment is a 5-way frequency divider formed by three D flip-flops and one nand gate, and the frequency of the differential input signal formed by clk and clk _ b can be reduced to 1/5 of the original frequency by connecting the OUT terminal and the IN terminal.
As shown in fig. 4, in this embodiment, the voter includes three transistor branches and an inverter circuit, an upper branch of each transistor branch includes two PMOS transistors connected in series, a lower branch of each transistor branch includes two NMOS transistors connected in series, an intermediate node between the upper branch and the lower branch of each transistor branch is connected to an input terminal of the inverter circuit, each transistor branch is respectively connected to two signals of the three frequency-divided signals, wherein the upper branch and the lower branch of a first row are respectively connected to a signal a and a signal B correspondingly, the upper branch and the lower branch of a second row are respectively connected to a signal B and a signal C correspondingly, the branch of a third row is connected to a signal C and a correspondingly, and after passing through the inverter circuit, different signals from the other two input signals in the three input paths of a, B, and C can be shielded.
As shown in fig. 4, the inverter circuit of this embodiment specifically includes a PMOS transistor and an NMOS transistor connected in series, and the whole voter circuit can be formed by connecting 14 thyristors, so that signals different from the other two paths of input signals in the three paths of input signals can be efficiently shielded, and output of a correct frequency-divided signal is realized.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (6)
1. A frequency divider circuit having an anti-radiation function, characterized by: the frequency divider comprises more than three frequency divider units (1) and a voter unit (2), wherein the output end of each frequency divider unit (1) is respectively connected with the input end of the voter unit (2), and the output end of the voter unit (2) is connected to the input end of each frequency divider unit (1) in a feedback mode; the input end of the frequency divider unit (1) is connected with the output end; the frequency divider unit (1) comprises a trigger circuit and a NAND gate circuit, wherein the output end of the trigger circuit is connected to the input end of the trigger circuit through the NAND gate circuit; the voter unit (2) comprises three transistor branches and an inverter circuit, wherein the upper branch of each transistor branch comprises two PMOS (P-channel metal oxide semiconductor) tubes connected in series, the lower branch of each transistor branch comprises two NMOS (N-channel metal oxide semiconductor) tubes connected in series, and a middle node between the upper branch and the lower branch of each transistor branch is connected to the input end of the inverter circuit.
2. The frequency divider circuit with radiation-resistant function according to claim 1, characterized in that: each frequency divider unit (1) receives an input signal, divides the frequency of the input signal, outputs the divided frequency to the voter unit (2), shields the frequency-divided signals which are different from other signals in each path of frequency-divided signals output by each frequency divider unit (1) through the voter unit (2), outputs final frequency-divided signals and feeds the final frequency-divided signals back to each frequency divider unit (1) respectively.
3. The frequency divider circuit with radiation-resistant function according to claim 1, characterized in that: the trigger circuit comprises a plurality of D triggers which are connected in sequence.
4. The frequency divider circuit with an irradiation-resistant function according to any one of claims 1 to 3, characterized in that: the number of the frequency divider units (1) is three, and the voter unit (2) receives three paths of frequency division signals output by the corresponding three frequency divider units (1), shields the frequency division signals different from other two paths of frequency division signals, and outputs final frequency division signals.
5. The frequency divider circuit with radiation-resistant function according to claim 4, characterized in that: and each transistor branch is respectively connected with two paths of signals in the three paths of frequency division signals.
6. The frequency divider circuit with radiation-resistant function according to claim 1 or 5, characterized in that: the phase inverter circuit comprises a PMOS tube and an NMOS tube which are connected in series.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811434619.8A CN109525243B (en) | 2018-11-28 | 2018-11-28 | Frequency divider circuit with anti-radiation function |
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| CN201811434619.8A CN109525243B (en) | 2018-11-28 | 2018-11-28 | Frequency divider circuit with anti-radiation function |
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| CN109525243A CN109525243A (en) | 2019-03-26 |
| CN109525243B true CN109525243B (en) | 2023-03-21 |
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| CN108847842B (en) * | 2018-06-05 | 2022-02-11 | 西安微电子技术研究所 | Asynchronous frequency division circuit with self-refreshing function and capable of resisting single event upset effect |
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