CN109509506A - To the detection method and device of Vcc when a kind of power up test - Google Patents
To the detection method and device of Vcc when a kind of power up test Download PDFInfo
- Publication number
- CN109509506A CN109509506A CN201811566182.3A CN201811566182A CN109509506A CN 109509506 A CN109509506 A CN 109509506A CN 201811566182 A CN201811566182 A CN 201811566182A CN 109509506 A CN109509506 A CN 109509506A
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- CN
- China
- Prior art keywords
- vcc
- signal
- detect
- power
- test
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses when a kind of power up test to the detection method and device of Vcc, it is optimized for the Vcc voltage measurement in the power up test circuit of storage chip, the time that Vcc voltage changes simply is calculated by an additional counter, the numerical value and triggered time Tvcc that Vcc_detect can quickly and easily be obtained, avoid traditional complicated test method.
Description
Technical field
The present invention relates to when a kind of power up test field, especially power up test of storage circuit to the detection method of Vcc
And device.
Background technique
In field of storage, upper electro-detection is the necessary steps of test before storage chip factory, is related to storage chip
Job stability, power on detection circuit can be all arranged in manufacturer in storage chip under normal conditions, in power on detection circuit
Test point is set, is used to Vcc, Vpp or level signal etc.;Since the variation of voltage in storage chip also relates to time ginseng
Number, therefore routine is typically more complicated for the test method of test point.
Summary of the invention
To solve the above problems, the present invention provides, to the detection method and device of Vcc, utilize meter when a kind of power up test
The parameter of number device combination clock test Vcc, can quickly and accurately be tested.
Technical solution used by the present invention solves the problems, such as it is:
To the detection method of Vcc when a kind of power up test, comprising the following steps:
Clock signal begins to count when reaching from Vcc_detect signal;
Clock signal stops counting when reaching from Vcc signal;
Clock signal is obtained from Vcc_detect to the duration reached during Vcc is reached by periodicity N and each period
T;
The numerical value of Vcc_detect signal is obtained, and the signal triggered time Tvcc from Vcc_detect to Vcc.
Further, the signal triggered time Tvcc=N*T from Vcc_detect to Vcc.
Further, Vcc signal is promoted since Vcc_detect signal with constant airspeed, and promotion rate is f, Vcc_
The numerical value of detect signal is Vcc-f*N*T.
Further, the clock signal is square-wave pulse signal, is generated by the clock inside storage chip or by outside
Clock input.
To the detection device of Vcc when a kind of power up test, comprising:
Start timing module, begins to count when reaching for clock signal from Vcc_detect signal;
Terminate timing module, stops counting when reaching for clock signal from Vcc signal;
Counting module, for obtain clock signal from Vcc_detect to reaching during Vcc is reached by periodicity N and
The duration T in each period;
Processing module, the signal touching for obtaining the numerical value of Vcc_detect signal, and from Vcc_detect to Vcc
Send out time Tvcc.
The beneficial effects of the present invention are: the present invention for storage chip power up test circuit in Vcc voltage measure into
Row optimization simply calculates the time that Vcc voltage changes by an additional counter, can quickly and easily be obtained
The numerical value and triggered time Tvcc for obtaining Vcc_detect, avoid traditional complicated test method.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples.
Fig. 1 is the flow diagram of the embodiment of the present invention;
Fig. 2 is the Vcc level schematic diagram of the embodiment of the present invention.
Specific embodiment
Referring to Figures 1 and 2, An embodiment provides, to the detection method of Vcc, wrap when a kind of power up test
Include following steps:
Clock signal begins to count when reaching from Vcc_detect signal;
Clock signal stops counting when reaching from Vcc signal;
Clock signal is obtained from Vcc_detect to the duration reached during Vcc is reached by periodicity N and each period
T;
The numerical value of Vcc_detect signal is obtained, and the signal triggered time Tvcc from Vcc_detect to Vcc.
The present embodiment actually attached the counter of conventional pulsed in the circuit of storage chip, and Vcc is drawn
One foot is connected in counter and is measured by counter according to the time of the voltage change of Vcc, and Vcc can be learnt by Vcc_
Detect begins to ramp up the time experienced, so as to quickly calculate numerical value and the triggered time of Vcc_detect signal
Tvcc provides foundation for decision circuitry problem.
Preferably, another embodiment of the present invention provides when a kind of power up test to the detection method of Vcc, from
The signal triggered time Tvcc=N*T of Vcc_detect to Vcc.Since the signal of counter is pulsed, directly
Periodicity and cycle duration can be used and carry out time measurement, in actual mechanical process, according to the certain timing of the selection of engineer
Clock signal, making periodicity in Tvcc is integer, easily facilitates calculating.
Preferably, another embodiment of the present invention provides, to the detection method of Vcc, Vcc believes when a kind of power up test
It number is promoted since Vcc_detect signal with constant airspeed, promotion rate is f, and the numerical value of Vcc_detect signal is
Vcc-f*N*T.
Promotion rate f in the present embodiment, can reach the Vcc level time experienced by conduction time obtains,
Vcc voltage can obtain the promotion rate f of Vcc divided by the time, belong to the voltage tester mode of conventional storage chip, by being promoted
Rate f is that may know that by Vcc_detect promotion to the amplitude of Vcc multiplied by Tvcc, thus retrodicts to obtain the number of Vcc_detect
Value.
Preferably, another embodiment of the present invention provides when a kind of power up test to the detection method of Vcc, when described
Clock signal is square-wave pulse signal, is generated by the clock inside storage chip or is inputted by external clock.The present embodiment uses
Square wave is convenient for obtaining the periodicity of integer.
To the detection device of Vcc when a kind of power up test, comprising:
Start timing module, begins to count when reaching for clock signal from Vcc_detect signal;
Terminate timing module, stops counting when reaching for clock signal from Vcc signal;
Counting module, for obtain clock signal from Vcc_detect to reaching during Vcc is reached by periodicity N and
The duration T in each period;
Processing module, the signal touching for obtaining the numerical value of Vcc_detect signal, and from Vcc_detect to Vcc
Send out time Tvcc.
Referring to Fig.1-2, another embodiment of the present invention provides, to the detection method of Vcc, wrap when a kind of power up test
Include following steps:
Clock signal begins to count when reaching from Vcc_detect signal;
Clock signal stops counting when reaching from Vcc signal;
Clock signal is obtained from Vcc_detect to the duration reached during Vcc is reached by periodicity N and each period
T;
The numerical value of Vcc_detect signal is obtained, and the signal triggered time Tvcc from Vcc_detect to Vcc, from
The numerical value of signal triggered time Tvcc=N*T, the Vcc_detect signal of Vcc_detect to Vcc is Vcc-f*N*T,
Wherein Vcc signal is promoted since Vcc_detect signal with constant airspeed, and promotion rate is f.
The clock signal is square-wave pulse signal, is generated by the clock inside storage chip or defeated by external clock
Enter.
The present invention is optimized for the Vcc voltage measurement in the power up test circuit of storage chip, by adding one
Counter simply calculates the time that Vcc voltage changes, and can quickly and easily obtain the numerical value of Vcc_detect
With triggered time Tvcc, traditional complicated test method is avoided.
The above, only presently preferred embodiments of the present invention, the invention is not limited to above embodiment, as long as
It reaches technical effect of the invention with identical means, all should belong to protection scope of the present invention.
Claims (5)
1. to the detection method of Vcc when a kind of power up test, it is characterised in that: the following steps are included:
Clock signal begins to count when reaching from Vcc_detect signal;
Clock signal stops counting when reaching from Vcc signal;
Clock signal is obtained from Vcc_detect to the duration T reached during Vcc is reached by periodicity N and each period;
The numerical value of Vcc_detect signal is obtained, and the signal triggered time Tvcc from Vcc_detect to Vcc.
2. to the detection method of Vcc when a kind of power up test according to claim 1, it is characterised in that: from Vcc_
The signal triggered time Tvcc=N*T of detect to Vcc.
3. to the detection method of Vcc when a kind of power up test according to claim 1 or 2, it is characterised in that: Vcc signal
It is promoted since Vcc_detect signal with constant airspeed, promotion rate is f, and the numerical value of Vcc_detect signal is Vcc-f*
N*T.
4. to the detection method of Vcc when a kind of power up test according to claim 1, it is characterised in that: the clock letter
Number it is square-wave pulse signal, is generated by the clock inside storage chip or inputted by external clock.
5. to the detection device of Vcc when a kind of power up test, it is characterised in that: include:
Start timing module, begins to count when reaching for clock signal from Vcc_detect signal;
Terminate timing module, stops counting when reaching for clock signal from Vcc signal;
Counting module passes through periodicity N and each week from Vcc_detect to during reaching Vcc arrival for obtaining clock signal
The duration T of phase;
Processing module, for obtaining the numerical value of Vcc_detect signal, and the signal triggered time from Vcc_detect to Vcc
Tvcc。
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CN201811566182.3A CN109509506B (en) | 2018-12-20 | 2018-12-20 | Method and device for detecting Vcc during power-on test |
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CN201811566182.3A CN109509506B (en) | 2018-12-20 | 2018-12-20 | Method and device for detecting Vcc during power-on test |
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CN109509506A true CN109509506A (en) | 2019-03-22 |
CN109509506B CN109509506B (en) | 2021-05-14 |
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US20030014620A1 (en) * | 1998-10-30 | 2003-01-16 | Fairchild Semiconductor Corporation | Method and circuit for performing automatic power on reset of an integrated circuit |
CN101017455A (en) * | 2006-02-11 | 2007-08-15 | 深圳市顶星数码网络技术有限公司 | Electrifying timing sequence testing device and method thereof |
CN101800530A (en) * | 2009-12-29 | 2010-08-11 | 福建星网锐捷网络有限公司 | Power supply electrifying control method,device and equipment |
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