CN109509499A - Coding/decoding method, memory storage apparatus and memorizer control circuit unit - Google Patents

Coding/decoding method, memory storage apparatus and memorizer control circuit unit Download PDF

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Publication number
CN109509499A
CN109509499A CN201710825756.3A CN201710825756A CN109509499A CN 109509499 A CN109509499 A CN 109509499A CN 201710825756 A CN201710825756 A CN 201710825756A CN 109509499 A CN109509499 A CN 109509499A
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China
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data
decoding
control circuit
buffering area
circuit unit
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CN201710825756.3A
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CN109509499B (en
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仇志良
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

One example of the present invention embodiment provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit unit, comprising: keeps in the first data to buffer storage, wherein buffer storage includes first buffering area and second buffering area；The decoding data of second buffering area is copied into first buffering area；In first buffering area, first kind decoding operate is executed to the first data based on the decoding data replicated, wherein the decoding data replicated is different from the raw decoded data corresponding to the first data；And if first kind decoding operate is successful, exports decoding data.Whereby, the efficiency of decoding operate can be improved.

Description

Coding/decoding method, memory storage apparatus and memorizer control circuit unit
Technical field
The present invention relates to a kind of coding/decoding method, memory storage apparatus and memorizer control circuit units.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Due to reproducible nonvolatile memorizer module (rewritable non-volatile Memory module) (for example, flash memory) have data non-volatile, power saving, small in size, and without mechanical structure etc. Characteristic, so being very suitable to be built into above-mentioned illustrated various portable multimedia devices.
In general, in order to ensure the correctness of data, it is non-easily that data can first be encoded and then be stored into again duplicative In the property lost memory module.When reading data, data can be decoded to attempt to correct mistake therein.If the mistake in data It is all corrected, the data of corrigendum can just be passed back to host system.However, as coding/decoding technology gradually improves, coding/decoding Need the data volume of temporary data that may be greater than the capacity of set buffer storage in the process.Therefore, in coding/decoding It generally requires to repeat to read specific data from reproducible nonvolatile memorizer module in the process, to increase duplicative The loss of non-volatile memory module, and can also reduce coding/decoding speed.In particular, in iteration decoding operation, it is above-mentioned Situation is more significant.
Summary of the invention
One example of the present invention embodiment provides a kind of coding/decoding method, memory storage apparatus and memorizer control circuit list Member can improve the efficiency of decoding operate under the limited situation of capacity of buffer storage.
One example of the present invention embodiment provides a kind of coding/decoding method, is used for type nonvolatile mould Block, the reproducible nonvolatile memorizer module include multiple solid elements, and the coding/decoding method includes: by the first data It keeps in buffer storage, wherein the buffer storage includes first buffering area and second buffering area；Described second is buffered The decoding data in area copies to the first buffering area；In the first buffering area, based on the decoding data replicated First kind decoding operate is executed to first data, wherein the decoding data replicated is different from corresponding to described first The raw decoded data of data；And if the first kind decoding operate is successful, exports decoding data.
In one example of the present invention embodiment, the coding/decoding method further include: encoded primary data is to generate correspondence In the raw decoded data of first data；The initial data is stored to the first instance unit；And it will The raw decoded data corresponding to first data is stored in at least second instance unit in the solid element.
In one example of the present invention embodiment, the coding/decoding method further include: read from the first instance unit Initial data simultaneously reads the original for corresponding to first data from at least second instance unit in the solid element Beginning decoding data；The initial data is kept in the raw decoded data for corresponding to first data to the buffering Memory；And in the first buffering area, based on the raw decoded data corresponding to first data to described Initial data executes the first kind decoding operate.
In one example of the present invention embodiment, the coding/decoding method further include: based on corresponding to first number According to the raw decoded data first kind decoding operate is executed to the initial data before, described first will be corresponded to The raw decoded data of data copies to the second buffering area.
In one example of the present invention embodiment, the coding/decoding method further include: based in the second buffering area The decoding data executes the second class decoding operate to more correction data, to update the solution yardage in the second buffering area According to wherein the more correction data is corrected via the first kind decoding operate.
In one example of the present invention embodiment, the first kind decoding operate includes normal decoding mode and erasing mould Formula, and the coding/decoding method further include: according to the sum in first data with the data cell that can not be righted the wrong, certainly It is fixed that the first kind decoding operate is operated in into the normal decoding mode or the erasing mode.
In one example of the present invention embodiment, the first kind decoding operate belongs to more frame decodings, and the decoding Method further include: single frame decoding is executed according to the decoding result of the first kind decoding operate, to verify the first kind solution Corrigendum of the code operation to an at least error bit.
Another example of the present invention embodiment provides a kind of memory storage apparatus comprising connecting interface unit can answer Write formula non-volatile memory module and memorizer control circuit unit.The connecting interface unit is to be connected to host system System.The reproducible nonvolatile memorizer module includes multiple solid elements.The memorizer control circuit unit, connection To the connecting interface unit and the reproducible nonvolatile memorizer module, wherein the memorizer control circuit unit Keeping in the first data to buffer storage, wherein the buffer storage includes first buffering area and second buffering area, Wherein the memorizer control circuit unit is also to copy to first buffering for the decoding data of the second buffering area Area, wherein the memorizer control circuit unit also in the first buffering area based on the decoding data replicated First kind decoding operate is executed to first data, wherein the decoding data replicated is different from corresponding to described first The raw decoded data of data, wherein if the first kind decoding operate success, the memorizer control circuit unit also to Export decoding data.
In one example of the present invention embodiment, the memorizer control circuit unit is also to encoded primary data to produce The raw raw decoded data for corresponding to first data, wherein the memorizer control circuit unit will be also to will be described Initial data is stored to the first instance unit, wherein the memorizer control circuit unit will be also will correspond to described The raw decoded data of one data is stored in at least second instance unit in the solid element.
In one example of the present invention embodiment, the memorizer control circuit unit is also real from described first to indicate Body unit, which reads the initial data and reads from at least second instance unit in the solid element, corresponds to described the The raw decoded data of one data, wherein the memorizer control circuit unit also to by the initial data with it is corresponding It keeps in the raw decoded data of first data to the buffer storage, wherein the memorizer control circuit list Member also in the first buffering area based on correspond to first data the raw decoded data to described original Data execute the first kind decoding operate.
In one example of the present invention embodiment, based on the raw decoded data pair for corresponding to first data Before the initial data executes the first kind decoding operate, the memorizer control circuit unit will be also will correspond to institute The raw decoded data for stating the first data copies to the second buffering area.
In one example of the present invention embodiment, the memorizer control circuit unit is also to based on second buffering The decoding data in area executes the second class decoding operate to more correction data, described in updating in the second buffering area Decoding data, wherein the more correction data is corrected via the first kind decoding operate.
In one example of the present invention embodiment, the first kind decoding operate includes normal decoding mode and erasing mould Formula, and the memorizer control circuit unit is also to according to having the data cell that can not right the wrong in first data Sum, determine the first kind decoding operate operating in the normal decoding mode or the erasing mode.
In one example of the present invention embodiment, the first kind decoding operate belongs to more frames and decodes, and the storage Device control circuit unit is also to execute single frame decoding according to the decoding result of the first kind decoding operate, described in verifying Corrigendum of the first kind decoding operate to an at least error bit.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, is used to control duplicative non- Volatile, wherein the reproducible nonvolatile memorizer module includes multiple solid elements, wherein described Memorizer control circuit unit includes host interface, memory interface, buffer storage, error checking and correcting circuit and storage Device manages circuit.The host interface is to be connected to host system.The memory interface described can be made carbon copies to be connected to Formula non-volatile memory module.The memory management circuitry is connected to the host interface, memory interface, described Buffer storage and the error checking and correcting circuit, wherein the memory management circuitry to by the first data keep in The buffer storage, wherein the buffer storage includes first buffering area and second buffering area, wherein the memory pipe Manage circuit also the decoding data of the second buffering area is copied to the first buffering area, wherein the error checking with Correcting circuit is to execute first to first data based on the decoding data replicated in the first buffering area Class decoding operate, wherein the decoding data replicated is different from the raw decoded data corresponding to first data, The first kind decoding operate success in if, the memory management circuitry is also to export decoding data.
In one example of the present invention embodiment, the error checking is with correcting circuit also to encoded primary data to produce The raw raw decoded data for corresponding to first data, wherein the memory management circuitry is also to will be described original Data are stored to the first instance unit, wherein the memory management circuitry will be also will correspond to first data The raw decoded data is stored in at least second instance unit in the solid element.
In one example of the present invention embodiment, the memory management circuitry is also to indicate from the first instance list Member, which reads the initial data and reads from at least second instance unit in the solid element, corresponds to first number According to the raw decoded data, wherein the memory management circuitry also to by the initial data with correspond to described the The raw decoded data of one data is kept in the buffer storage, wherein the error checking and correcting circuit also to The initial data is executed based on the raw decoded data for corresponding to first data in the first buffering area The first kind decoding operate.
In one example of the present invention embodiment, based on the raw decoded data pair for corresponding to first data Before the initial data executes the first kind decoding operate, the memory management circuitry will be also will correspond to described the The raw decoded data of one data copies to the second buffering area.
In one example of the present invention embodiment, the memorizer control circuit unit is also to based on second buffering The decoding data in area executes the second class decoding operate to more correction data, described in updating in the second buffering area Decoding data, wherein the more correction data is corrected via the first kind decoding operate.
In one example of the present invention embodiment, the more correction data does not include with the data sheet that can not be righted the wrong Member.
In one example of the present invention embodiment, the decoding data for copying to the first buffering area is based on to Second class decoding operate performed by more correction data and the raw decoded data corresponding to first data and generate.
In one example of the present invention embodiment, the first kind decoding operate includes normal decoding mode and erasing mould Formula, and the memory management circuitry also to according in first data have can not right the wrong data cell it is total Number determines the first kind decoding operate operating in the normal decoding mode or the erasing mode.
In one example of the present invention embodiment, first data are in the first instance unit by independent hard disk The protection of redundant array error correcting code.
In one example of the present invention embodiment, the first kind decoding operate belongs to more frames and decodes, and the storage Device control circuit unit is also to execute single frame decoding according to the decoding result of the first kind decoding operate, described in verifying Corrigendum of the first kind decoding operate to an at least error bit.
Based on above-mentioned, the decoding data dynamically generated in decoding process can be stored in buffer storage by the present invention.When Subsequent this decoding data can be used immediately when decoding the first data, non-volatile from duplicative without repeating Memory module reads related data and computes repeatedly and obtain.It whereby, can be under the limited situation of capacity of buffer storage Improve the efficiency of decoding operate.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is host system, memory storage apparatus and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out.
Fig. 2 is host system shown by another exemplary embodiment according to the present invention, memory storage apparatus and I/O dress The schematic diagram set.
Fig. 3 is the signal of host system and memory storage apparatus shown by another exemplary embodiment according to the present invention Figure.
Fig. 4 is the schematic block diagram of memory storage apparatus shown by an exemplary embodiment according to the present invention.
Fig. 5 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Fig. 6 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram.
Fig. 7 is the schematic diagram of more frame codings shown by an exemplary embodiment according to the present invention.
Fig. 8 to Figure 11 is the schematic diagram of decoding operate shown by an exemplary embodiment according to the present invention.
Figure 12 and Figure 13 is the flow chart of coding/decoding method shown by an exemplary embodiment according to the present invention.
Drawing reference numeral explanation
10,30: memory storage apparatus
11,31: host system
110: system bus
111: processor
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: motherboard
201:U disk
202: storage card
203: solid state hard disk
204: radio memory storage device
205: GPS module
206: network interface card
207: radio transmitting device
208: keyboard
209: screen
210: loudspeaker
32:SD card
33:CF card
34: embedded storage device
341: embedded multi-media card
342: embedded type multi-core piece sealed storage device
402: connecting interface unit
404: memorizer control circuit unit
406: reproducible nonvolatile memorizer module
502: memory management circuitry
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer storage
512: electric power management circuit
601: memory block
602: replacement area
610 (0)~610 (B), 710 (0)~710 (E): solid element
612 (0)~612 (C): logic unit
701 (1)~701 (r): position
830,831,832,833,1001,1002: data
720,840,841,941,942: decoding data
810,820: buffer area
S1201: step (reads initial data and raw decoded data from reproducible nonvolatile memorizer module)
S1202: step (keeps in initial data and raw decoded data to buffer storage)
S1203: raw decoded data (is copied to the second buffering area of buffer storage) by step
S1204: step (in the first buffering area of buffer storage, executes initial data based on raw decoded data First kind decoding operate)
S1205: step (judges whether first kind decoding operate succeeds)
S1206: step (output decodes decoding data)
S1301: step (from reproducible nonvolatile memorizer module read the first data and by the first data keep in Buffer storage)
S1302: step (copies to the decoding data in second buffering area in first buffering area)
S1303: step (in first buffering area, executes first kind solution to the first data based on the decoding data replicated Code operation)
S1304: step (judges whether first kind decoding operate succeeds)
S1305: step (exports decoding data)
S1306: step (judges whether there is data to be corrected in first kind decoding operate)
S1307: step (executes the second class decoding behaviour to the data corrected based on the decoding data in second buffering area Make, to update decoding data)
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module (rewritable non-volatile memory module) and controller (also referred to as, control circuit).It is commonly stored Device storage device is used together with host system, so that host system can write data into memory storage apparatus or from depositing Data are read in reservoir storage device.
Fig. 1 is host system, memory storage apparatus and input shown by an exemplary embodiment according to the present invention/defeated The schematic diagram of (I/O) device out.Fig. 2 is that host system shown by another exemplary embodiment according to the present invention, memory are deposited The schematic diagram of storage device and I/O device.
Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, RAM) 112, read-only memory (read only memory, ROM) 113 and data transmission interface 114.Place Reason device 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all connected to system bus (system bus)110。
In this exemplary embodiment, host system 11 is connected by data transmission interface 114 and memory storage apparatus 10 It connects.For example, host system 11 can store data to memory storage apparatus 10 or from memory via data transmission interface 114 Data are read in storage device 10.In addition, host system 11 is to be connect by system bus 110 with I/O device 12.For example, main Output signal can be sent to I/O device 12 via system bus 110 or receive input signal from I/O device 12 by machine system 11.
In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 may be provided on the motherboard 20 of host system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, motherboard 20 can be connected to memory storage apparatus 10 via wired or wireless way.Memory Storage device 10 can be for example USB flash disk 201, storage card 202, solid state hard disk (Solid State Drive, SSD) 203 or wirelessly deposit Reservoir storage device 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth) Memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. are with various wireless communication technique The memory storage apparatus on basis.In addition, motherboard 20 can also be connected to global positioning system by system bus 110 (Global Positioning System, GPS) module 205, network interface card 206, radio transmitting device 207, keyboard 208, The various I/O device such as screen 209, loudspeaker 210.For example, motherboard 20 can pass through radio transmitting device in an exemplary embodiment 207 access wireless memory storage apparatus 204.
In an exemplary embodiment, mentioned host system is substantially to cooperate with memory storage apparatus to store The arbitrary system of data.Although host system is explained with computer system, however, Fig. 3 is in above-mentioned exemplary embodiment The schematic diagram of host system and memory storage apparatus shown by another exemplary embodiment according to the present invention.Referring to figure 3., In another exemplary embodiment, host system 31 is also possible to digital camera, video camera, communication device, audio player, video The systems such as player or tablet computer, and memory storage apparatus 30 can be its used secure digital (Secure Digital, SD) card 32, compact flash (Compact Flash, CF) block 33 or embedded storage device 34 etc. it is various non-volatile Property memory storage apparatus.Embedded storage device 34 includes embedded multi-media card (embedded Multi Media Card, eMMC) 341 and/or embedded type multi-core piece encapsulate (embedded Multi Chip Package, eMCP) storage device The all types of embedded storage devices being directly connected in memory module on the substrate of host system such as 342.
Fig. 4 is the schematic block diagram of memory storage apparatus shown by an exemplary embodiment according to the present invention.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.
Connecting interface unit 402 is to be connected to host system 11 for memory storage apparatus 10.In this exemplary embodiment In, connecting interface unit 402 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, and connecting interface unit 402 is also possible to Meet parallel advanced technology annex (Parallel Advanced Technology Attachment, PATA) standard, it is electrical and Electronic Engineering Association (Institute of Electrical and Electronic Engineers, IEEE) 1394 marks Quasi-, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, UHS-II) interface Standard, MCP interface standard, MMC interface standard, eMMC interface standard, is led at memory stick (Memory Stick, MS) interface standard With flash memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, whole Box-like driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.Connection Interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface unit 402 is cloth Outside a chip comprising memorizer control circuit unit 404.
Memorizer control circuit unit 404 is to execute multiple logic gates or control with hardware pattern or Solid form implementation System instructs and carries out writing for data in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.
Reproducible nonvolatile memorizer module 406 is to be connected to memorizer control circuit unit 404 and to deposit The data that storage host system 11 is written.Reproducible nonvolatile memorizer module 406 can be single-order storage unit (Single Level Cell, SLC) NAND type flash memory module is (that is, can store 1 bit in a storage unit Flash memory module), multi-level cell memory (Multi Level Cell, MLC) NAND type flash memory module is (that is, one The flash memory module of 2 bits can be stored in a storage unit), Complex Order storage unit (Triple Level Cell, TLC) NAND type flash memory module (that is, flash memory module that 3 bits can be stored in a storage unit), other Flash memory module or other memory modules with the same characteristics.
Each of reproducible nonvolatile memorizer module 406 storage unit (is hereinafter also referred to faced with voltage Boundary's voltage) change store one or more bits.Specifically, the control grid (control of each storage unit Gate) there is an electric charge capture layer between channel.By bestowing a write-in voltage to controlling grid, thus it is possible to vary charge benefit is caught The amount of electrons of layer, and then change the critical voltage of storage unit.This change storage unit critical voltage operation be also referred to as " Data are written to storage unit " or " sequencing (programming) storage unit ".With the change of critical voltage, can make carbon copies Each of formula non-volatile memory module 406 storage unit has multiple storage states.It can by bestowing reading voltage To judge a storage unit is which storage state belonged to, one or more ratios that this storage unit is stored are obtained whereby It is special.
In this exemplary embodiment, the storage unit of reproducible nonvolatile memorizer module 406 can constitute multiple realities Body programmed cell, and these entity program units can constitute multiple entity erased cells.Specifically, same character Storage unit on line can form one or more entity program units.If each storage unit can store 2 or more ratios Spy, then the entity program unit on same word-line can at least be classified as lower entity program unit and upper entity program Change unit.For example, the minimum effective bit (Least Significant Bit, LSB) of a storage unit is to belong to lower entity journey Sequence unit, and the highest significant bit (Most Significant Bit, MSB) of a storage unit is to belong to entity journey Sequence unit.In general, in MLC NAND type flash memory, the writing speed of lower entity program unit can be greater than upper The reliability of the writing speed of entity program unit and/or lower entity program unit is above entity program unit Reliability.
In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is The minimum unit of data is written.For example, entity program unit is physical page (page) or entity fan (sector).If real Body programmed cell is physical page, then these entity program units generally include data bit area and redundancy (redundancy) bit area.Data bit area is fanned comprising multiple entities, and to store user's data, and redundancy ratio special zone is used With memory system data (for example, error correcting code etc. manages data).In this exemplary embodiment, data bit area includes 32 Entity fan, and the size of entity fan is 512 bit groups (byte, B).However, in other exemplary embodiments, data bit It also may include 8,16 or the more or fewer entity fans of number in area, and the size of each entity fan is also possible to more It is big or smaller.On the other hand, entity erased cell is the minimum unit erased.That is, each entity erased cell contains minimum The storage unit of number being erased together.For example, entity erased cell is physical blocks (block).
Fig. 5 is the schematic block diagram of memorizer control circuit unit shown by an exemplary embodiment according to the present invention.
Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504, storage Device interface 506, error checking and correcting circuit 508 and buffer storage 510.
Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.It is equivalent when illustrating the operation of memory management circuitry 502 below In the operation for illustrating memorizer control circuit unit 404.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with Solid form.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.
In another exemplary embodiment, the control instruction of memory management circuitry 502 can also be stored in procedure code pattern The specific region of reproducible nonvolatile memorizer module 406 is (for example, be exclusively used in storage system data in memory module System area) in.In addition, memory management circuitry 502 have microprocessor unit (not shown), read-only memory (not shown) and Random access memory (not shown).In particular, this read-only memory has boot code (boot code), and work as memory When control circuit unit 404 is enabled, microprocessor unit can first carry out this boot code, and will to be stored in duplicative non-volatile Control instruction in property memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- Processor unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.
In addition, the control instruction of memory management circuitry 502 can also be come in another exemplary embodiment with a hardware pattern Implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write circuit, storage Device reading circuit, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write circuit, storage Device reading circuit, memory erase circuit and data processing circuit is to be connected to microcontroller.Storage Unit Management circuit to Manage storage unit or its group of reproducible nonvolatile memorizer module 406.Memory write circuit is to can answer It writes formula non-volatile memory module 406 and assigns write instruction sequence to write data into type nonvolatile In module 406.Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign read instruction sequence with Data are read from reproducible nonvolatile memorizer module 406.Memory erases circuit to non-volatile to duplicative Property memory module 406, which is assigned, erases instruction sequence so that data to be erased from reproducible nonvolatile memorizer module 406. Data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative to handle The data read in non-volatile memory module 406.Write instruction sequence reads instruction sequence and instruction sequence of erasing can be each It Bao Kuo not one or more procedure codes or instruction code and to indicate that reproducible nonvolatile memorizer module 406 executes relatively The write-in answered such as reads and erases at the operation.In an exemplary embodiment, memory management circuitry 502 can also assign other classes The instruction sequence of type indicates to execute corresponding operation to reproducible nonvolatile memorizer module 406.
Host interface 504 is to be connected to memory management circuitry 502 and passed to receive with identification host system 11 The instruction and data sent.That is, the instruction that host system 11 is transmitted can be sent to data by host interface 504 Memory management circuitry 502.In this exemplary embodiment, host interface 504 is to be compatible to SATA standard.However, it is necessary to understand Be that the invention is not limited thereto, host interface 504 is also possible to be compatible to PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS mark Standard, CF standard, IDE standard or other suitable data transmission standards.
Memory interface 506 is to be connected to memory management circuitry 502 and duplicative is non-volatile to be deposited to access Memory modules 406.It can be via memory to the data of reproducible nonvolatile memorizer module 406 that is, being intended to be written Interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if memory pipe Reason circuit 502 will access reproducible nonvolatile memorizer module 406, and memory interface 506 can transmit corresponding sequence of instructions Column.For example, these instruction sequences may include the reading sequence of instructions of the write instruction sequence of instruction write-in data, instruction reading data Column, instruction erase data erase instruction sequence and to indicate various storage operations (for example, change read voltage electricity It is flat or execute garbage collection operation etc.) corresponding instruction sequence.These instruction sequences are, for example, by memory management electricity Road 502 generates and is sent to reproducible nonvolatile memorizer module 406 by memory interface 506.These sequence of instructions Column may include one or more signals, or the data in bus.These signals or data may include instruction code or procedure code.Example Such as, in reading instruction sequence, the information such as identification code, the storage address of reading be will include.
Error checking and correcting circuit 508 be connected to memory management circuitry 502 and to execute error checking with Correct operation is to ensure the correctness of data.Specifically, it is write when memory management circuitry 502 is received from host system 11 When entering to instruct, error checking can generate corresponding error correcting code with correcting circuit 508 for the data of this corresponding write instruction (error correcting code, ECC) and/or error checking code (error detecting code, EDC), and store Device management circuit 502 data of this corresponding write instruction and corresponding error correcting code and/or error checking code can be written to In reproducible nonvolatile memorizer module 406.Later, when memory management circuitry 502 is deposited from duplicative is non-volatile The corresponding error correcting code of this data and/or error checking code can be read when reading data in memory modules 406 simultaneously, and wrong Erroneous detection, which is looked into, can execute mistake inspection to read data according to this error correcting code and/or error checking code with correcting circuit 508 It looks into and correct operation.
Buffer storage 510 is connected to memory management circuitry 502 and is configured to temporarily store from host system 11 Data and instruction or the data from reproducible nonvolatile memorizer module 406.In an exemplary embodiment, memory Control circuit unit 404 further includes electric power management circuit 512.Electric power management circuit 512 is to be connected to memory management circuitry 502 And to the power supply for controlling memory storage apparatus 10.
Fig. 6 is management reproducible nonvolatile memorizer module shown by an exemplary embodiment according to the present invention Schematic diagram.
Fig. 6 is please referred to, memory management circuitry 502 can be by the entity list of reproducible nonvolatile memorizer module 406 First 610 (0)~610 (B) are logically grouped to memory block 601 and replacement area 602.Solid element 610 (0) in memory block 601 ~610 (A) are that the solid element 610 (A+1)~610 (B) to storing data, and in replacement area 602 is deposited to replace The solid element damaged in storage area 601.For example, if the data read from some solid element the mistake that is included it is excessive and When can not be corrected, this solid element can be considered to be the solid element of damage.It is noted that if not having in replacement area 602 Available entity erased cell, then whole memory storage device 10 may be declared as being written by memory management circuitry 502 (write protect) state of protection, and data can not be written again.
In this exemplary embodiment, each solid element refers to an entity program unit.However, in another example In embodiment, a solid element may also mean that a physical address, an entity erased cell or by it is multiple continuously or not Continuous physical address composition.The meeting of memory management circuitry 502 configuration logic unit 612 (0)~612 (C) is with mapped memory region Solid element 610 (0)~610 (A) in 601.In this exemplary embodiment, each logic unit refer to one logically Location.However, a logic unit may also mean that a logical program unit, a logic in another exemplary embodiment Erased cell is made of multiple continuous or discontinuous logical addresses.In addition, in logic unit 612 (0)~612 (C) Each can be mapped to one or more solid elements.
Memory management circuitry 502 can be by mapping relations (also referred to as logic-entity between logic unit and solid element Address mapping relation) it is recorded at least one logic-physical address mapping table.When host system 11 is intended to from memory storage apparatus 10 When reading data or writing data to memory storage apparatus 10, memory management circuitry 502 can be according to this logic-physical address Mapping table executes the data access operation for memory storage apparatus 10.
In this exemplary embodiment, the basic unit of error checking and the execution coded program of correcting circuit 508 is a news Frame (frame) (also referred to as decoding frame).One frame includes multiple data bits.In this exemplary embodiment, a frame Including 256 bits.However, in another exemplary embodiment, a frame also may include more (such as 4K bytes) or Less bit.
In this exemplary embodiment, error checking and correcting circuit 508 can be directed to and be stored in the same solid element Data carry out single frame (single-frame) and encode and decoding, can also be for the data being stored in multiple solid elements Carry out more frames (multi-frame) coding and decoding.Low-density surprise can be respectively adopted with more frames coding in single frame coding It is even check correcting code (low density parity code, LDPC), BCH code, convolution code (convolutional code) or At least one of the encryption algorithms such as turbine code (turbo code).Alternatively, more frame codings are also in an exemplary embodiment Reed Solomon code (Reed-solomon codes, RS codes) algorithm can be used.In addition, in another exemplary embodiment In, the encryption algorithm not being listed in more can also be used, and just not repeated herein.According to used encryption algorithm, mistake The data to be protected can be encoded with correcting circuit 508 to generate corresponding error correcting code and/or error checking code by checking. For convenience of description, below by via coding generate error correcting code and/or error checking code be referred to as decoding data (that is, For decoded data).In an exemplary embodiment, odd and even data is also referred to as via the decoding data that coding generates.
Fig. 7 is the schematic diagram of more frame codings shown by an exemplary embodiment according to the present invention.
Fig. 7 is please referred to, generates corresponding decoding with data that coding entity unit 710 (0)~710 (E) is stored For data 720, at least partly data visualization that each of solid element 710 (0)~710 (E) is stored is a news Frame.It in more frames coding, is come for foundation to solid element 710 (0) with the position where each bit (or, bit group) Data in~710 (E) are encoded.For example, being located at the bit b of position 701 (1)11、b21、…、bp1It can be encoded as decoding Bit b in data 720o1, it is located at the bit b of position 701 (2)12、b22、…、bp2The ratio that can be encoded as in decoding data 720 Special bo2；And so on, it is located at the bit b of position 701 (r)1r、b2r、…、bprThe bit that can be encoded as in decoding data 720 bor。
In an exemplary embodiment, solid element 710 (0)~710 (E) is also referred to as first instance unit, and to store The solid element of decoding data 720 is then known as second instance unit.The number of first instance unit and second instance unit all may be used To be more or less.In an exemplary embodiment, decoding data 720 is via in coding entity unit 710 (0)~710 (E) Specific data (also referred to as initial data) and generate, therefore decoding data 720 be considered as it is original corresponding to initial data Decoding data.In an exemplary embodiment, it can be considered that initial data is in solid element 710 (0)~710 (E) by solution yardage According to 720 protections.In an exemplary embodiment, decoding data 720 is also considered as independent hard disk redundancy array (Redundant Array of Independent Disks, RAID) error correcting code.Based on decoding data 720, from solid element 710 (0)~ The data read in 710 (E) can be decoded, to attempt to correct mistake that may be present in read data.
In an exemplary embodiment, for generate decoding data 720 data may also include solid element 710 (0)~ Redundant bit corresponding to the data bit in data that 710 (E) are stored.It is with the data that solid element 710 (0) is stored Example, redundant bit therein are, for example, to carry out single frame coding to the data bit being stored in solid element 710 (0) and generate 's.
In an exemplary embodiment, when the data (also referred to as target data) for being intended to read some solid element and being stored When, single frame decoding corresponding to this target data can be first performed.For example, if target data is to carry out list based on LDPC code Frame coding, then this target data can also carry out single frame decoding based on LDPC code.If corresponding to the Dan Xun of this target data Frame decoding failure then can connect execution corresponding to more frames decoding of this target data, for example, the RS code used when based on coding And it executes.
In an exemplary embodiment, single frame decoding can be alternately performed with the decoding of more frames, until determining decoding failure Or until successfully decoded.By taking Fig. 7 as an example, when being intended to read the target data for being stored in solid element 710 (0), correspond to entity The first time list frame decoding for the target data to be read in unit 710 (0) can be first performed, that may be present to attempt corrigendum Mistake.If the first time list frame decoding failure corresponding to target data, decoding data 720 and solid element 710 (1)~ First time more frames of target data can be read out and corresponded in 710 (E) for generating the data of decoding data 720 Decoding can be performed.If the first time for corresponding to target data more frame decoding failures, decode according to more frames of first time Implementing result (for example, certain bits in target data may be corrected), second of Dan Xun corresponding to target data Frame decoding can be performed.If second of single frame decoding still fails, correspond to second of more frame decoding of target data It can be performed.The rest may be inferred, is executing single frame decoding at least once and/or more frame solutions at least once to target data After code, the mistake in target data can should be gradually corrected.If certain primary single frame decoding or more frame successfully decodeds are more Institute in positive goal data is wrong, then corresponding iteration decoding can stop.Alternatively, if the Dan Xun executed to same target data Frame decoding and/or the decoded number of more frames reach a number critical value, then can determine that decoding failure.
In an exemplary embodiment, decoding in a certain more frames that completion corresponds to target data (may in target data Still wrong presence) after, at least one single frame decoding can be executed according to this more decoded decoding result of frame.This single frame Whether decoding can verify that correct to the corrigendum of at least one error bit in previous more frames decoding.If this single frame is decoded Decoding result reflects that the corrigendum previously for a certain error bit is correctly, then the corrigendum of this error bit can be retained. Conversely, if this single decoded decoding result of frame reflect the corrigendum previously for a certain error bit be not correctly, this The corrigendum of error bit can be cancelled, so that it is its initial value that the bit value of this error bit, which is replied,.
Fig. 8 to Figure 11 is the schematic diagram of decoding operate shown by an exemplary embodiment according to the present invention.Please refer to figure 8, buffer storage 510 includes buffer area 810 and 820.Buffer area 810 is also referred to as first buffering area, and buffer area 820 is also referred to as For second buffering area.In an exemplary embodiment, the capacity of buffer area 810 can the identical or rough buffer area 820 that is identical to Capacity.In an exemplary embodiment, the capacity of buffer area 820 is less than the capacity of buffer area 810.In an exemplary embodiment, delay Rushing area 810 and 820 can be by 502 dynamic configuration of memory management unit of Fig. 5.
When determining to need to be implemented more frames decoding corresponding to data 831, data 830 and the solution for corresponding to data 830 Code data 840 can be read out from first instance unit and second instance unit respectively.Data 830 include data 831 with 832.Data 831 are currently to be intended to the target data for being decoded and being corrected based on decoding data 840, and data 832 are then for for producing The remainder data of raw decoding data 840.By taking Fig. 7 as an example, if data 831 are stored in the data of solid element 710 (0), count At least partly data that solid element 710 (1)~710 (E) may be stored according to 832.
In an exemplary embodiment, data 830 are considered as initial data, and decoding data 840 is considered as corresponding to The raw decoded data of data 830, data 831 and/or 832.Data 830 and decoding data 840 can be loaded on buffer-stored Device 510.For example, data 830 and decoding data 840 can be temporary in buffer area 810.It is noted that being based on decoding data Before 840 pairs of data 830 are decoded, decoding data 840 can be copied to buffer area 820 as decoding data 841.It will decode Data 840 copy to after buffer area 820, are based on decoding data 840, and data 830 can be decoded in buffer area 810.
In an exemplary embodiment, since the off-capacity of buffer storage 510 (or buffer area 810) is disposably to deposit Store up complete data 830 (i.e. the total amount of data of data 830 is greater than buffer storage 510 or the capacity of buffer area 810), therefore number It may be stored into buffer area 810 in batches according to 830 and decoded in batches based on decoding data 840.It is noted that In one exemplary embodiment, during decoded in batches to data 830, data 831 persistently can be maintained and/or be retained in slow It rushes in area 810, until data 831 are successfully decoded and/or correct.
In an exemplary embodiment, corresponding to the decoding executed in buffer area 810, in decoding data 840 at least partly Bit may be updated so that in buffer area 810 updated decoding data 840 may with deposited in advance in buffer area 820 The decoding data 841 of storage is different.In an exemplary embodiment, corresponding to the decoding executed in buffer area 810, decoding data 840 It can be updated to verification (syndrome) data.This verification data can reflect the decoded decoded state executed for data 830 Or decoding result.
Please refer to Fig. 9, it is assumed that according to the decoding executed in buffer area 810, the data 833 in data 830 are corrected, still Data 831 are not yet corrected.In an exemplary embodiment, data 833 are also referred to as more correction data.After more correction data 833, base Decoding data 841 in buffer area 820, data 833 can be decoded.In the process based on 841 decoding data 833 of decoding data In, at least partly bit in decoding data 841 can may be also updated.Updated decoding data 841 can be saved persistently In buffer area 820.It is noted that the decoding data 841 in buffer area 820 is only used in solution in an exemplary embodiment The data (that is, data 833) corrected in code data 830, without the data for not yet being corrected in decoding data 830.This Outside, updated decoding data 841 is alternatively referred to as the verification data corresponding to data 833, and data 833 are executed with reflection Decoded decoded state or decoding result.
In an exemplary embodiment, corrigendum of the data 833 based on decoding data 840 still must be via corresponding to data 833 Single decoded verifying of frame.For example, in an exemplary embodiment of Fig. 9, after based on the more correction data 833 of decoding data 840, Single frame decoding corresponding to data 833 can be performed.If this single decoded decoding result of frame reflects in data 833 The corrigendum of error bit is correctly that then the corrigendum result of data 833 can be retained.Conversely, if this decoded decoding of single frame As a result reflect for the corrigendum of error bit in data 833 it is not correctly that then the corrigendum result of data 833 can be cancelled, So that certain bits being corrected can be responded as its original bit value in data 833.
In an exemplary embodiment, the decoding operate of Fig. 8 and Fig. 9 are considered as frames more for the first time of data 831 Decoding.More frame decodings are executed for the mistake in more correction data 831 for the first time for this.For example, data 831 may be to come Some from host system reads the indicated data read of instruction.If the mistake in data 831 is not corrected completely, this More frame decodings can be judged as failure for the first time.
Figure 10 is please referred to, if frame more for the first time of data 831 decoding failure, data 1001 can be by again from the It is read out in one solid element.It is noted that continuing the exemplary embodiment of Fig. 8 and Fig. 9, data 831 are sustainably protected It is stored in buffer area 810, without being read from first instance unit again with data 1001.In an exemplary embodiment, Data 1001 are also referred to as the first data.Data 1001 can be not comprising the data 833 being corrected in the exemplary embodiment of Fig. 9.Number It can be loaded on buffer storage 510 according to 1001, for example, being temporarily stored into buffer area 810.
Before decoding data 831 and 1001, decoding data 941 can by from buffer area 820 copy in buffer area 810 at For decoding data 942.It is noted that decoding data 941 is to indicate updated solution yardage in the buffer area 820 of Fig. 9 According to 841.In other words, the data content of decoding data 941 can be identical to updated decoding data in the buffer area 820 of Fig. 9 841.By decoding data 941 after copying to buffer area 810 in buffer area 820, be based on decoding data 942, data 831 with 1001 can be decoded in buffer area 810.
It is noted that in the exemplary embodiment of Figure 10, the decoding data 942 for decoding data 831 and 1001 is It replicates from buffer area 820, rather than is read from second instance unit.Therefore, the solution of decoding data 831 and 1001 is used in Figure 10 Code data 942 are different from the decoding data 840 in Fig. 8 and Fig. 9.Decoding data in an exemplary embodiment, in Fig. 8 and Fig. 9 840 are also considered as the raw decoded data corresponding to data 1001.Further, since buffer storage 510 or buffer area 810 Off-capacity with disposably store complete data 1001 (i.e. the total amount of data of data 1001 be greater than buffer storage 510 or The capacity of buffer area 810), thus data 1001 can also may be stored into buffer area 810 in batches and based on decoding data 942 and It is decoded in batches.In addition, the data 1001 that deposit buffer area 810 is decoded in batches will not cover data 831.
Please refer to Figure 11, it is assumed that according to the decoding that Figure 10 is executed in buffer area 810, data 1002 are corrected, but number It is not corrected yet according to 831.In an exemplary embodiment, data 1002 are also referred to as more correction data.It is right in an exemplary embodiment It also can be by the decoded verifying of single frame corresponding to data 1002, to determine for data 1002 in the corrigendum of data 1002 The correctness of corrigendum.After more correction data 1002, based on the decoding data 941 in buffer area 820, data 1002 can be decoded. During being based on 941 decoding data 1002 of decoding data, at least partly bit in decoding data 941 may also can be by more Newly.Updated decoding data 941 can be persistently stored in buffer area 820, for corresponding to iterating for data 831 next time Decoding uses.
Decoding data 941 similar to the exemplary embodiment of Fig. 9, in an exemplary embodiment of Figure 11, in buffer area 820 The data (that is, data 1002) corrected of decoding are only used in, without for decoding the data not yet corrected (such as data The data that do not corrected in the data 1001 of 831 or Figure 10).Updated decoding data 941 alternatively referred to as corresponds to data 1002 Verification data, to reflect the decoded decoded state executed for data 1002 or decoding result.So far, it can be considered completion pair The more frame decodings of second of data 831.This second more frame decodings are executed also for the mistake in more correction data 831 's.In the exemplary embodiment of Figure 11, if the mistake in data 831 is not corrected completely, this second more frame decoding It can be judged as failure.
If second of more frame decoding still fails, the reading in the exemplary embodiment of Figure 10 and Figure 11 does not include target The operation of first data of data and more new data, the behaviour that decoding data is copied to first buffering area from second buffering area Make, execute decoding in first buffering area with data correcting operation, based on the decoding data in second buffering area to more positive number It can be all repeatedly executed according to the operation for executing the decoding data in decoded operation and update second buffering area, until saving Mistake in target data in first buffering area is by until successfully correcting.In addition, the decoding operate of Fig. 8 to Figure 11 can be by scheming 5 502 collocation error inspection of memory management circuitry and correcting circuit 508 execute.
In an exemplary embodiment, based on the decoding data copied in first buffering area (for example, the decoding data of Fig. 8 840 with the decoding data 942 in Figure 10) decoding that executes is also referred to as first kind decoding operate, and based on being stored in the second buffering The decoding that decoding data (for example, decoding data 941 in the decoding data 841 of Fig. 9 and Figure 11) in area executes is also referred to as the Two class decoding operates.
In an exemplary embodiment, first kind decoding operate data decoded (such as initial data and/or the first number According to) it may include and the second class decoding operate data decoded with can not correct the data cell of (referred to as UNC) mistake (such as more correction data) not will include the data cell with UNC mistake.Here, refer to can not be by corresponding for UNC mistake The mistake that single frame decodes to correct.By taking Fig. 7 as an example, it is assumed that a data cell refers to a frame, if being stored in entity list Some data cell in first 710 (0) can not successfully be corrected wherein by corresponding to single frame decoding of this data cell Mistake, then this data cell is considered as the data cell with UNC mistake.Alternatively, if being stored in solid element 710 (1) some data cell in can successfully correct mistake therein by corresponding to single frame decoding of this data cell Accidentally, then this data cell is considered as the data cell for not having UNC mistake.
In an exemplary embodiment, first kind decoding operate includes normal decoding mode and erasing (erasure) mode.Root According to the data cell in data to be decoded (for example, data 831 and 1001 of data 830 or Figure 10 in Fig. 8) with UNC mistake Sum, the operation of first kind decoding operate can be decided to be and operates in normal decoding mode or erasing mode.Implement in an example In example, if the sum of the data cell in data to be decoded with UNC mistake is greater than or equal to a predetermined value, such as 2, but not As limit, then normal decoding mode can be operated at by corresponding to the first kind decoding operate operation that data to be decoded execute.If The sum of data cell in data to be decoded with UNC mistake is less than predetermined value, then corresponds to data to be decoded execute the A kind of decoding operate operation can be operated at erasing mode.In the erase mode, first kind decoding operate can usually guarantee In pairs in the decoding and corrigendum of data to be decoded (or target data).
In the exemplary embodiment of Fig. 9 or Figure 11, the data to be decoded in buffer area 810 may include at least one tool There is the data cell of UNC mistake.Corresponding to the first kind decoding operate for treating decoding data execution, some in buffer area 810 Data cell with UNC mistake may be corrected as the data cell without UNC mistake.This does not have UNC mistake Data cell can be considered as more correction data.In the multiple iteration decoding continuously performed, read every time from first instance unit And it is loaded into the data cell that the first data in buffer area 810 can not have UNC mistake.Whereby, it is continuously holding In capable multiple iteration decoding, the number of the data cell in data to be decoded with UNC mistake can be gradually decreased, to improve It is decoded into power.
It is noted that only executing first time to initial data in the previous cases embodiment of Fig. 8 to Figure 11 When first kind decoding operate, the raw decoded data for corresponding to the first data (or initial data) can be by from second instance unit It reads.In the first kind decoding operate executed after second, the decoding data for being decoded to the first data is all It is replicated from second buffering area.In addition, in updating storage (decoding) operation in the decoding data of second buffering area, second The update of decoding data in buffer area only will receive the influence of the data cell without UNC mistake, so that it is slow to reduce by second The probability that the decoding data rushed in area is influenced by error bit (or UNC mistake).Therefore, decoding data is being buffered from second After area copies to first buffering area, the solution based on the first kind decoding operate that the decoding data replicated is executed in first buffering area Code success rate can be enhanced.
Figure 12 and Figure 13 is the flow chart of decoding operate shown by an exemplary embodiment according to the present invention.Please refer to figure 12, in step S1201, from reproducible nonvolatile memorizer module read initial data with correspond to the first data (or Initial data) raw decoded data.In step S1202, by initial data and the primitive solution yardage for corresponding to the first data According to keeping in the first buffering area of buffer storage (for example, buffer storage 510 of Fig. 8) (for example, the buffer area in Fig. 8 810).In step S1203, the raw decoded data for corresponding to the first data is copied to the second buffering area of buffer storage (for example, buffer area 820 in Fig. 8).In step S1204, in the first buffering area of buffer storage, based on corresponding to the The raw decoded data of one data executes first kind decoding operate to initial data.In step S1205, judgement corresponds to original Whether the first kind decoding operate of data succeeds.If (i.e. first kind decoding operate success), in step S1206, output solution The successful data (also referred to as decoding data) of code.If not (i.e. first kind decoding operate fail), then the step of entering Figure 13 S1301。
Figure 13 is please referred to, in step S1301, the first data is read from reproducible nonvolatile memorizer module and incites somebody to action First data are kept in the first buffering area of buffer storage.It is noted that the first data, which may not include, is persistently stored in Target data in one buffer area and the more correction data corrected in previous first kind decoding operate.In step In S1302, the decoding data in second buffering area is copied in first buffering area.In step S1303, in first buffering area In, first kind decoding operate is executed to the first data and target data based on the decoding data replicated.In step S1304, Judge whether first kind decoding operate succeeds.If so, exporting decoding data in step S1305.If it is not, in step S1306 In, it judges whether there is data (or data cell) and is corrected in first kind decoding operate.(i.e. no data (or data if not Unit) be corrected in first kind decoding operate), step S1301 is returned to, iteration decoding next time is re-executed.If having (has Data (or data cell) are corrected in first kind decoding operate), in step S1307, based on the solution in second buffering area Code data execute the second class decoding operate to the data (i.e. more correction data) corrected, to update the decoding in second buffering area Data.The decoding data updated based on more correction data is sustainable to be stored in second buffering area, for iterating next time Decoding uses.After step S1307, step S1301 is repeatable to be executed.In addition, in the exemplary embodiment of Figure 12 and Figure 13, If an execution number of performed decoding operate reaches a number critical value, decoding operate can be determined failure and by Stop.
In an exemplary embodiment, step S1206 and/or S1305 may also include the data by successfully decoded (for example, mesh Mark data) it copies to other solid elements and stores again, and will originally store the entity of this data (for example, target data) Entity erased cell of the erased cell labeled as damage.In addition, more error handle means can also in step S1206 and/or It is executed in S1305, the present invention is without restriction.
However, each step has been described in detail as above in Figure 12 and Figure 13, just repeat no more herein.It is worth noting that, figure 12 can be implemented as multiple procedure codes or circuit with each step in Figure 13, and the present invention is without restriction.In addition, Figure 12 and Figure 13 Method can arrange in pairs or groups example above embodiment use, also can be used alone, the present invention it is without restriction.
In conclusion the decoding data dynamically generated in decoding process can be persistently stored in buffer storage by the present invention In.When it is subsequent want repeat decoding target data when, the decoding data being stored in buffer storage can be used immediately, without It needs to repeat to read related data from reproducible nonvolatile memorizer module and computes repeatedly and obtain.In addition, of the invention Influence of the UNC mistake to the decoding data being stored in buffer storage can also be reduced.It whereby, can be in the capacity of buffer storage The efficiency of decoding operate is improved under limited situation.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field Middle technical staff, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection of the invention Range is subject to the view refined fine jade institute defender of right.

Claims (30)

1. a kind of coding/decoding method is used for reproducible nonvolatile memorizer module, deposits wherein the duplicative is non-volatile Memory modules include multiple solid elements, which is characterized in that the coding/decoding method includes:
First data are kept in buffer storage, wherein the buffer storage includes first buffering area and second buffering area；
The decoding data of the second buffering area is copied into the first buffering area；
In the first buffering area, first kind decoding behaviour is executed to first data based on the decoding data replicated Make, wherein the decoding data replicated is different from the raw decoded data corresponding to first data；And
If the first kind decoding operate success, exports decoding data.
2. coding/decoding method according to claim 1, further includes:
Encoded primary data corresponds to the raw decoded data of first data to generate；
The initial data is stored to an at least first instance unit；And
At least 1 the raw decoded data for corresponding to first data is stored in the multiple solid element Two solid elements.
3. coding/decoding method according to claim 1, further includes:
It is from least first instance unit reading initial data and real from least one second in the multiple solid element Body unit reads the raw decoded data for corresponding to first data；
The initial data is loaded into the buffer storage with the raw decoded data for corresponding to first data； And
In the first buffering area, based on the raw decoded data corresponding to first data to the initial data Execute the first kind decoding operate.
4. coding/decoding method according to claim 3, further includes:
The first kind solution is being executed to the initial data based on the raw decoded data for corresponding to first data Before code operation, the raw decoded data for corresponding to first data is copied into the second buffering area.
5. coding/decoding method according to claim 1, further includes:
The second class decoding operate is executed to more correction data based on the decoding data in the second buffering area, to update The decoding data in second buffering area is stated,
Wherein the more correction data is corrected via the first kind decoding operate.
6. coding/decoding method according to claim 5, wherein the more correction data does not include having and can not righting the wrong Data cell.
7. coding/decoding method according to claim 1, wherein the decoding data for copying to the first buffering area is base The decoding behaviour of one second class performed by the raw decoded data to more correction data and corresponding to first data Make and generates.
8. coding/decoding method according to claim 1, wherein the first kind decoding operate includes normal decoding mode and wipes Except mode, and the coding/decoding method further include:
According to the sum in first data with the data cell that can not be righted the wrong, determines to decode the first kind and grasp It operates in the normal decoding mode or the erasing mode.
9. coding/decoding method according to claim 1, wherein first data are in an at least first instance unit In by independent hard disk redundancy array error more code protect.
10. coding/decoding method according to claim 1, wherein the first kind decoding operate belongs to more frame decodings, and institute State coding/decoding method further include:
Single frame decoding is executed according to the decoding result of the first kind decoding operate, to verify the first kind decoding operate pair At least corrigendum of an error bit.
11. a kind of memory storage apparatus characterized by comprising
Connecting interface unit, to be connected to host system；
Reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module includes multiple entities Unit；And
Memorizer control circuit unit is connected to the connecting interface unit and the type nonvolatile mould Block,
Wherein the memorizer control circuit unit is keeping in the first data to buffer storage, wherein the buffer-stored Device includes first buffering area and second buffering area,
Wherein the memorizer control circuit unit is also to copy to described first for the decoding data of the second buffering area Buffer area,
Wherein the memorizer control circuit unit also in the first buffering area based on the solution yardage replicated First kind decoding operate is executed according to first data, wherein the decoding data replicated is different from corresponding to described the The raw decoded data of one data,
If the wherein first kind decoding operate success, the memorizer control circuit unit is also to export decoding data.
12. memory storage apparatus according to claim 11, wherein the memorizer control circuit unit is also to compile Code initial data corresponds to the raw decoded data of first data to generate,
Wherein the memorizer control circuit unit is also storing the initial data to an at least first instance list Member,
Wherein the memorizer control circuit unit is also to deposit the raw decoded data for corresponding to first data At least second instance unit being stored in the multiple solid element.
13. memory storage apparatus according to claim 11, wherein the memorizer control circuit unit is also to refer to Show and reads the initial data from an at least first instance unit and from least one second in the multiple solid element Solid element reads the raw decoded data for corresponding to first data,
Wherein the memorizer control circuit unit is also to by the initial data and corresponding to described in first data Raw decoded data is loaded into the buffer storage,
Wherein the memorizer control circuit unit in the first buffering area also to be based on corresponding to first data The raw decoded data first kind decoding operate is executed to the initial data.
14. memory storage apparatus according to claim 13, wherein based on corresponding to described in first data Before raw decoded data executes the first kind decoding operate to the initial data, the memorizer control circuit unit is also The raw decoded data for corresponding to first data is copied to the second buffering area.
15. memory storage apparatus according to claim 11, wherein the memorizer control circuit unit is also to base The decoding data in the second buffering area executes the second class decoding operate to more correction data, to update described second The decoding data in buffer area,
Wherein the more correction data is corrected via the first kind decoding operate.
16. memory storage apparatus according to claim 15, wherein the more correction data does not include that have can not be more The data cell of lookup error.
17. memory storage apparatus according to claim 11, wherein copying to the decoding of the first buffering area Data are based on the second class performed by the raw decoded data to more correction data and corresponding to first data Decoding operate and generate.
18. memory storage apparatus according to claim 11, wherein the first kind decoding operate includes normal decoding Mode and erasing mode, and the memorizer control circuit unit also to according in first data have can not correct mistake The sum of data cell accidentally determines the first kind decoding operate operating in the normal decoding mode or the erasing mould Formula.
19. memory storage apparatus according to claim 11, wherein first data are described at least one first It is protected in solid element by independent hard disk redundancy array error more code.
20. memory storage apparatus according to claim 11, wherein the first kind decoding operate belongs to more frame solutions Code, and the memorizer control circuit unit is also to execute single frame solution according to the decoding result of the first kind decoding operate Code, to verify corrigendum of the first kind decoding operate to an at least error bit.
21. a kind of memorizer control circuit unit, for controlling reproducible nonvolatile memorizer module, wherein described can answer The formula non-volatile memory module of writing includes multiple solid elements, which is characterized in that the wherein memorizer control circuit unit Include:
Host interface, to be connected to host system；
Memory interface, to be connected to the reproducible nonvolatile memorizer module；
Buffer storage；
Error checking and correcting circuit；And
Memory management circuitry is connected to the host interface, the memory interface, the buffer storage and the mistake Inspection and correcting circuit,
Wherein the memory management circuitry is keeping in the first data to the buffer storage, wherein the buffer-stored Device includes first buffering area and second buffering area,
Wherein the memory management circuitry is also to copy to first buffering for the decoding data of the second buffering area Area,
Wherein the error checking and correcting circuit in the first buffering area based on the decoding data replicated First kind decoding operate is executed to first data, wherein the decoding data replicated is different from corresponding to described first The raw decoded data of data,
If the wherein first kind decoding operate success, the memory management circuitry is also to export decoding data.
22. memorizer control circuit unit according to claim 21, wherein the error checking is also used with correcting circuit With encoded primary data to generate the raw decoded data for corresponding to first data,
Wherein the memory management circuitry is also storing the initial data to an at least first instance unit,
Wherein the memory management circuitry is also the raw decoded data for corresponding to first data to be stored in An at least second instance unit in the multiple solid element.
23. memorizer control circuit unit according to claim 21, wherein the memory management circuitry is also to refer to Show and reads the initial data from an at least first instance unit and from least one second in the multiple solid element Solid element reads the raw decoded data for corresponding to first data,
Wherein the memory management circuitry also to by the initial data with correspond to first data it is described original Decoding data is loaded into the buffer storage,
Wherein the error checking and correcting circuit in the first buffering area also to be based on corresponding to first data The raw decoded data first kind decoding operate is executed to the initial data.
24. memorizer control circuit unit according to claim 23, wherein based on corresponding to first data Before the raw decoded data executes the first kind decoding operate to the initial data, the memory management circuitry is also The raw decoded data for corresponding to first data is copied to the second buffering area.
25. memorizer control circuit unit according to claim 21, wherein the memorizer control circuit unit is also used To execute the second class decoding operate to more correction data based on the decoding data in the second buffering area, described in updating The decoding data in second buffering area,
Wherein the more correction data is corrected via the first kind decoding operate.
26. memorizer control circuit unit according to claim 25, wherein the more correction data does not include with nothing The data cell that method is righted the wrong.
27. memorizer control circuit unit according to claim 21, wherein copying to the described of the first buffering area Decoding data is based on performed by the raw decoded data to more correction data and corresponding to first data Two class decoding operates and generate.
28. memorizer control circuit unit according to claim 21, wherein the first kind decoding operate includes normal Decoding mode and erasing mode, and the memory management circuitry also to according in first data have can not correct mistake The sum of data cell accidentally determines the first kind decoding operate operating in the normal decoding mode or the erasing mould Formula.
29. memorizer control circuit unit according to claim 21, wherein first data are described at least one It is protected in first instance unit by independent hard disk redundancy array error more code.
30. memorizer control circuit unit according to claim 21, wherein the first kind decoding operate belongs to more news Frame decoding, and the memorizer control circuit unit is also to execute Dan Xun according to the decoding result of the first kind decoding operate Frame decoding, to verify corrigendum of the first kind decoding operate to an at least error bit.
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