CN109509499B - Decoding method, memory storage device and memory control circuit unit - Google Patents

Abstract

An exemplary embodiment of the present invention provides a decoding method, a memory storage device and a memory control circuit unit, including: temporarily storing the first data into a buffer memory, wherein the buffer memory comprises a first buffer area and a second buffer area; copying the decoded data of the second buffer to the first buffer; performing, in the first buffer, a first type of decoding operation on the first data based on the copied decoded data, wherein the copied decoded data is different from original decoded data corresponding to the first data; and outputting the decoded data if the first type of decoding operation is successful. Therefore, the efficiency of the decoding operation can be improved.

Description

Decoding method, memory storage device and memory control circuit unit

technical field

The invention relates to a decoding method, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for built-in Among the various portable multimedia devices listed above.

Generally speaking, in order to ensure the correctness of the data, the data will be encoded first and then stored in the rewritable non-volatile memory module. As data is read, it is decoded in an attempt to correct errors in it. If the errors in the data are corrected, the corrected data will be sent back to the host system. However, as the encoding/decoding technology gradually improves, the amount of data that needs to be temporarily stored during the encoding/decoding process may be greater than the capacity of the set buffer memory. Therefore, it is often necessary to repeatedly read specific data from the rewritable non-volatile memory module during the encoding/decoding process, thereby increasing the loss of the rewritable non-volatile memory module and reducing the encoding/decoding speed. Especially, in the iterative decoding operation, the above-mentioned situation is more remarkable.

Contents of the invention

An exemplary embodiment of the present invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve the efficiency of the decoding operation under the condition that the capacity of the buffer memory is limited.

An exemplary embodiment of the present invention provides a decoding method for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of physical units, the decoding method includes: The first data is temporarily stored in a buffer memory, wherein the buffer memory includes a first buffer and a second buffer; the decoded data of the second buffer is copied to the first buffer; in the first buffer region, performing a first type of decoding operation on said first data based on said copied decoded data, wherein said copied decoded data is different from the original decoded data corresponding to said first data; and if said The first type of decode operation succeeds, outputting the decoded data.

In an exemplary embodiment of the present invention, the decoding method further includes: encoding original data to generate the original decoded data corresponding to the first data; storing the original data in the first physical unit ; and storing the original decoded data corresponding to the first data in at least one second physical unit among the physical units.

In an exemplary embodiment of the present invention, the decoding method further includes: reading the original data from the first physical unit and reading the data corresponding to the second physical unit from at least one second physical unit among the physical units the original decoded data of a data; temporarily store the original decoded data and the original decoded data corresponding to the first data in the buffer memory; and in the first buffer, based on the corresponding performing the first type of decoding operation on the original decoded data of the first data.

In an exemplary embodiment of the present invention, the decoding method further includes: before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the corresponding The original decoded data based on the first data is copied to the second buffer.

In an exemplary embodiment of the present invention, the decoding method further includes: performing a second type of decoding operation on the corrected data based on the decoded data in the second buffer to update the second buffer The decoded data in , wherein the corrected data is corrected via the first type of decoding operation.

In an exemplary embodiment of the present invention, the first type of decoding operation includes a normal decoding mode and an erasure mode, and the decoding method further includes: according to the total number of data units with uncorrectable errors in the first data , decide to operate the first type of decoding operation in the normal decoding mode or the erasing mode.

In an exemplary embodiment of the present invention, the first type of decoding operation belongs to multi-frame decoding, and the decoding method further includes: performing single-frame decoding according to the decoding result of the first type of decoding operation to verify The first type of decoding operation corrects at least one erroneous bit.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module includes multiple physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to temporarily store the first data in a buffer memory, wherein the buffer The memory includes a first buffer and a second buffer, wherein the memory control circuit unit is also used to copy the decoded data of the second buffer to the first buffer, wherein the memory control circuit unit is also used to to perform a first type of decoding operation on the first data in the first buffer based on the copied decoded data, wherein the copied decoded data is different from the original decoded corresponding to the first data data, wherein if the first type of decoding operation is successful, the memory control circuit unit is further configured to output decoded data.

In an exemplary embodiment of the present invention, the memory control circuit unit is further used to encode original data to generate the original decoded data corresponding to the first data, wherein the memory control circuit unit is also used to encode the original data storing the original data in the first physical unit, wherein the memory control circuit unit is also used to store the original decoded data corresponding to the first data in at least one second physical unit in the physical unit .

In an exemplary embodiment of the present invention, the memory control circuit unit is also used to instruct to read the original data from the first physical unit and read the corresponding For the original decoded data of the first data, wherein the memory control circuit unit is further configured to temporarily store the original data and the original decoded data corresponding to the first data in the buffer memory, Wherein the memory control circuit unit is further configured to perform the first type of decoding operation on the original data in the first buffer based on the original decoded data corresponding to the first data.

In an exemplary embodiment of the present invention, before performing the first-type decoding operation on the original data based on the original decoded data corresponding to the first data, the memory control circuit unit is further configured to The original decoded data corresponding to the first data is copied to the second buffer.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to perform a second type of decoding operation on the corrected data based on the decoded data in the second buffer, so as to update the second buffer The decoded data in a region, wherein the corrected data is corrected via the first type of decoding operation.

In an exemplary embodiment of the present invention, the first type of decoding operation includes a normal decoding mode and an erasing mode, and the memory control circuit unit is further configured to detect data units with uncorrectable errors in the first data The total number is determined to operate the first type of decoding operation in the normal decoding mode or the erasing mode.

In an exemplary embodiment of the present invention, the first type of decoding operation belongs to multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation, to verify the correction of at least one erroneous bit by the decoding operation of the first type.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, wherein the The memory control circuit unit includes a host interface, a memory interface, a buffer memory, an error checking and correction circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, the buffer memory and the error checking and correction circuit, wherein the memory management circuit is configured to temporarily store the first data in the buffer memory, Wherein the buffer memory includes a first buffer and a second buffer, wherein the memory management circuit is also used to copy the decoded data of the second buffer to the first buffer, wherein the error check and a correction circuit for performing a first type of decoding operation on the first data in the first buffer based on the copied decoded data, wherein the copied decoded data is different from The original decoded data, wherein if the first type of decoding operation is successful, the memory management circuit is also used to output the decoded data.

In an exemplary embodiment of the present invention, the error checking and correction circuit is further configured to encode original data to generate the original decoded data corresponding to the first data, wherein the memory management circuit is further configured to encode the original data The original data is stored in the first physical unit, wherein the memory management circuit is further configured to store the original decoded data corresponding to the first data in at least one second physical unit in the physical unit.

In an exemplary embodiment of the present invention, the memory management circuit is further used to instruct to read the original data from the first physical unit and to read the corresponding The original decoded data of the first data, wherein the memory management circuit is further configured to temporarily store the original data and the original decoded data corresponding to the first data in the buffer memory, wherein the The error checking and correction circuit is further configured to perform the first type of decoding operation on the original data in the first buffer based on the original decoded data corresponding to the first data.

In an exemplary embodiment of the present invention, before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory management circuit is further configured to The original decoded data based on the first data is copied to the second buffer.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to perform a second type of decoding operation on the corrected data based on the decoded data in the second buffer, so as to update the second buffer The decoded data in a region, wherein the corrected data is corrected via the first type of decoding operation.

In an exemplary embodiment of the invention, the corrected data does not include data units with uncorrectable errors.

In an exemplary embodiment of the invention, said decoded data copied to said first buffer is based on a second type of decoding performed on corrected data and said original decoded data corresponding to said first data generated by the operation.

In an exemplary embodiment of the present invention, the first type of decoding operation includes a normal decoding mode and an erasing mode, and the memory management circuit is further configured to perform a data unit with an uncorrectable error in the first data according to The total number determines to operate the first type of decoding operation in the normal decoding mode or the erasing mode.

In an exemplary embodiment of the present invention, the first data is protected by a Redundant Array of Independent Disks error correction code in the first physical unit.

In an exemplary embodiment of the present invention, the first type of decoding operation belongs to multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation, to verify the correction of at least one erroneous bit by the decoding operation of the first type.

Based on the above, the present invention can save the decoded data dynamically generated during the decoding process in the buffer memory. When the first data is to be decoded subsequently, the decoded data can be used immediately without repeatedly reading relevant data from the rewritable non-volatile memory module and obtaining it repeatedly. Thereby, the efficiency of the decoding operation can be improved under the condition that the capacity of the buffer memory is limited.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

FIG. 7 is a schematic diagram of multi-frame coding according to an exemplary embodiment of the present invention.

8 to 11 are schematic diagrams showing decoding operations according to an exemplary embodiment of the present invention.

FIG. 12 and FIG. 13 are flowcharts of a decoding method according to an exemplary embodiment of the present invention.

Explanation of reference numbers

10, 30: memory storage device

11, 31: host system

110: System bus

111: Processor

112: random access memory

113: ROM

114: data transmission interface

12: Input/Output (I/O) device

20: Motherboard

201: U disk

202: memory card

203: SSD

204: Wireless memory storage device

205: Global Positioning System Module

206: Network interface card

207: Wireless transmission device

208: Keyboard

209: screen

210: Horn

32: SD card

33: CF card

34: Embedded storage device

341: Embedded multimedia card

342: Embedded multi-chip package storage device

402: Connect the interface unit

404: memory control circuit unit

406: Rewritable non-volatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: Error checking and correction circuit

510: buffer memory

512: Power management circuit

601: storage area

602: Replacement area

610(0)～610(B), 710(0)～710(E): entity unit

612(0)～612(C): logic unit

701(1)～701(r): Position

830, 831, 832, 833, 1001, 1002: data

720, 840, 841, 941, 942: decoded data

810, 820: buffer

S1201: step (reading original data and original decoded data from the rewritable non-volatile memory module)

S1202: Step (temporarily storing the original data and the original decoded data in the buffer memory)

S1203: Step (copying the original decoded data to the second buffer of the buffer memory)

S1204: Step (in the first buffer memory of the buffer memory, perform a first type of decoding operation on the original data based on the original decoded data)

S1205: step (judging whether the first type of decoding operation is successful)

S1206: Step (output decoded decoded data)

S1301: Step (reading the first data from the rewritable non-volatile memory module and temporarily storing the first data in the buffer memory)

S1302: step (copy the decoded data in the second buffer to the first buffer)

S1303: Step (in the first buffer, perform a first type of decoding operation on the first data based on the copied decoded data)

S1304: step (judging whether the first type of decoding operation is successful)

S1305: Step (output decoded data)

S1306: step (judging whether there is data corrected in the first type of decoding operation)

S1307: Step (perform a second type of decoding operation on the corrected data based on the decoded data in the second buffer to update the decoded data)

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , random access memory 112 , ROM 113 and data transmission interface 114 are all connected to a system bus 110 .

In this exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114 . In addition, the host system 11 is connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be connected to the memory storage device 10 via wire or wirelessly. The memory storage device 10 may be, for example, a USB flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy storage device (for example, iBeacon ) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I/Os such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 3 , in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. Various non-volatile memory storage devices such as a secure digital (Secure Digital, SD) card 32 , a compact flash (Compact Flash, CF) card 33 or an embedded storage device 34 . The embedded storage device 34 includes various types such as an embedded multimedia card (embedded Multi MediaCard, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342, etc., which directly connect the memory module to the substrate of the host system on the embedded storage device.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11 . In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a device conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, Peripheral Component Interconnect Express (PCIExpress) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard , Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (Universal Flash Storage , UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or solid state and write data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11, Operations such as reading and erasing.

The rewritable non-volatile memory module 406 is connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level storage unit (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in a storage unit), a multi-level Storage unit (Multi Level Cell, MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a storage unit), complex level storage unit (Triple Level Cell, TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in one storage unit), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (also referred to as threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a writing voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. The operation of changing the threshold voltage of the memory cell is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple storage states. Which storage state a memory cell belongs to can be determined by applying a read voltage, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the storage units of the rewritable non-volatile memory module 406 constitute a plurality of physical programming units, and these physical programming units constitute a plurality of physical erasing units. Specifically, the storage units on the same word line form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a storage unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a storage unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit will be greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the programmatic unit.

In this exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page (page) or an entity sector (sector). If the physical programming units are physical pages, these physical programming units usually include data bit areas and redundancy (redundancy) bit areas. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bits (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 , a memory interface 506 , an error checking and correction circuit 508 and a buffer memory 510 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 502 below, it is equivalent to describing the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in solid form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a specific area of the rewritable non-volatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) in the form of program codes. middle. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instructions in 406 are loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The storage unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The storage unit management circuit is used for managing the storage units or groups thereof of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasing circuit is used for issuing an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 502 can also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 504 is connected to the memory management circuit 502 and is used for receiving and identifying commands and data transmitted by the host system 11 . That is to say, the commands and data sent by the host system 11 are sent to the memory management circuit 502 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standard, IEEE 1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is connected to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable nonvolatile memory module 406 will be converted into a format acceptable to the rewritable nonvolatile memory module 406 via the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit the corresponding instruction sequence. For example, these command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and instructions for various memory operations such as changing the read the corresponding sequence of instructions to fetch voltage levels or perform garbage collection operations, etc.). These instruction sequences are, for example, generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program codes. For example, in the read command sequence, information such as read identification code and memory address will be included.

The error checking and correction circuit 508 is connected to the memory management circuit 502 and configured to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correction code (error correcting code, ECC) and /or error checking code (error detecting code, EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable non-volatile memory In module 406. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 will be based on The error correcting code and/or error checking code performs error checking and correcting operations on the read data.

The buffer memory 510 is connected to the memory management circuit 502 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . In an exemplary embodiment, the memory control circuit unit 404 further includes a power management circuit 512 . The power management circuit 512 is connected to the memory management circuit 502 and used to control the power of the memory storage device 10 .

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , the memory management circuit 502 logically groups the physical units 610 ( 0 )˜ 610 (B) of the rewritable non-volatile memory module 406 into a storage area 601 and a replacement area 602 . The physical units 610(0)-610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)-610(B) in the replacement area 602 are used to replace the data in the storage area 601 Damaged solid elements. For example, if the data read from a certain physical unit contains too many errors to be corrected, the physical unit will be regarded as a damaged physical unit. It should be noted that if there is no available physical erasing unit in the replacement area 602 , the memory management circuit 502 may declare the entire memory storage device 10 as a write-protected state, and data cannot be written any more.

In this exemplary embodiment, each physical unit refers to a physical programming unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical erase unit, or consist of multiple continuous or discontinuous physical addresses. The memory management circuit 502 configures the logic units 612 ( 0 )˜ 612 (C) to map the physical units 610 ( 0 )˜ 610 (A) in the storage area 601 . In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logical unit may also refer to a logical programming unit, a logical erasing unit, or consist of multiple consecutive or discontinuous logical addresses. Furthermore, each of logical units 612(0)-612(C) may be mapped to one or more physical units.

The memory management circuit 502 records the mapping relationship between the logical unit and the physical unit (also referred to as the logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 intends to read data from or write data to the memory storage device 10 , the memory management circuit 502 can perform a data access operation to the memory storage device 10 according to the logical-physical address mapping table.

In this exemplary embodiment, the basic unit for the error checking and correction circuit 508 to execute the encoding process is a frame (also called a decoding frame). A frame includes multiple data bits. In this exemplary embodiment, a frame includes 256 bits. However, in another exemplary embodiment, a frame may also include more (eg 4K bytes) or less bits.

In this exemplary embodiment, the error checking and correction circuit 508 can perform single-frame encoding and decoding on data stored in the same physical unit, or can perform single-frame encoding and decoding on data stored in multiple physical units. Multi-frame (multi-frame) encoding and decoding. The single-frame coding and the multi-frame coding can respectively adopt at least one of coding algorithms such as low density parity correction code (low density parity code, LDPC), BCH code, convolutional code or turbo code. one. Alternatively, in an exemplary embodiment, the multi-frame coding may also use Reed-Solomon codes (Reed-solomon codes, RS codes) algorithm. In addition, in another exemplary embodiment, more encoding algorithms not listed above may also be adopted, so details will not be described here. According to the encoding algorithm used, the ECC circuit 508 can encode the data to be protected to generate corresponding ECC codes and/or ECC codes. For the convenience of description, the error correction codes and/or error check codes generated through encoding are collectively referred to as decoded data (ie, data used for decoding) hereinafter. In an exemplary embodiment, the decoded data generated through encoding is also referred to as parity data.

FIG. 7 is a schematic diagram of multi-frame coding according to an exemplary embodiment of the present invention.

Please refer to FIG. 7, taking the data stored in the encoding entity units 710(0)-710(E) to generate the corresponding decoded data 720 as an example, each of the entity units 710(0)-710(E) At least part of the stored data can be considered as a frame. In multi-frame coding, the data in the physical units 710(0)-710(E) are coded based on the position of each bit (or bit group). _{For example} , bits b _{11 ,} b ₂₁ , _{. p2} will be encoded as bit b _o2 in decoded data 720 ; and so on, bits b _1r , b _2r , . . . , b _pr at position 701(r) will be encoded as bit b _or in decoded data 720 .

In an exemplary embodiment, the physical units 710 ( 0 )˜710 (E) are also called first physical units, and the physical units for storing the decoded data 720 are called second physical units. Both the number of the first physical unit and the number of the second physical unit can be more or less. In an exemplary embodiment, the decoded data 720 is generated by encoding specific data (also referred to as original data) in the physical units 710(0)-710(E), so the decoded data 720 can be regarded as corresponding to the original data the original decoded data. In an exemplary embodiment, it can be considered that the original data is protected by the decoded data 720 in the physical units 710(0)˜710(E). In an exemplary embodiment, the decoded data 720 can also be regarded as a redundant array of independent disks (Redundant Array of Independent Disks, RAID) error correction code. Based on decoded data 720, data read from physical units 710(0)-710(E) may be decoded in an attempt to correct possible errors in the read data.

In an exemplary embodiment, the data used to generate the decoded data 720 may also include redundant bits corresponding to data bits in the data stored in the physical units 710(0)˜710(E). Taking the data stored in the physical unit 710(0) as an example, the redundant bits are generated by performing single-frame coding on the data bits stored in the physical unit 710(0).

In an exemplary embodiment, when data stored in a certain physical unit (also referred to as target data) is to be read, single-frame decoding corresponding to the target data may be performed first. For example, if the target data is single-frame encoded based on LDPC codes, the target data will also be single-frame decoded based on LDPC codes. If the single-frame decoding corresponding to the target data fails, then the multi-frame decoding corresponding to the target data is performed sequentially, for example, based on the RS code used during encoding.

In an exemplary embodiment, single-frame decoding and multi-frame decoding may be performed alternately until it is determined that decoding fails or succeeds. Taking FIG. 7 as an example, when the target data stored in the physical unit 710(0) is to be read, the first single-frame decoding corresponding to the target data to be read in the physical unit 710(0) will be executed first , to try to correct possible errors. If the first single-frame decoding corresponding to the target data fails, the decoded data 720 and the data used to generate the decoded data 720 in the physical units 710(1)-710(E) will be read out and correspond to the target data The first multiframe decoding can be performed. If the first multiframe decoding corresponding to the target data fails, then according to the execution result of the first multiframe decoding (for example, some bits in the target data may have been corrected), the first multiframe corresponding to the target data may be corrected. A second single-frame decoding can be performed. If the second single-frame decoding still fails, the second multi-frame decoding corresponding to the target data can be performed. By analogy, after performing at least one single-frame decoding and/or at least one multi-frame decoding on the target data, errors in the target data should be corrected gradually. If a certain single-frame decoding or multi-frame decoding successfully corrects all errors in the target data, the corresponding iterative decoding may stop. Alternatively, if the number of single-frame decoding and/or multi-frame decoding performed on the same target data reaches a threshold value, it may be determined that the decoding fails.

In an exemplary embodiment, after completing a certain multi-frame decoding corresponding to the target data (errors may still exist in the target data), at least one single-frame decoding can be performed according to the decoding result of the multi-frame decoding . This single-frame decoding verifies that at least one erroneous bit was corrected in the previous multi-frame decoding. If the decoding result of the single frame decoding reflects that the previous correction to an erroneous bit is correct, the correction of the erroneous bit can be kept. Conversely, if the decoding result of the single-frame decoding reflects that the previous correction of an erroneous bit is not correct, the correction of the erroneous bit can be canceled so that the bit value of the erroneous bit returns to its initial value.

8 to 11 are schematic diagrams showing decoding operations according to an exemplary embodiment of the present invention. Please refer to FIG. 8 , the buffer memory 510 includes buffers 810 and 820 . Buffer 810 is also called a first buffer, and buffer 820 is also called a second buffer. In an exemplary embodiment, the capacity of the buffer 810 may be the same or approximately the same as the capacity of the buffer 820 . In an exemplary embodiment, the capacity of the buffer 820 is smaller than that of the buffer 810 . In an exemplary embodiment, the buffers 810 and 820 can be dynamically configured by the memory management unit 502 of FIG. 5 .

When it is determined that multi-frame decoding corresponding to the data 831 needs to be performed, the data 830 and the decoded data 840 corresponding to the data 830 are read from the first physical unit and the second physical unit respectively. Data 830 includes data 831 and 832 . The data 831 is the target data to be decoded and corrected based on the decoded data 840 , and the data 832 is the remaining data for generating the decoded data 840 . Taking FIG. 7 as an example, if the data 831 is data stored in the physical unit 710(0), then the data 832 may be at least part of the data stored in the physical units 710(1)-710(E).

In an exemplary embodiment, data 830 may be regarded as original data, and decoded data 840 may be regarded as original decoded data corresponding to data 830 , data 831 and/or 832 . The data 830 and the decoded data 840 are loaded into the buffer memory 510 . For example, the data 830 and the decoded data 840 are temporarily stored in the buffer 810 . It should be noted that, before decoding the data 830 based on the decoded data 840 , the decoded data 840 will be copied to the buffer 820 to become the decoded data 841 . After copying the decoded data 840 to the buffer 820 , the data 830 can be decoded in the buffer 810 based on the decoded data 840 .

In an exemplary embodiment, since the capacity of the buffer memory 510 (or the buffer memory 810) is not enough to store the complete data 830 at one time (that is, the total data volume of the data 830 is greater than the capacity of the buffer memory 510 or the buffer memory 810), therefore Data 830 may be stored into buffer 810 in batches and decoded in batches based on decoded data 840 . It should be noted that, in an exemplary embodiment, in the process of decoding data 830 in batches, data 831 will continue to be maintained and/or remain in buffer 810 until data 831 is successfully decoded and/or corrected until.

In an exemplary embodiment, corresponding to the decoding performed in the buffer 810, at least some bits in the decoded data 840 may be updated, so that the updated decoded data 840 in the buffer 810 may be compared with the previously stored bits in the buffer 820. The decoded data of 841 is different. In an exemplary embodiment, corresponding to the decoding performed in the buffer 810, the decoded data 840 will be updated as syndrome data. This check data may reflect the decoding status or decoding results of the decoding performed on the data 830 .

Referring to FIG. 9 , it is assumed that according to the decoding performed in the buffer 810, data 833 in data 830 is corrected, but data 831 is not yet corrected. In an exemplary embodiment, the data 833 is also referred to as corrected data. After correcting data 833 , based on decoded data 841 in buffer 820 , data 833 is decoded. During the process of decoding the data 833 based on the decoded data 841 , at least some bits in the decoded data 841 may also be updated. The updated decoded data 841 will be kept in the buffer 820 continuously. It should be noted that, in an exemplary embodiment, the decoded data 841 in the buffer 820 will only be used for the corrected data in the decoded data 830 (ie, data 833 ), and will not be used in the uncorrected data in the decoded data 830 The data. In addition, the updated decoded data 841 may also be referred to as check data corresponding to the data 833 to reflect the decoding status or decoding result of the decoding performed on the data 833 .

In an exemplary embodiment, corrections to data 833 based on decoded data 840 are still subject to verification corresponding to single frame decoding of data 833 . For example, in an exemplary embodiment of FIG. 9, after data 833 is corrected based on decoded data 840, single frame decoding corresponding to data 833 is performed. If the decoding result of the single frame decoding reflects that the correction of the erroneous bits in the data 833 is correct, the correction result of the data 833 can be kept. On the contrary, if the decoding result of this single frame decoding reflects that the correction of the erroneous bits in the data 833 is not correct, then the correction result of the data 833 can be canceled, so that some of the corrected bits in the data 833 will be returned to their Raw bit value.

In an exemplary embodiment, the decoding operations in FIG. 8 and FIG. 9 can be regarded as the first multi-frame decoding for the data 831 . This first multiframe decoding is performed to correct errors in the data 831 . For example, the data 831 may be the data instructed to be read by a certain read command from the host system. If the errors in the data 831 are not completely corrected, the first multiframe decoding will be judged as failed.

Referring to FIG. 10 , if the first multi-frame decoding of the data 831 fails, the data 1001 can be re-read from the first physical unit. It should be noted that continuing the exemplary embodiments of FIG. 8 and FIG. 9 , the data 831 can be continuously stored in the buffer 810 without re-reading from the first physical unit along with the data 1001 . In an exemplary embodiment, the data 1001 is also referred to as first data. The data 1001 may not include the corrected data 833 in the exemplary embodiment of FIG. 9 . The data 1001 will be loaded into the buffer memory 510 , for example, temporarily stored in the buffer 810 .

Before decoding the data 831 and 1001 , the decoded data 941 is copied from the buffer 820 to the buffer 810 to become the decoded data 942 . It should be noted that the decoded data 941 is used to represent the updated decoded data 841 in the buffer 820 in FIG. 9 . In other words, the data content of the decoded data 941 is the same as the updated decoded data 841 in the buffer 820 of FIG. 9 . After copying the decoded data 941 from the buffer 820 to the buffer 810 , based on the decoded data 942 , the data 831 and 1001 are decoded in the buffer 810 .

It should be noted that in the exemplary embodiment of FIG. 10 , the decoded data 942 for the decoded data 831 and 1001 is copied from the buffer 820 instead of being read from the second physical unit. Therefore, the decoded data 942 for the decoded data 831 and 1001 in FIG. 10 is different from the decoded data 840 in FIGS. 8 and 9 . In an exemplary embodiment, the decoded data 840 in FIG. 8 and FIG. 9 can also be regarded as the original decoded data corresponding to the data 1001 . In addition, because the capacity of the buffer memory 510 or the buffer memory 810 is not enough to store the complete data 1001 at one time (that is, the total data volume of the data 1001 is greater than the capacity of the buffer memory 510 or the buffer memory 810), the data 1001 may also be divided into batches are stored in buffer 810 and decoded in batches based on decoded data 942 . In addition, data 1001 batched into buffer 810 for decoding will not overwrite data 831 .

Referring to FIG. 11 , suppose that according to the decoding performed in the buffer 810 in FIG. 10 , the data 1002 is corrected, but the data 831 is still not corrected. In an exemplary embodiment, data 1002 is also referred to as corrected data. In an exemplary embodiment, the correction to the data 1002 is also verified by the single-frame decoding corresponding to the data 1002 to determine the correctness of the correction to the data 1002 . After correcting data 1002 , based on decoded data 941 in buffer 820 , data 1002 is decoded. During the process of decoding the data 1002 based on the decoded data 941 , at least some bits in the decoded data 941 may also be updated. The updated decoded data 941 will be kept in the buffer 820 for the next iterative decoding corresponding to the data 831 .

Similar to the exemplary embodiment of FIG. 9, in an exemplary embodiment of FIG. 11, the decoded data 941 in the buffer 820 will only be used for decoding the corrected data (ie, data 1002), and will not be used for decoding Corrected data (eg, data 831 or uncorrected data in data 1001 of FIG. 10 ). The updated decoded data 941 may also be referred to as check data corresponding to the data 1002 to reflect the decoding status or decoding result of the decoding performed on the data 1002 . So far, it can be considered that the second multi-frame decoding of the data 831 is completed. This second multiframe decoding is also performed to correct errors in the data 831 . In the exemplary embodiment of FIG. 11 , if the errors in the data 831 are not completely corrected, then the second multi-frame decoding is also judged as failed.

If the second multi-frame decoding still fails, the operation of reading the first data that does not include the target data and the updated data in the exemplary embodiment of FIG. 10 and FIG. 11 copies the decoded data from the second buffer to Operation of the first buffer, decoding and data correction in the first buffer, decoding of corrected data based on the decoded data in the second buffer, and updating of the decoded data in the second buffer can be executed repeatedly until the error in the target data stored in the first buffer is successfully corrected. In addition, the decoding operations in FIGS. 8 to 11 can be performed by the memory management circuit 502 in FIG. 5 together with the error checking and correction circuit 508 .

In an exemplary embodiment, the decoding based on the decoded data copied into the first buffer (for example, the decoded data 840 in FIG. 8 and the decoded data 942 in FIG. 10 ) is also referred to as the first type of decoding operation, and The decoding performed on the decoded data stored in the second buffer (eg, the decoded data 841 in FIG. 9 and the decoded data 941 in FIG. 11 ) is also referred to as a second type of decoding operation.

In an exemplary embodiment, data decoded by the first type of decoding operation (such as raw data and/or first data) may include data units with uncorrectable (abbreviated as UNC) errors, while data decoded by the second type of decoding operation The data (such as corrected data) will not include data units with UNC errors. Here, UNC errors refer to errors that cannot be corrected by corresponding single-frame decoding. Taking FIG. 7 as an example, assuming that a data unit refers to a frame, if a certain data unit stored in the physical unit 710(0) cannot successfully correct the error in the single frame decoding corresponding to the data unit, Then this data unit can be regarded as a data unit with UNC error. Or, if a certain data unit stored in the physical unit 710(1) can successfully correct the error therein through single-frame decoding corresponding to this data unit, then this data unit can be regarded as a UNC error-free data unit.

In an exemplary embodiment, the first type of decoding operation includes a normal decoding mode and an erasure mode. According to the total number of data units with UNC errors in the data to be decoded (for example, data 830 in FIG. 8 or data 831 and 1001 in FIG. 10 ), the first type of decoding operation can be decided to operate in normal decoding mode or erase model. In an exemplary embodiment, if the total number of data units with UNC errors in the data to be decoded is greater than or equal to a predetermined value, such as 2, but not limited thereto, the first type of decoding corresponding to the data to be decoded is performed The operation will be operated in normal decoding mode. If the total number of data units with UNC errors in the data to be decoded is less than a predetermined value, the first type of decoding operation performed corresponding to the data to be decoded will be operated in an erase mode. In the erasing mode, the first type of decoding operation can usually guarantee to complete the decoding and correction of the data to be decoded (or target data).

In the exemplary embodiment of FIG. 9 or FIG. 11 , the data to be decoded in the buffer 810 may include at least one data unit with a UNC error. Corresponding to the first type of decoding operation performed on the data to be decoded, a certain data unit with a UNC error in the buffer 810 may be corrected to a data unit without a UNC error. Such data units without UNC errors may be considered corrected data. In multiple iterative decodings performed consecutively, the first data read from the first physical unit and loaded into the buffer 810 each time may not include data units that have no UNC error. Thereby, the number of data units with UNC errors in the data to be decoded can be gradually reduced during multiple iterative decodings performed continuously, thereby improving the success rate of decoding.

It should be noted that, in the aforementioned exemplary embodiments of FIG. 8 to FIG. 11 , only when the first type of decoding operation is performed on the original data, the original decoded data corresponding to the first data (or original data) will be is read from the second entity unit. In the first type of decoding operation performed after the second time, the decoded data used to decode the first data is all copied from the second buffer. Furthermore, in the (decoding) operation of updating the decoded data stored in the second buffer, the update of the decoded data in the second buffer is only affected by data units that do not have UNC errors, thereby reducing the The probability that the decoded data is affected by erroneous bits (or UNC errors). Therefore, after copying the decoded data from the second buffer to the first buffer, the decoding success rate of the first type of decoding operation performed in the first buffer based on the copied decoded data can be improved.

FIG. 12 and FIG. 13 are flowcharts showing decoding operations according to an exemplary embodiment of the present invention. Please refer to FIG. 12 , in step S1201 , the original data and the original decoded data corresponding to the first data (or original data) are read from the rewritable non-volatile memory module. In step S1202, the original data and the original decoded data corresponding to the first data are temporarily stored in a first buffer (eg, buffer 810 in FIG. 8 ) of a buffer memory (eg, buffer 510 in FIG. 8 ). In step S1203, the original decoded data corresponding to the first data is copied to the second buffer of the buffer memory (for example, the buffer 820 in FIG. 8). In step S1204, in the first buffer memory of the buffer memory, a first type of decoding operation is performed on the original data based on the original decoded data corresponding to the first data. In step S1205, it is judged whether the first type of decoding operation corresponding to the original data is successful. If yes (that is, the first type of decoding operation succeeds), in step S1206, output the data that has been successfully decoded (also referred to as decoded data). If not (that is, the first type of decoding operation fails), go to step S1301 in FIG. 13 .

Please refer to FIG. 13 , in step S1301 , read first data from the rewritable non-volatile memory module and temporarily store the first data into a first buffer of the buffer memory. It should be noted that the first data may not include the target data persistently stored in the first buffer and the corrected data that has been corrected in the previous first type of decoding operation. In step S1302, copy the decoded data in the second buffer to the first buffer. In step S1303, in the first buffer zone, a first type of decoding operation is performed on the first data and the target data based on the copied decoded data. In step S1304, it is judged whether the first type of decoding operation is successful. If yes, in step S1305, output the decoded data. If not, in step S1306, it is determined whether any data (or data unit) is corrected in the first type of decoding operation. If not (that is, no data (or data unit) is corrected in the first type of decoding operation), go back to step S1301 and re-execute the next iterative decoding. If there is (that is, there is data (or data unit) that is corrected in the first type of decoding operation), in step S1307, based on the decoded data in the second buffer, a second operation is performed on the corrected data (that is, the corrected data) Decode-like operation to update the decoded data in the second buffer. The decoded data updated based on the corrected data is continuously stored in the second buffer for use in the next iterative decoding. After step S1307, step S1301 may be executed repeatedly. In addition, in the exemplary embodiments of FIG. 12 and FIG. 13 , if a number of execution times of the performed decoding operation reaches a threshold value, the decoding operation may be judged to be failed and stopped.

In an exemplary embodiment, steps S1206 and/or S1305 may also include copying successfully decoded data (for example, target data) to other entity units for re-storage, and copying the entity that originally stored the data (for example, target data) The erase unit is marked as a damaged physical erase unit. In addition, more error handling means can also be executed in step S1206 and/or S1305, which is not limited by the present invention.

However, each step in FIG. 12 and FIG. 13 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 12 and FIG. 13 can be implemented as a plurality of program codes or circuits, which is not limited in the present invention. In addition, the methods shown in FIG. 12 and FIG. 13 can be used together with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

To sum up, the present invention can continuously save the decoded data dynamically generated during the decoding process in the buffer memory. When the target data is to be repeatedly decoded subsequently, the decoded data stored in the buffer memory can be used immediately without repeatedly reading relevant data from the rewritable non-volatile memory module and obtaining it repeatedly. In addition, the present invention can also reduce the influence of UNC errors on the decoded data stored in the buffer memory. Thereby, the efficiency of the decoding operation can be improved under the condition that the capacity of the buffer memory is limited.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be subject to what is defined by the right Yaqi.

Claims (30)

1. A decoding method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, the decoding method comprising:

temporarily storing first data to a first buffer area in a buffer memory, wherein the buffer memory comprises the first buffer area and a second buffer area;

copying the decoded data of the second buffer to the first buffer to decode the first data;

performing, in the first buffer, a first type of decoding operation on the first data based on the copied decoded data, wherein the first type of decoding operation includes at least one decoding operation performed in the first buffer; and

and outputting the decoded data if the first type of decoding operation is successful.

2. The decoding method of claim 1, further comprising:

encoding original data to generate original decoded data corresponding to the first data;

storing the original data to at least one first entity unit; and

storing the original decoded data corresponding to the first data in at least a second physical unit of the plurality of physical units.

3. The decoding method of claim 1, further comprising:

reading original data from at least one first entity unit and original decoded data corresponding to the first data from at least one second entity unit of the plurality of entity units;

loading the original data and the original decoded data corresponding to the first data into the buffer memory; and

performing, in the first buffer, the first type of decoding operation on the original data based on the original decoded data corresponding to the first data.

4. The decoding method of claim 3, further comprising:

copying the original decoded data corresponding to the first data to the second buffer before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data.

5. The decoding method of claim 1, further comprising:

performing a second type of decoding operation on the corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer,

wherein the corrected data is corrected via the first type of decoding operation.

6. The decoding method according to claim 5, wherein the corrected data does not include data units having uncorrectable errors.

7. The decoding method according to claim 1, wherein the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on the corrected data and original decoded data corresponding to the first data.

8. The decoding method of claim 1, wherein the first class of decoding operations comprises a normal decoding mode and an erasure mode, and the decoding method further comprises:

and determining to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to the total number of data units with uncorrectable errors in the first data.

9. The decoding method according to claim 1, wherein the first data is protected by RAID ECC in at least a first physical unit.

10. The decoding method of claim 1, wherein the first type of decoding operation belongs to multi-frame decoding, and the decoding method further comprises:

and performing single-frame decoding according to the decoding result of the first type of decoding operation to verify the correction of the first type of decoding operation on at least one error bit.

11. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of entity units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for temporarily storing the first data into a first buffer area in a buffer memory, wherein the buffer memory comprises the first buffer area and a second buffer area,

wherein the memory control circuit unit is further to copy decoded data of the second buffer to the first buffer to decode the first data,

wherein the memory control circuitry unit is further to perform a first type of decoding operation on the first data in the first buffer based on the copied decoded data, wherein the first type of decoding operation includes at least one decoding operation performed in the first buffer,

wherein the memory control circuit unit is further configured to output decoded data if the first type of decoding operation is successful.

12. The memory storage device of claim 11, wherein the memory control circuitry unit is further to encode original data to produce original decoded data corresponding to the first data,

wherein the memory control circuit unit is further configured to store the raw data to at least a first physical unit,

wherein the memory control circuitry unit is further to store the original decoded data corresponding to the first data in at least a second physical unit of the plurality of physical units.

13. The memory storage device of claim 11, wherein the memory control circuitry unit is further to instruct reading original data from at least a first physical unit and reading original decoded data corresponding to the first data from at least a second physical unit of the plurality of physical units,

wherein the memory control circuit unit is further configured to load the original data and the original decoded data corresponding to the first data into the buffer memory,

wherein the memory control circuitry unit is further to perform the first type of decoding operation on the original data in the first buffer based on the original decoded data corresponding to the first data.

14. The memory storage device of claim 13, wherein prior to performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory control circuitry unit is also to copy the original decoded data corresponding to the first data to the second buffer.

15. The memory storage device of claim 11, wherein the memory control circuitry unit is further to perform a second type of decoding operation on corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer,

wherein the corrected data is corrected via the first type of decoding operation.

16. The memory storage device of claim 15, wherein the corrected data does not include data units having uncorrectable errors.

17. The memory storage device of claim 11, wherein the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on corrected data and original decoded data corresponding to the first data.

18. The memory storage device of claim 11, wherein the first type of decoding operation comprises a normal decoding mode and an erasure mode, and the memory control circuit unit is further configured to determine to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to a total number of data units in the first data having uncorrectable errors.

19. The memory storage device of claim 11, wherein the first data is protected in at least a first physical unit by redundant array of independent disks error correction code.

20. The memory storage device of claim 11, wherein the first type of decoding operation is multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation to verify correction of at least one erroneous bit by the first type of decoding operation.

21. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, wherein the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

a buffer memory;

an error checking and correcting circuit; and

memory management circuitry connected to the host interface, the memory interface, the buffer memory, and the error checking and correction circuitry,

wherein the memory management circuit is used for temporarily storing the first data to a first buffer area in the buffer memory, wherein the buffer memory comprises the first buffer area and a second buffer area,

wherein the memory management circuitry is further to copy decoded data of the second buffer to the first buffer to decode the first data,

wherein the error checking and correcting circuit is configured to perform a first type of decoding operation on the first data based on the copied decoded data in the first buffer, wherein the first type of decoding operation comprises at least one decoding operation performed in the first buffer,

wherein the memory management circuit is further configured to output decoded data if the first type of decoding operation is successful.

22. The memory control circuitry unit of claim 21, wherein the error checking and correction circuitry is further to encode raw data to produce raw decoded data corresponding to the first data,

wherein the memory management circuit is further configured to store the raw data to at least a first physical unit,

wherein the memory management circuitry is also to store the original decoded data corresponding to the first data in at least a second physical unit of the plurality of physical units.

23. The memory control circuit unit of claim 21, wherein the memory management circuit is further configured to instruct reading original data from at least a first physical unit and reading original decoded data corresponding to the first data from at least a second physical unit of the plurality of physical units,

wherein the memory management circuit is further to load the original data and the original decoded data corresponding to the first data into the buffer memory,

wherein the error checking and correcting circuit is further configured to perform the first type of decoding operation on the original data in the first buffer based on the original decoded data corresponding to the first data.

24. The memory control circuitry unit of claim 23, wherein prior to performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory management circuitry is further to copy the original decoded data corresponding to the first data to the second buffer.

25. The memory control circuit unit of claim 21, wherein the memory control circuit unit is further configured to perform a second type of decoding operation on corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer,

wherein the corrected data is corrected via the first type of decoding operation.

26. The memory control circuit unit of claim 25, wherein the corrected data does not include data cells with uncorrectable errors.

27. The memory control circuit unit of claim 21, wherein the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on corrected data and original decoded data corresponding to the first data.

28. The memory control circuit unit of claim 21, wherein the first type of decoding operation comprises a normal decoding mode and an erasure mode, and the memory management circuit is further configured to determine to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to a total number of data units in the first data having uncorrectable errors.

29. The memory control circuit unit of claim 21, wherein the first data is protected by redundant array of independent disks error correction code in at least a first physical unit.

30. The memory control circuit unit of claim 21, wherein the first type of decoding operation is multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation to verify the correction of at least one erroneous bit by the first type of decoding operation.

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