CN109509499B

CN109509499B - Decoding method, memory storage device and memory control circuit unit

Info

Publication number: CN109509499B
Application number: CN201710825756.3A
Authority: CN
Inventors: 仇志良
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2017-09-14
Filing date: 2017-09-14
Publication date: 2023-02-28
Anticipated expiration: 2037-09-14
Also published as: CN109509499A

Abstract

An exemplary embodiment of the present invention provides a decoding method, a memory storage device and a memory control circuit unit, including: temporarily storing the first data into a buffer memory, wherein the buffer memory comprises a first buffer area and a second buffer area; copying the decoded data of the second buffer to the first buffer; performing, in the first buffer, a first type of decoding operation on the first data based on the copied decoded data, wherein the copied decoded data is different from original decoded data corresponding to the first data; and outputting the decoded data if the first type of decoding operation is successful. Therefore, the efficiency of the decoding operation can be improved.

Description

Decoding method, memory storage device and memory control circuit unit

Technical Field

The invention relates to a decoding method, a memory storage device and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, to ensure the correctness of data, the data is encoded and then stored in the rewritable nonvolatile memory module. When reading data, the data is decoded to attempt to correct errors therein. If the errors in the data are all corrected, the corrected data is transmitted back to the host system. However, as the encoding/decoding technology gradually advances, the data amount of the data to be temporarily stored in the encoding/decoding process may be larger than the set capacity of the buffer memory. Therefore, it is often necessary to repeatedly read specific data from the rewritable non-volatile memory module during the encoding/decoding process, thereby increasing the wear of the rewritable non-volatile memory module and also reducing the encoding/decoding speed. In particular, in an iterative decoding operation, the above-described situation is more significant.

Disclosure of Invention

An exemplary embodiment of the present invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve the efficiency of decoding operation under the condition of limited capacity of a buffer memory.

An exemplary embodiment of the present invention provides a decoding method for a rewritable nonvolatile memory module including a plurality of physical units, the decoding method including: temporarily storing the first data to a buffer memory, wherein the buffer memory comprises a first buffer area and a second buffer area; copying decoded data of the second buffer to the first buffer; performing, in the first buffer, a first type of decoding operation on the first data based on the copied decoded data, wherein the copied decoded data is different from original decoded data corresponding to the first data; and outputting the decoded data if the first type of decoding operation is successful.

In an exemplary embodiment of the present invention, the decoding method further includes: encoding original data to generate the original decoded data corresponding to the first data; storing the raw data to the first entity unit; and storing the original decoded data corresponding to the first data in at least a second one of the physical units.

In an exemplary embodiment of the present invention, the decoding method further includes: reading original data from the first physical unit and reading the original decoded data corresponding to the first data from at least a second physical unit of the physical units; temporarily storing the original data and the original decoding data corresponding to the first data into the buffer memory; and in the first buffer, performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data.

In an exemplary embodiment of the present invention, the decoding method further includes: copying the original decoded data corresponding to the first data to the second buffer before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data.

In an exemplary embodiment of the present invention, the decoding method further includes: performing a second type of decoding operation on corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer, wherein the corrected data is corrected via the first type of decoding operation.

In an exemplary embodiment of the present invention, the first type of decoding operation includes a normal decoding mode and an erasure mode, and the decoding method further includes: and determining to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to the total number of data units with uncorrectable errors in the first data.

In an exemplary embodiment of the present invention, the first type of decoding operation belongs to multi-frame decoding, and the decoding method further includes: and performing single-frame decoding according to the decoding result of the first type of decoding operation to verify the correction of the first type of decoding operation on at least one error bit.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is configured to temporarily store first data in a buffer memory, the buffer memory includes a first buffer area and a second buffer area, the memory control circuit unit is further configured to copy decoded data of the second buffer area to the first buffer area, the memory control circuit unit is further configured to perform a first type of decoding operation on the first data in the first buffer area based on the copied decoded data, the copied decoded data is different from original decoded data corresponding to the first data, and the memory control circuit unit is further configured to output the decoded data if the first type of decoding operation is successful.

In an example embodiment of the present invention, the memory control circuit unit is further configured to encode original data to generate the original decoded data corresponding to the first data, wherein the memory control circuit unit is further configured to store the original data to the first physical unit, wherein the memory control circuit unit is further configured to store the original decoded data corresponding to the first data in at least one second physical unit of the physical units.

In an example embodiment of the present invention, the memory control circuit unit is further configured to instruct reading the original data from the first physical unit and reading the original decoded data corresponding to the first data from at least a second physical unit of the physical units, wherein the memory control circuit unit is further configured to temporarily store the original data and the original decoded data corresponding to the first data into the buffer memory, wherein the memory control circuit unit is further configured to perform the first type of decoding operation on the original data based on the original decoded data corresponding to the first data in the first buffer.

In an example embodiment of the present invention, before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory control circuit unit is further configured to copy the original decoded data corresponding to the first data to the second buffer.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to perform a second type of decoding operation on the corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer, wherein the corrected data is corrected by the first type of decoding operation.

In an exemplary embodiment of the invention, the first type of decoding operation includes a normal decoding mode and an erasure mode, and the memory control circuit unit is further configured to determine to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to a total number of data units having uncorrectable errors in the first data.

In an exemplary embodiment of the invention, the first type of decoding operation belongs to multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation to verify correction of at least one error bit by the first type of decoding operation.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, wherein the memory control circuit unit comprises a host interface, a memory interface, a buffer memory, an error checking and correcting circuit, and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface, the memory interface, the buffer memory and the error checking and correcting circuit, wherein the memory management circuit is configured to temporarily store first data into the buffer memory, wherein the buffer memory includes a first buffer area and a second buffer area, wherein the memory management circuit is further configured to copy decoded data of the second buffer area into the first buffer area, wherein the error checking and correcting circuit is configured to perform a first type of decoding operation on the first data based on the copied decoded data in the first buffer area, wherein the copied decoded data is different from original decoded data corresponding to the first data, and wherein the memory management circuit is further configured to output the decoded data if the first type of decoding operation is successful.

In an exemplary embodiment of the present invention, the error checking and correcting circuit is further configured to encode original data to generate the original decoded data corresponding to the first data, wherein the memory management circuit is further configured to store the original data to the first physical unit, wherein the memory management circuit is further configured to store the original decoded data corresponding to the first data in at least one second physical unit of the physical units.

In an example embodiment of the present invention, the memory management circuit is further configured to instruct reading the original data from the first physical unit and reading the original decoded data corresponding to the first data from at least a second physical unit of the physical units, wherein the memory management circuit is further configured to temporarily store the original data and the original decoded data corresponding to the first data into the buffer memory, wherein the error checking and correcting circuit is further configured to perform the first type of decoding operation on the original data based on the original decoded data corresponding to the first data in the first buffer.

In an example embodiment of the present invention, before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory management circuit is further configured to copy the original decoded data corresponding to the first data to the second buffer.

In an exemplary embodiment of the invention, the corrected data does not include data units having uncorrectable errors.

In an exemplary embodiment of the present invention, the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on the corrected data and the original decoded data corresponding to the first data.

In an exemplary embodiment of the invention, the first type of decoding operation includes a normal decoding mode and an erasure mode, and the memory management circuit is further configured to determine to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to a total number of data units having uncorrectable errors in the first data.

In an exemplary embodiment of the invention, the first data is protected by raid error correction code in the first physical unit.

In an exemplary embodiment of the invention, the first type of decoding operation belongs to multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation to verify correction of at least one erroneous bit by the first type of decoding operation.

Based on the above, the present invention can store the decoded data dynamically generated in the decoding process in the buffer memory. When the first data is to be decoded subsequently, the decoded data can be used immediately without repeating the reading of the relevant data from the rewritable nonvolatile memory module and the calculation. Therefore, the efficiency of the decoding operation can be improved under the condition that the capacity of the buffer memory is limited.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an example embodiment of the present invention.

Fig. 7 is a diagram illustrating multi-frame encoding in accordance with an exemplary embodiment of the present invention.

Fig. 8 to 11 are schematic diagrams illustrating a decoding operation according to an exemplary embodiment of the present invention.

Fig. 12 and 13 are flowcharts illustrating a decoding method according to an exemplary embodiment of the invention.

Description of the reference numerals

10. 30: memory storage device

11. 31: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard with a memory card

201: u disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

601: storage area

602: replacement area

610 (0) to 610 (B), 710 (0) to 710 (E): entity unit

612 (0) to 612 (C): logic unit

701 (1) to 701 (r): position of

830. 831, 832, 833, 1001, 1002: data of

720. 840, 841, 941, 942: decoding data

810. 820: buffer zone

S1201: step (reading original data and original decoding data from rewritable nonvolatile memory module)

S1202: step (temporarily storing original data and original decoding data to a buffer memory)

S1203: step (copying the original decoded data to the second buffer of the buffer memory)

S1204: step (in a first buffer of the buffer memory, a first type of decoding operation is performed on the original data based on the original decoded data)

S1205: step (judging whether the first type decoding operation succeeds)

S1206: step (output decoding decoded data)

S1301: step (reading the first data from the rewritable nonvolatile memory module and temporarily storing the first data in the buffer memory)

S1302: step (copying the decoded data in the second buffer to the first buffer)

S1303: step of (in the first buffer, performing a first type of decoding operation on the first data based on the copied decoded data)

S1304: step (judging whether the first type decoding operation is successful)

S1305: step (output decoded data)

S1306: step (determining whether any data is corrected in a first type of decoding operation)

S1307: step (performing a second type of decoding operation on the corrected data based on the decoded data in the second buffer to update the decoded data)

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be compliant with Parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronics Engineers (IEEE) 1394 standard, high-Speed Peripheral Component connection interface (PCI Express) standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed-II (UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal Flash Storage interface (media Storage, cp interface), CF interface, device interface (Flash interface, integrated Electronics standard, or other integration standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a solid type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line can be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bit groups (bytes, B). However, in other example embodiments, 8, 16 or more or less physical fans may be included in the data bit region, and the size of each physical fan may also be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, an error checking and correcting circuit 508, and a buffer memory 510.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform operations such as data writing, reading and erasing.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 may also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit issues an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data sent from the host system 11 are sent to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequence of instructions may include one or more signals, or data, on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes information such as the identification code and the memory address of the read command.

The ECC circuitry 508 is coupled to the memory management circuitry 502 and is configured to perform ECC operations to ensure data correctness. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. In an example embodiment, the memory control circuit unit 404 further includes a power management circuit 512. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.

Referring to fig. 6, the memory management circuit 502 logically groups the physical units 610 (0) -610 (B) of the rewritable nonvolatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610 (0) -610 (a) in the storage area 601 are used for storing data, and the physical units 610 (a + 1) -610 (B) in the replacement area 602 are used for replacing damaged physical units in the storage area 601. For example, if the data read from a certain physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit. It should be noted that if there are no available physical erase units in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protected (write protect) state, and no more data can be written.

In the present exemplary embodiment, each physical unit refers to a physical programming unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical erase unit, or be composed of a plurality of consecutive or non-consecutive physical addresses. The memory management circuit 502 configures the logic units 612 (0) -612 (C) to map the physical units 610 (0) -610 (a) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. Further, each of logical units 612 (0) -612 (C) may be mapped to one or more physical units.

The memory management circuit 502 records a mapping relationship between logical units and physical units (also referred to as a logical-to-physical address mapping relationship) in at least one logical-to-physical address mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access operations with respect to the memory storage device 10 according to the logical-to-physical address mapping table.

In the exemplary embodiment, the basic unit of the error checking and correcting circuit 508 performing the encoding process is a frame (frame) (also referred to as a decoded frame). A frame includes a plurality of data bits. In the present exemplary embodiment, one frame includes 256 bits. However, in another example embodiment, a frame may include more (e.g., 4K bytes) or less bits.

In the exemplary embodiment, the error checking and correcting circuit 508 can perform single-frame (single-frame) encoding and decoding on data stored in the same physical unit, and can also perform multi-frame (multi-frame) encoding and decoding on data stored in multiple physical units. The single frame coding and the multi-frame coding may respectively use at least one of low density parity check code (LDPC), BCH, convolutional code (convolutional code), turbo code, and other coding algorithms. Alternatively, in an exemplary embodiment, the multi-frame coding may also employ Reed-Solomon codes (RS codes) algorithm. In addition, in another exemplary embodiment, more unlisted coding algorithms may be used, and are not described herein. Depending on the encoding algorithm employed, the error checking and correction circuitry 508 may encode the data to be protected to produce a corresponding error correction code and/or error check code. For convenience of explanation, the error correction code and/or the error check code generated via encoding will be collectively referred to as decoded data (i.e., data for decoding) hereinafter. In an example embodiment, the decoded data generated via encoding is also referred to as parity data.

Referring to fig. 7, taking the example of encoding the data stored in the physical units 710 (0) to 710 (E) to generate the corresponding decoded data 720, at least a portion of the data stored in each of the physical units 710 (0) to 710 (E) may be regarded as a frame. In multi-frame coding, the data in the physical units 710 (0) -710 (E) are encoded according to the position of each bit (or bit group). For example, bit b at position 701 (1) ₁₁ 、b ₂₁ 、…、b _p1 Will be encoded as bit b in decoded data 720 _o1 Bit b at position 701 (2) ₁₂ 、b ₂₂ 、…、b _p2 Will be encoded as bit b in decoded data 720 _o2 (ii) a By analogy, bit b at position 701 (r) _1r 、b _2r 、…、b _pr Will be encoded as bit b in decoded data 720 _or 。

In an exemplary embodiment, the physical units 710 (0) -710 (E) are also referred to as first physical units, and the physical unit for storing the decoded data 720 is referred to as a second physical unit. The number of the first physical units and the number of the second physical units can be more or less. In an exemplary embodiment, the decoded data 720 is generated by encoding specific data (also referred to as original data) in the entity units 710 (0) -710 (E), so that the decoded data 720 can be regarded as original decoded data corresponding to the original data. In an exemplary embodiment, the original data may be considered protected by the decoded data 720 in the physical units 710 (0) -710 (E). In an exemplary embodiment, the decoded data 720 can also be considered as a Redundant Array of Independent Disks (RAID) error correcting code. Based on the decoded data 720, the data read from physical units 710 (0) -710 (E) may be decoded in an attempt to correct errors that may be present in the read data.

In an exemplary embodiment, the data used to generate the decoded data 720 may also include redundant bits corresponding to data bits in the data stored in the physical units 710 (0) -710 (E). Taking the data stored in the physical unit 710 (0) as an example, the redundant bits are generated by encoding the data bits stored in the physical unit 710 (0) in a single frame.

In an exemplary embodiment, when data stored in a physical unit (also referred to as target data) is to be read, decoding of a single frame corresponding to the target data may be performed first. For example, if the target data is single-frame encoded based on the LDPC code, the target data is also single-frame decoded based on the LDPC code. If the decoding of the single frame corresponding to the target data fails, the decoding of the multi-frame corresponding to the target data is performed sequentially, for example, based on the RS code employed in the encoding.

In an exemplary embodiment, single frame decoding and multi-frame decoding may be performed alternately until a decoding failure or a decoding success is determined. Taking fig. 7 as an example, when target data stored in physical unit 710 (0) is to be read, a first single frame decoding corresponding to the target data to be read in physical unit 710 (0) is performed first to attempt to correct errors that may exist. If the first single-frame decoding corresponding to the target data fails, the decoded data 720 and the data used to generate the decoded data 720 in the physical units 710 (1) -710 (E) are read and a first multi-frame decoding corresponding to the target data is performed. If the first multi-frame decoding corresponding to the target data fails, a second single-frame decoding corresponding to the target data may be performed based on the results of the first multi-frame decoding (e.g., some bits of the target data may have been corrected). If the second single frame decoding still fails, a second multi-frame decoding corresponding to the target data may be performed. By analogy, after performing at least one single-frame decoding and/or at least one multi-frame decoding on the target data, errors in the target data should be gradually corrected. If a single-frame or multi-frame decoding of a particular time successfully corrects all errors in the target data, the corresponding iterative decoding may be stopped. Alternatively, if the number of times of single-frame decoding and/or multi-frame decoding performed on the same target data reaches a number threshold, it may be determined that decoding has failed.

In an exemplary embodiment, after completing a multi-frame decoding corresponding to target data (there may still be errors in the target data), at least one single-frame decoding may be performed according to the decoding result of the multi-frame decoding. The single frame decoding verifies that the correction of the at least one erroneous bit in the previous multi-frame decoding is correct. If the decoding result of the single frame decoding reflects that the previous correction for a certain error bit is correct, the correction for the error bit can be preserved. Otherwise, if the decoding result of the single frame decoding reflects that the previous correction for a certain error bit is not correct, the correction for the error bit can be cancelled, so that the bit value of the error bit is returned to its original value.

Fig. 8 to 11 are schematic diagrams illustrating a decoding operation according to an exemplary embodiment of the present invention. Referring to fig. 8, the buffer memory 510 includes

buffers

810 and 820. Buffer 810 is also referred to as a first buffer, and buffer 820 is also referred to as a second buffer. In an exemplary embodiment, the capacity of buffer 810 may be the same or approximately the same as the capacity of buffer 820. In an exemplary embodiment, the capacity of buffer 820 is less than the capacity of buffer 810. In an exemplary embodiment, the

buffers

810 and 820 may be dynamically configured by the memory management unit 502 of FIG. 5.

When it is determined that multi-frame decoding corresponding to the data 831 needs to be performed, the data 830 and the decoded data 840 corresponding to the data 830 are read from the first physical unit and the second physical unit, respectively. Data 830 includes

data

831 and 832. The data 831 is the target data to be decoded and corrected currently based on the decoded data 840, and the data 832 is the rest of the data used to generate the decoded data 840. Taking fig. 7 as an example, if data 831 is data stored in entity unit 710 (0), data 832 may be at least a portion of the data stored in entity units 710 (1) -710 (E).

In an example embodiment, the data 830 may be regarded as original data, and the decoded data 840 may be regarded as original decoded data corresponding to the data 830, the data 831, and/or 832. Data 830 and decoded data 840 are loaded into buffer memory 510. For example, the data 830 and the decoded data 840 are buffered in the buffer 810. It is noted that the decoded data 840 is copied to the buffer 820 as decoded data 841 before decoding the data 830 based on the decoded data 840. After copying the decoded data 840 to the buffer 820, the data 830 may be decoded in the buffer 810 based on the decoded data 840.

In an example embodiment, since the capacity of the buffer memory 510 (or the buffer 810) is not sufficient to store the complete data 830 at once (i.e., the total data amount of the data 830 is larger than the capacity of the buffer memory 510 or the buffer 810), the data 830 may be stored in the buffer 810 in batches and decoded in batches based on the decoded data 840. It is noted that, in an exemplary embodiment, during the batch decoding of the data 830, the data 831 continues to be maintained and/or retained in the buffer 810 until the data 831 is successfully decoded and/or corrected.

In an exemplary embodiment, at least some of the bits of the decoded data 840 may be updated corresponding to the decoding performed in the buffer 810, such that the updated decoded data 840 in the buffer 810 may be different from the pre-stored decoded data 841 in the buffer 820. In an exemplary embodiment, the decoded data 840 is updated to check (syndrome) data corresponding to the decoding performed in the buffer 810. This check data may reflect the decoding status or decoding result of the decoding performed on data 830.

Referring to fig. 9, it is assumed that data 833 in data 830 is corrected, but data 831 is not corrected, according to the decoding performed in buffer 810. In an example embodiment, data 833 is also referred to as corrected data. After correcting the data 833, the data 833 is decoded based on the decoded data 841 in the buffer 820. In decoding data 833 based on decoded data 841, at least some of the bits in decoded data 841 may also be updated. The updated decoded data 841 is continuously stored in the buffer 820. It should be noted that, in an exemplary embodiment, the decoded data 841 in the buffer 820 is only used for the corrected data (i.e., the data 833) in the decoded data 830, and is not used for the data that has not been corrected in the decoded data 830. Furthermore, updated decoded data 841 may also be referred to as check data corresponding to data 833 to reflect the decoding status or decoding result of decoding performed on data 833.

In an exemplary embodiment, the correction of data 833 based on decoded data 840 is still verified by decoding a single frame corresponding to data 833. For example, in the example embodiment of fig. 9, after data 833 is corrected based on decoded data 840, single frame decoding corresponding to data 833 is performed. If the decoding result of the single frame decoding reflects that the correction for the erroneous bits in the data 833 is correct, the correction result of the data 833 can be retained. Conversely, if the decoding result of the single frame decoding reflects that the correction for the erroneous bits in the data 833 is not correct, the correction result of the data 833 can be cancelled, so that some of the corrected bits in the data 833 are restored to their original bit values.

In an exemplary embodiment, the decoding operations of fig. 8 and 9 may be considered as a first multi-frame decoding of the data 831. This first multi-frame decoding is performed to correct errors in the data 831. For example, the data 831 may be data that is instructed to be read by a certain read command from the host system. If the errors in the data 831 are not completely corrected, the first multi-frame decoding is determined to have failed.

Referring to fig. 10, if the first multi-frame decoding on the data 831 fails, the data 1001 can be read out from the first physical unit again. It should be noted that, continuing with the example embodiments of FIGS. 8 and 9, data 831 may be continuously stored in buffer 810 without being re-read from the first physical unit with data 1001. In an example embodiment, the data 1001 is also referred to as first data. Data 1001 may not contain data 833 that has been corrected in the example embodiment of fig. 9. Data 1001 is loaded into buffer 510, e.g., buffered in buffer 810.

Before decoding the

data

831 and 1001, the decoded data 941 is copied from the buffer 820 to the buffer 810 as decoded data 942. It should be noted that the decoded data 941 is used to represent the updated decoded data 841 in the buffer 820 of fig. 9. In other words, the data content of the decoded data 941 is identical to the updated decoded data 841 in the buffer 820 of FIG. 9. After copying the decoded data 941 from the buffer 820 to the buffer 810, the

data

831 and 1001 are decoded in the buffer 810 based on the decoded data 942.

It is noted that, in the example embodiment of fig. 10, the decoded data 942 for the decoded

data

831 and 1001 is copied from the buffer 820, rather than being read from the second physical unit. Therefore, the decoded data 942 of fig. 10 for the decoded

data

831 and 1001 is different from the decoded data 840 of fig. 8 and 9. In an exemplary embodiment, the decoded data 840 of fig. 8 and 9 can also be considered as the original decoded data corresponding to the data 1001. Furthermore, since the capacity of the buffer memory 510 or the buffer 810 is not enough to store the complete data 1001 at a time (i.e. the total data amount of the data 1001 is larger than the capacity of the buffer memory 510 or the buffer 810), the data 1001 may be stored into the buffer 810 in batches and decoded in batches based on the decoded data 942. Furthermore, data 1001 decoded by batch buffer 810 does not overwrite data 831.

Referring to fig. 11, it is assumed that the data 1002 is corrected, but the data 831 is not corrected according to the decoding performed in the buffer 810 in fig. 10. In an example embodiment, the data 1002 is also referred to as corrected data. In an exemplary embodiment, the correction to the data 1002 is also verified by decoding a single frame corresponding to the data 1002 to determine the correctness of the correction to the data 1002. After the data 1002 is corrected, the data 1002 is decoded based on the decoded data 941 in the buffer 820. In decoding the data 1002 based on the decoded data 941, at least some bits of the decoded data 941 may also be updated. The updated decoded data 941 is kept in the buffer 820 for the next iterative decoding corresponding to the data 831.

Similar to the example embodiment of FIG. 9, in the example embodiment of FIG. 11, the decoded data 941 in the buffer 820 is only used to decode corrected data (i.e., the data 1002) but not used to decode uncorrected data (e.g., the data 831 or the uncorrected data in the data 1001 of FIG. 10). The updated decoded data 941 may also be referred to as check data corresponding to the data 1002 to reflect a decoding state or a decoding result of decoding performed on the data 1002. This may be considered to complete the second multi-frame decoding of the data 831. This second multi-frame decoding is also performed to correct errors in the data 831. In the exemplary embodiment of fig. 11, if the error in the data 831 is not completely corrected, the second multi-frame decoding is also determined to have failed.

If the second multi-frame decoding still fails, the operations of reading the first data not including the target data and the updated data, copying the decoded data from the second buffer to the first buffer, performing the decoding and data correction operations in the first buffer, performing the decoding on the corrected data based on the decoded data in the second buffer, and updating the decoded data in the second buffer in the exemplary embodiments of fig. 10 and 11 may be repeatedly performed until the errors in the target data stored in the first buffer are successfully corrected. In addition, the decoding operations of FIGS. 8-11 can be performed by the memory management circuit 502 of FIG. 5 in conjunction with the error checking and correcting circuit 508.

In an example embodiment, decoding performed based on the decoded data copied into the first buffer (e.g., the decoded data 840 of fig. 8 and the decoded data 942 of fig. 10) is also referred to as a first type of decoding operation, and decoding performed based on the decoded data stored in the second buffer (e.g., the decoded data 841 of fig. 9 and the decoded data 941 of fig. 11) is also referred to as a second type of decoding operation.

In an example embodiment, the data (e.g., the original data and/or the first data) decoded by the first type of decoding operation may include data units having uncorrectable (abbreviated as UNC) errors, while the data (e.g., the corrected data) decoded by the second type of decoding operation may not include data units having UNC errors. Here, the UNC error refers to an error that cannot be corrected by decoding a corresponding single frame. Taking fig. 7 as an example, assuming that a data unit is a frame, if a data unit stored in the physical unit 710 (0) cannot successfully correct an error therein by decoding a single frame corresponding to the data unit, the data unit can be regarded as a data unit with a UNC error. Alternatively, if a data unit stored in entity unit 710 (1) can successfully correct errors therein by decoding a single frame corresponding to the data unit, the data unit can be regarded as a data unit without UNC errors.

In an exemplary embodiment, the first type of decoding operation includes a normal decoding mode and an erasure (erasure) mode. The first type of decoding operation can be determined to operate in a normal decoding mode or an erasure mode according to the total number of data units with UNC errors in the data to be decoded (e.g., the data 830 in fig. 8 or the

data

831 and 1001 in fig. 10). In an exemplary embodiment, if the total number of data units having UNC errors in the data to be decoded is greater than or equal to a predetermined value, such as 2, but not limited thereto, the first type of decoding operation performed on the data to be decoded is operated in the normal decoding mode. If the total number of data units with UNC errors in the data to be decoded is less than a predetermined value, the first type of decoding operation performed on the data to be decoded is operated in an erasure mode. In the erasure mode, the first type of decoding operation can generally ensure that the decoding and correction of the data to be decoded (or the target data) are completed.

In the example embodiments of fig. 9 or 11, the data to be decoded in the buffer 810 may include at least one data unit having a UNC error. A data unit in the buffer 810 with a UNC error may be corrected to a data unit without a UNC error corresponding to a first type of decoding operation performed on the data to be decoded. The data unit without the UNC error can be considered as corrected data. In the multiple iterative decoding performed consecutively, the first data read from the first physical unit and loaded into the buffer 810 at a time may not include a data unit that has not had a UNC error. Therefore, in the multiple iterative decoding which is continuously executed, the number of data units with UNC errors in the data to be decoded can be gradually reduced, thereby improving the decoding success rate.

It should be noted that, in the foregoing exemplary embodiments of fig. 8 to 11, only when the first type decoding operation is performed on the original data for the first time, the original decoded data corresponding to the first data (or the original data) is read from the second physical unit. In a second, later, decoding operation of the first type, decoded data used to decode the first data is copied from the second buffer. In addition, in the (decoding) operation of updating the decoded data stored in the second buffer, the updating of the decoded data in the second buffer is only affected by the data units without the UNC error, thereby reducing the probability that the decoded data in the second buffer is affected by the error bits (or UNC errors). Therefore, after copying the decoded data from the second buffer to the first buffer, the decoding success rate of the first type of decoding operation performed on the first buffer based on the copied decoded data can be improved.

Fig. 12 and 13 are flowcharts illustrating a decoding operation according to an exemplary embodiment of the present invention. Referring to fig. 12, in step S1201, original data and original decoded data corresponding to the first data (or the original data) are read from the rewritable nonvolatile memory module. In step S1202, the original data and the original decoded data corresponding to the first data are temporarily stored in a first buffer (e.g., the buffer 810 in fig. 8) of a buffer memory (e.g., the buffer 510 in fig. 8). In step S1203, the original decoded data corresponding to the first data is copied to a second buffer (e.g., buffer 820 in fig. 8) of the buffer memory. In step S1204, in a first buffer area of the buffer memory, a first type of decoding operation is performed on original data based on original decoded data corresponding to the first data. In step S1205, it is determined whether the first type of decoding operation corresponding to the original data is successful. If so (i.e., the first type of decoding operation is successful), in step S1206, the successfully decoded data (also referred to as decoded data) is output. If not (i.e., the first type decoding operation fails), the process proceeds to step S1301 in fig. 13.

Referring to fig. 13, in step S1301, first data is read from the rewritable nonvolatile memory module and temporarily stored in a first buffer area of the buffer memory. It should be noted that the first data may not include the target data that is continuously stored in the first buffer and the corrected data that has been corrected in the previous decoding operation of the first type. In step S1302, the decoded data in the second buffer is copied into the first buffer. In step S1303, in the first buffer, a first type of decoding operation is performed on the first data and the target data based on the copied decoded data. In step S1304, it is determined whether the first type decoding operation is successful. If yes, in step S1305, the decoded data is output. If not, in step S1306, it is determined whether there is data (or data unit) to be corrected in the first type decoding operation. If not (i.e., no data (or data unit) is corrected in the first decoding operation), go back to step S1301, and re-perform the next iterative decoding. If there is data (or data unit) to be corrected in the first type of decoding operation, in step S1307, a second type of decoding operation is performed on the corrected data (i.e., corrected data) based on the decoded data in the second buffer area to update the decoded data in the second buffer area. The decoded data updated based on the corrected data may be continuously saved in the second buffer for the next iterative decoding. After step S1307, step S1301 may be repeatedly performed. In addition, in the example embodiments of fig. 12 and 13, if a number of times of execution of the decoding operation performed reaches a number threshold, the decoding operation may be determined to have failed and stopped.

In an exemplary embodiment, steps S1206 and/or S1305 may further include copying the successfully decoded data (e.g., the target data) to other physical units for storing, and marking the physical erase unit in which the data (e.g., the target data) is originally stored as a damaged physical erase unit. In addition, more error handling means may also be executed in step S1206 and/or S1305, and the invention is not limited thereto.

However, the steps in fig. 12 and fig. 13 have been described in detail above, and are not repeated herein. It is noted that the steps in fig. 12 and fig. 13 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 12 and fig. 13 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

In summary, the present invention can continuously store the decoded data dynamically generated during the decoding process in the buffer memory. When the target data is to be decoded repeatedly subsequently, the decoded data stored in the buffer memory can be used immediately without repeatedly reading the relevant data from the rewritable nonvolatile memory module and repeatedly calculating. In addition, the invention can also reduce the influence of UNC errors on the decoded data stored in the buffer memory. Therefore, the efficiency of the decoding operation can be improved under the condition that the capacity of the buffer memory is limited.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A decoding method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical units, the decoding method comprising:

temporarily storing first data to a first buffer area in a buffer memory, wherein the buffer memory comprises the first buffer area and a second buffer area;

copying the decoded data of the second buffer to the first buffer to decode the first data;

performing, in the first buffer, a first type of decoding operation on the first data based on the copied decoded data, wherein the first type of decoding operation includes at least one decoding operation performed in the first buffer; and

and outputting the decoded data if the first type of decoding operation is successful.

2. The decoding method of claim 1, further comprising:

encoding original data to generate original decoded data corresponding to the first data;

storing the original data to at least one first entity unit; and

storing the original decoded data corresponding to the first data in at least a second physical unit of the plurality of physical units.

3. The decoding method of claim 1, further comprising:

reading original data from at least one first entity unit and original decoded data corresponding to the first data from at least one second entity unit of the plurality of entity units;

loading the original data and the original decoded data corresponding to the first data into the buffer memory; and

performing, in the first buffer, the first type of decoding operation on the original data based on the original decoded data corresponding to the first data.

4. The decoding method of claim 3, further comprising:

copying the original decoded data corresponding to the first data to the second buffer before performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data.

5. The decoding method of claim 1, further comprising:

performing a second type of decoding operation on the corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer,

wherein the corrected data is corrected via the first type of decoding operation.

6. The decoding method according to claim 5, wherein the corrected data does not include data units having uncorrectable errors.

7. The decoding method according to claim 1, wherein the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on the corrected data and original decoded data corresponding to the first data.

8. The decoding method of claim 1, wherein the first class of decoding operations comprises a normal decoding mode and an erasure mode, and the decoding method further comprises:

and determining to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to the total number of data units with uncorrectable errors in the first data.

9. The decoding method according to claim 1, wherein the first data is protected by RAID ECC in at least a first physical unit.

10. The decoding method of claim 1, wherein the first type of decoding operation belongs to multi-frame decoding, and the decoding method further comprises:

and performing single-frame decoding according to the decoding result of the first type of decoding operation to verify the correction of the first type of decoding operation on at least one error bit.

11. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of entity units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for temporarily storing the first data into a first buffer area in a buffer memory, wherein the buffer memory comprises the first buffer area and a second buffer area,

wherein the memory control circuit unit is further to copy decoded data of the second buffer to the first buffer to decode the first data,

wherein the memory control circuitry unit is further to perform a first type of decoding operation on the first data in the first buffer based on the copied decoded data, wherein the first type of decoding operation includes at least one decoding operation performed in the first buffer,

wherein the memory control circuit unit is further configured to output decoded data if the first type of decoding operation is successful.

12. The memory storage device of claim 11, wherein the memory control circuitry unit is further to encode original data to produce original decoded data corresponding to the first data,

wherein the memory control circuit unit is further configured to store the raw data to at least a first physical unit,

wherein the memory control circuitry unit is further to store the original decoded data corresponding to the first data in at least a second physical unit of the plurality of physical units.

13. The memory storage device of claim 11, wherein the memory control circuitry unit is further to instruct reading original data from at least a first physical unit and reading original decoded data corresponding to the first data from at least a second physical unit of the plurality of physical units,

wherein the memory control circuit unit is further configured to load the original data and the original decoded data corresponding to the first data into the buffer memory,

wherein the memory control circuitry unit is further to perform the first type of decoding operation on the original data in the first buffer based on the original decoded data corresponding to the first data.

14. The memory storage device of claim 13, wherein prior to performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory control circuitry unit is also to copy the original decoded data corresponding to the first data to the second buffer.

15. The memory storage device of claim 11, wherein the memory control circuitry unit is further to perform a second type of decoding operation on corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer,

16. The memory storage device of claim 15, wherein the corrected data does not include data units having uncorrectable errors.

17. The memory storage device of claim 11, wherein the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on corrected data and original decoded data corresponding to the first data.

18. The memory storage device of claim 11, wherein the first type of decoding operation comprises a normal decoding mode and an erasure mode, and the memory control circuit unit is further configured to determine to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to a total number of data units in the first data having uncorrectable errors.

19. The memory storage device of claim 11, wherein the first data is protected in at least a first physical unit by redundant array of independent disks error correction code.

20. The memory storage device of claim 11, wherein the first type of decoding operation is multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation to verify correction of at least one erroneous bit by the first type of decoding operation.

21. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity units, wherein the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

a buffer memory;

an error checking and correcting circuit; and

memory management circuitry connected to the host interface, the memory interface, the buffer memory, and the error checking and correction circuitry,

wherein the memory management circuit is used for temporarily storing the first data to a first buffer area in the buffer memory, wherein the buffer memory comprises the first buffer area and a second buffer area,

wherein the memory management circuitry is further to copy decoded data of the second buffer to the first buffer to decode the first data,

wherein the error checking and correcting circuit is configured to perform a first type of decoding operation on the first data based on the copied decoded data in the first buffer, wherein the first type of decoding operation comprises at least one decoding operation performed in the first buffer,

wherein the memory management circuit is further configured to output decoded data if the first type of decoding operation is successful.

22. The memory control circuitry unit of claim 21, wherein the error checking and correction circuitry is further to encode raw data to produce raw decoded data corresponding to the first data,

wherein the memory management circuit is further configured to store the raw data to at least a first physical unit,

wherein the memory management circuitry is also to store the original decoded data corresponding to the first data in at least a second physical unit of the plurality of physical units.

23. The memory control circuit unit of claim 21, wherein the memory management circuit is further configured to instruct reading original data from at least a first physical unit and reading original decoded data corresponding to the first data from at least a second physical unit of the plurality of physical units,

wherein the memory management circuit is further to load the original data and the original decoded data corresponding to the first data into the buffer memory,

wherein the error checking and correcting circuit is further configured to perform the first type of decoding operation on the original data in the first buffer based on the original decoded data corresponding to the first data.

24. The memory control circuitry unit of claim 23, wherein prior to performing the first type of decoding operation on the original data based on the original decoded data corresponding to the first data, the memory management circuitry is further to copy the original decoded data corresponding to the first data to the second buffer.

25. The memory control circuit unit of claim 21, wherein the memory control circuit unit is further configured to perform a second type of decoding operation on corrected data based on the decoded data in the second buffer to update the decoded data in the second buffer,

26. The memory control circuit unit of claim 25, wherein the corrected data does not include data cells with uncorrectable errors.

27. The memory control circuit unit of claim 21, wherein the decoded data copied to the first buffer is generated based on a second type of decoding operation performed on corrected data and original decoded data corresponding to the first data.

28. The memory control circuit unit of claim 21, wherein the first type of decoding operation comprises a normal decoding mode and an erasure mode, and the memory management circuit is further configured to determine to operate the first type of decoding operation in the normal decoding mode or the erasure mode according to a total number of data units in the first data having uncorrectable errors.

29. The memory control circuit unit of claim 21, wherein the first data is protected by redundant array of independent disks error correction code in at least a first physical unit.

30. The memory control circuit unit of claim 21, wherein the first type of decoding operation is multi-frame decoding, and the memory control circuit unit is further configured to perform single-frame decoding according to a decoding result of the first type of decoding operation to verify the correction of at least one erroneous bit by the first type of decoding operation.