CN109492239B - Device for realizing real-time segmentation of simulation waveform data - Google Patents
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Abstract
The invention provides a device for realizing real-time segmentation of simulation waveform data, which comprises: the hardware side module generates simulation waveform data, sets period information, packs the data, and sends the packed simulation waveform data to the simulation waveform data segmentation module; the waveform segmentation requirement information transmission module receives waveform segmentation condition information set by a user TestStandard and sends the waveform segmentation condition information to the simulation waveform data segmentation module; the simulation waveform data segmentation module receives the simulation waveform data and waveform segmentation condition information, segments the simulation waveform data according to the waveform segmentation condition information, and sends the data generated by segmentation to the simulation waveform data writing file module; the simulation waveform data writing file module receives the segmentation data and writes the segmentation data into the waveform file. The invention supports online real-time segmentation of simulation waveforms when simulation is executed, is convenient for a user to selectively check waveforms, and avoids the problem of low loading efficiency of oversized waveform data.
Description
Technical Field
The invention relates to the technical field of FPGA prototype verification, in particular to a device for realizing real-time segmentation of simulation waveform data.
Background
In the design of digital integrated circuits, after a design engineer completes the design in HDL (Hardware Description Language ), it is necessary to verify whether the design satisfies the intended function through Simulation (Simulation). Typically, a designer sends test stimulus to a DUT (Device Under Test, user design under test) through a test file TestBench (TestBench) running on an HDL simulator and responds to the output information, and determines from the responding output information whether the DUT satisfies the intended function. With the continuous improvement of the design complexity of the DUT and the high occurrence rate of design anomalies, the design engineer cannot judge whether the design of the DUT meets the requirements or whether the cause of anomalies occurs in high-efficiency positioning through the responsive output information, the design engineer needs to sample the signals in the DUT in real time, and confirm anomalies by observing the simulation waveforms, when the design complexity of the DUT is continuously improved, the simulation waveform data is also continuously increased, which brings great inconvenience to the design engineer, the design engineer cannot quickly check the waveform data at a certain stage, and meanwhile, the extra-large waveform data wastes time when the tool for watching waveforms is used for loading, so that the work efficiency of the design engineer is greatly reduced.
Disclosure of Invention
In view of the above problems, an object of an embodiment of the present invention is to provide a device for implementing real-time segmentation of simulation waveform data, so as to solve the problem that when the design complexity of a DUT is continuously improved, the simulation waveform data is continuously increased, which brings great inconvenience to design engineers.
In order to solve the above problems, an embodiment of the present invention discloses a device for implementing real-time segmentation of simulation waveform data, including: a hardware side module, a waveform segmentation requirement information transfer module, a simulation waveform data segmentation module and a simulation waveform data writing file module, wherein,
the hardware side module is used for generating simulation waveform data, performing period information setting and data packaging, and sending the packaged simulation waveform data to the simulation waveform data segmentation module;
the waveform segmentation requirement information transfer module is used for receiving waveform segmentation condition information set by a user TestBench and sending the waveform segmentation condition information to the simulation waveform data segmentation module;
the simulation waveform data segmentation module is used for receiving the simulation waveform data sent by the hardware side module and the waveform segmentation condition information sent by the waveform segmentation requirement information transfer module, segmenting the simulation waveform data according to the waveform segmentation condition information, and sending the data generated by segmentation to the simulation waveform data writing file module;
the simulation waveform data writing file module is used for receiving the segmentation data generated by the simulation waveform data segmentation module and writing the segmentation data into a waveform file.
Optionally, the hardware side module includes: sample module, pack module, wherein,
the sample module is connected with the pack module and is used for sampling the designated signals according to the design of the DUT of a user and sending the sampled simulation waveform data to the pack module;
the pack module is connected with the simulation waveform data segmentation module, and is used for receiving the sampled simulation waveform data sent by the sample module, adding periodic header information in a preset format to the received simulation waveform data, packaging the periodic header information, and sending the packaged simulation waveform data to the simulation waveform data segmentation module.
Optionally, the waveform division condition information includes a waveform division condition including: one of dividing according to file size, dividing according to number of cycles, dividing according to signal types, dividing according to module names.
Optionally, the simulation waveform data segmentation module includes: a data verification module, a segmentation condition information analysis module and a data segmentation module, wherein,
the data verification module is respectively connected with the pack module and the data segmentation module of the hardware side module, and is used for receiving the simulation waveform data sent by the pack module, verifying whether the cycle head information of the simulation waveform data meets a preset format and verifying whether the load information of the simulation waveform data is complete, and sending the verified simulation waveform data to the data segmentation module;
the segmentation condition information analysis module is respectively connected with the waveform segmentation requirement information transmission module and the data segmentation module, and is used for analyzing the waveform segmentation condition information sent by the waveform segmentation requirement information transmission module and sending the waveform segmentation condition information to the data segmentation module;
the data segmentation module is respectively connected with the data verification module, the segmentation condition information analysis module and the simulated waveform data writing file module, and is used for receiving the verified simulated waveform data sent by the data verification module and the waveform segmentation condition information sent by the segmentation condition information analysis module, segmenting the verified simulated waveform data received by the data verification module according to the waveform segmentation condition information received by the segmentation condition information analysis module, and sending the segmented data to the simulated waveform data writing file module.
Optionally, the predetermined format includes Zhou Qitou identification, data type, payload data length, and includes one or more of number of cycles, signal type, module name, the length of the predetermined format includes 128bit, 256bit, or other 128bit integer multiple length, wherein,
the Zhou Qitou identified location represents a start location of one cycle of data;
the data type represents the type of the load data;
the number of cycles represents a current number of cycles;
the payload data length represents an effective length of the payload data.
The embodiment of the invention has the following advantages:
1. the invention supports online real-time segmentation of simulation waveforms when simulation is executed, and is convenient for users (such as design engineers) to selectively check waveforms at a certain stage;
2. the invention can avoid the problem of low efficiency of loading and checking waveforms caused by overlarge simulation waveform data generated by high complexity of the DUT;
3. the invention supports a plurality of different simulation waveform segmentation conditions, for example, can support: dividing according to file size, dividing according to cycle number, dividing according to signal variety, dividing according to module name, etc.;
4. the invention has the advantages of simple design, high use flexibility and low maintenance cost, supports a plurality of software development languages, and has strong portability.
Drawings
FIG. 1 is a block diagram of an embodiment of an apparatus for implementing real-time segmentation of simulated waveform data in accordance with the present invention;
fig. 2 is a schematic diagram of a predetermined format in an embodiment of an apparatus for implementing real-time segmentation of simulated waveform data according to the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, a block diagram of an embodiment of an apparatus for implementing real-time segmentation of simulated waveform data according to the present invention may specifically include the following modules: the device comprises a hardware side module, a waveform segmentation requirement information transmission module, a simulation waveform data segmentation module and a simulation waveform data writing file module, wherein the hardware side module is used for generating simulation waveform data, performing period information setting and data packaging, and sending the packaged simulation waveform data to the simulation waveform data segmentation module; the waveform segmentation requirement information transfer module is used for receiving waveform segmentation condition information set by a user TestBench and sending the waveform segmentation condition information to the simulation waveform data segmentation module; the simulation waveform data segmentation module is used for receiving the simulation waveform data sent by the hardware side module and the waveform segmentation condition information sent by the waveform segmentation requirement information transmission module, segmenting the simulation waveform data according to the waveform segmentation condition information, and sending the data generated by segmentation to the simulation waveform data writing file module; the simulation waveform data writing file module is used for receiving the segmentation data generated by the simulation waveform data segmentation module and writing the segmentation data into the waveform file.
Alternatively, the hardware-side module may include: the system comprises a sample module and a pack module, wherein the sample module is connected with the pack module, and is used for sampling a designated signal according to the design of a user DUT and sending sampled simulation waveform data to the pack module; the pack module is connected with the simulation waveform data segmentation module and is used for receiving the sampled simulation waveform data sent by the sample module, adding periodic header information in a preset format to the received simulation waveform data, packaging the periodic header information, and sending the packaged simulation waveform data to the simulation waveform data segmentation module.
Alternatively, the predetermined format may include a format that any user wants to set, for example, the predetermined format may include a cycle header identification, a data type, a payload data length, and one or more of a cycle number, a signal type, and a module name. Alternatively, the length of the predetermined format may include 128 bits, 256 bits, or other integer multiple lengths of 128 bits, where the position of the cycle header flag indicates the start position of one cycle data; the data type indicates a type of the load data, for example, the data type may be waveform data or other data other than waveform data; the number of cycles represents the current number of cycles; the payload data length represents the effective length of the payload data.
Specifically, in one embodiment of the present invention, the information in the predetermined format with the length of 128 bits is shown in fig. 2, where 127:40flag represents a period header identifier and represents a start position of one period data; 39:34type represents a data type, which may be waveform data or other data other than waveform data; 33:10cycle represents the current number of cycles; 9:0length represents the effective length of the load data.
Alternatively, the waveform division condition information may include a waveform division condition, and the waveform division condition may include: one of dividing by file size, dividing by number of cycles, dividing by signal type, dividing by module name, etc.
Alternatively, the simulation waveform data dividing module may include: the device comprises a data verification module, a segmentation condition information analysis module and a data segmentation module, wherein the data verification module is respectively connected with a pack module and the data segmentation module of the hardware side module, and is used for receiving simulation waveform data sent by the pack module, verifying whether periodic header information of the simulation waveform data meets a preset format and verifying whether load information of the simulation waveform data is complete or not, and sending the verified simulation waveform data to the data segmentation module; the segmentation condition information analysis module is respectively connected with the waveform segmentation requirement information transmission module and the data segmentation module, and is used for analyzing the waveform segmentation condition information sent by the waveform segmentation requirement information transmission module and sending the waveform segmentation condition information to the data segmentation module; the data segmentation module is respectively connected with the data verification module, the segmentation condition information analysis module and the simulation waveform data writing file module, and is used for receiving the verified simulation waveform data sent by the data verification module and the waveform segmentation condition information sent by the segmentation condition information analysis module, segmenting the verified simulation waveform data received by the data verification module according to the waveform segmentation condition information received by the segmentation condition information analysis module, and sending the data generated by segmentation to the simulation waveform data writing file module. The simulation waveform data writing file module is used for receiving data generated by the segmentation of the data segmentation module in the simulation waveform data segmentation module and writing the segmented data into the waveform file.
The embodiment of the invention has the following advantages:
1. the invention supports online real-time segmentation of simulation waveforms when simulation is executed, and is convenient for users (such as design engineers) to selectively check waveforms at a certain stage;
2. the invention can avoid the problem of low efficiency of loading and checking waveforms caused by overlarge simulation waveform data generated by high complexity of the DUT;
3. the invention supports a plurality of different simulation waveform segmentation conditions, for example, can support: dividing according to file size, dividing according to cycle number, dividing according to signal variety, dividing according to module name, etc.;
4. the invention has the advantages of simple design, high use flexibility and low maintenance cost, supports a plurality of software development languages, and has strong portability.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above describes in detail a device for implementing real-time segmentation of simulation waveform data, and specific examples are applied to illustrate the principle and implementation of the present invention, and the above description of the examples is only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (3)
1. An apparatus for implementing real-time segmentation of simulated waveform data, comprising: a hardware side module, a waveform segmentation requirement information transfer module, a simulation waveform data segmentation module and a simulation waveform data writing file module, wherein,
the hardware side module is used for generating simulation waveform data, performing period information setting and data packaging, and sending the packaged simulation waveform data to the simulation waveform data segmentation module;
the waveform segmentation requirement information transfer module is used for receiving waveform segmentation condition information set by a user TestBench and sending the waveform segmentation condition information to the simulation waveform data segmentation module;
the simulation waveform data segmentation module is used for receiving the simulation waveform data sent by the hardware side module and the waveform segmentation condition information sent by the waveform segmentation requirement information transfer module, segmenting the simulation waveform data according to the waveform segmentation condition information, and sending the data generated by segmentation to the simulation waveform data writing file module;
the simulation waveform data writing-in file module is used for receiving the segmentation data generated by the simulation waveform data segmentation module and writing the segmentation data into a waveform file;
the hardware-side module includes: sample module, pack module, wherein,
the sample module is connected with the pack module and is used for sampling the designated signals according to the design of the DUT of a user and sending the sampled simulation waveform data to the pack module;
the pack module is connected with the simulation waveform data segmentation module, and is used for receiving the sampled simulation waveform data sent by the sample module, adding periodic header information in a preset format to the received simulation waveform data, packaging the periodic header information, and sending the packaged simulation waveform data to the simulation waveform data segmentation module;
the simulation waveform data segmentation module comprises: a data verification module, a segmentation condition information analysis module and a data segmentation module, wherein,
the data verification module is respectively connected with the pack module and the data segmentation module of the hardware side module, and is used for receiving the simulation waveform data sent by the pack module, verifying whether the cycle head information of the simulation waveform data meets a preset format and verifying whether the load information of the simulation waveform data is complete, and sending the verified simulation waveform data to the data segmentation module;
the segmentation condition information analysis module is respectively connected with the waveform segmentation requirement information transmission module and the data segmentation module, and is used for analyzing the waveform segmentation condition information sent by the waveform segmentation requirement information transmission module and sending the waveform segmentation condition information to the data segmentation module;
the data segmentation module is respectively connected with the data verification module, the segmentation condition information analysis module and the simulated waveform data writing file module, and is used for receiving the verified simulated waveform data sent by the data verification module and the waveform segmentation condition information sent by the segmentation condition information analysis module, segmenting the verified simulated waveform data received by the data verification module according to the waveform segmentation condition information received by the segmentation condition information analysis module, and sending the segmented data to the simulated waveform data writing file module.
2. The apparatus of claim 1, wherein the waveform segmentation condition information comprises a waveform segmentation condition, the waveform segmentation condition comprising: one of dividing according to file size, dividing according to number of cycles, dividing according to signal types, dividing according to module names.
3. The apparatus of claim 1, wherein the predetermined format comprises one or more of Zhou Qitou identification, data type, payload data length, and number of cycles, signal type, module name, and wherein the length of the predetermined format comprises 128 bits, 256 bits, or an integer multiple of other 128 bits, wherein,
the Zhou Qitou identified location represents a start location of one cycle of data;
the data type represents the type of the load data;
the number of cycles represents a current number of cycles;
the payload data length represents an effective length of the payload data.
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| CN114003456A (en) * | 2021-09-26 | 2022-02-01 | 芯华章科技股份有限公司 | Waveform data display method, device and storage medium |
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