CN114003456A - Waveform data display method, device and storage medium - Google Patents
Waveform data display method, device and storage medium Download PDFInfo
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- CN114003456A CN114003456A CN202111132687.0A CN202111132687A CN114003456A CN 114003456 A CN114003456 A CN 114003456A CN 202111132687 A CN202111132687 A CN 202111132687A CN 114003456 A CN114003456 A CN 114003456A
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The present disclosure provides a method, an apparatus, and a storage medium for displaying waveform data, the method including: receiving a first instruction for reading specified waveform data, wherein the specified waveform data comprises a plurality of subdata; reading first subdata in the plurality of subdata; processing the first subdata; and reading second sub-data of the plurality of sub-data during processing of the first sub-data, wherein processing of the first sub-data includes generating a first waveform based on the first sub-data and displaying the first waveform via an image interface. According to the method and the device, waveform data do not need to be loaded to the memory completely, occupation of the memory is reduced, display of the waveform data is guaranteed to be carried out timely, blocking in the debugging process and reduction of the response speed of a system are avoided, and therefore debugging efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of data processing technologies, and in particular, to a method and an apparatus for displaying waveform data, and a storage medium.
Background
In the verification process of the chip, hardware simulation (emulation) is performed on the chip design, and then corresponding simulation data is generated, and then debugging (debug) is performed to determine the specific module and the reason of the fault in the chip design. During debugging, simulation data generated in the simulation stage is reloaded, so that a worker can conveniently debug the chip design. However, the scale of chip design is increasing continuously, and the data amount of the simulation data generated in the simulation phase is also increasing correspondingly, so that when the simulation data is loaded into the debugging tool from the storage device in the debugging phase, the debugging process is stuck, the system response speed is reduced, and the efficiency of debugging work is reduced. The above-described problems also exist in software simulation (simulation).
Disclosure of Invention
In view of the above, the present disclosure is directed to a method, an apparatus and a storage medium for displaying waveform data.
In a first aspect, the present disclosure provides a method for displaying waveform data, including:
receiving a first instruction for reading specified waveform data, wherein the specified waveform data comprises a plurality of subdata;
reading first subdata in the plurality of subdata;
processing the first subdata; and
reading second sub-data of the plurality of sub-data during processing of the first sub-data, wherein processing of the first sub-data includes generating a first waveform based on the first sub-data and displaying the first waveform via an image interface.
Optionally, the method further comprises: determining the number of the first sub data based on the maximum number of the waveforms displayed by the image interface.
Optionally, the data amount of each sub data is determined based on a preset time length.
Optionally, the preset time length is greater than or equal to a minimum time length, where the minimum time length is a time length corresponding to a minimum data size required for generating a waveform.
Optionally, the first sub data includes first signal data and second signal data, and the method further includes:
reading the first signal data and the second signal data;
comparing the first signal data and the second signal data; and
and reading third signal data and fourth signal data to be compared in the second sub data during the comparison.
Optionally, the method further comprises: reading the plurality of sub data based on the priority of the sub data.
Optionally, the method further comprises:
reading a description of a logic system design, the logic system design comprising a plurality of modules; and
determining a target module associated with the first child data among the plurality of modules, wherein,
the second subdata is subdata corresponding to at least one signal of the target module.
Optionally, the method further comprises:
reading a description of a logic system design, the logic system design comprising a plurality of signals; and
receiving a second instruction for reading the specified signal;
determining at least one associated signal associated with the designated signal among the plurality of signals according to the description of the logic system design;
and preferentially reading the sub data corresponding to the at least one associated signal.
In a second aspect, the present disclosure proposes an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to any one of the first aspect when executing the program.
In a third aspect, the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method of the first aspect.
As can be seen from the foregoing, according to the waveform data display method, device, and storage medium provided by the present disclosure, when the loaded waveform data is displayed, the remaining waveform data is read, on one hand, it is not necessary to load all the waveform data into the memory, so that the occupation of the memory is reduced, and on the other hand, it is possible to ensure that the waveform data is displayed in time, and the stutter during the debugging process and the decrease in the system response speed do not occur, thereby improving the efficiency of the debugging operation.
Drawings
In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of an authentication system according to an embodiment of the present disclosure.
Fig. 2 is a schematic flow chart of a display method of waveform data according to an embodiment of the present disclosure.
Fig. 3 is a schematic and schematic diagram of a display method of waveform data according to an embodiment of the present disclosure.
Fig. 4 is still another schematic and schematic diagram of a display method of waveform data according to an embodiment of the present disclosure.
Fig. 5 is still another schematic and schematic diagram of a display method of waveform data according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure.
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
It is to be noted that technical terms or scientific terms used in the embodiments of the present disclosure should have a general meaning as understood by those having ordinary skill in the art to which the present disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
A large amount of simulation data is generated in the simulation stage of the chip design, and increases as the scale of the chip design increases. The simulation data generally includes waveform data, the simulation data is stored in a storage medium such as a disk after the simulation is finished, when the simulation data is reproduced in a debugging stage, all the simulation data in the storage medium is generally read by a back-end device of a debugging tool, the simulation data is stored in a memory, and the front-end device of the simulation tool generates the simulation data in the memory into a corresponding waveform to be displayed. When the conventional method faces the simulation data with increasing data volume, the data volume of all the simulation data loaded at one time is large, so that the response speed of the system is reduced, the debugging process is blocked, and the debugging efficiency is reduced. Therefore, how to ensure that the system response is timely and does not jam when a large amount of waveform data is displayed in debugging becomes a problem which needs to be solved urgently.
In view of this, the embodiments of the present disclosure provide a method for displaying waveform data, which reads remaining waveform data while displaying loaded waveform data, on one hand, the waveform data does not need to be completely loaded into a memory, so as to reduce the occupation of the memory, and on the other hand, the display of the waveform data can be ensured to be performed in time, and the stutter during the debugging process and the decrease in the system response speed do not occur, thereby improving the efficiency of the debugging operation.
FIG. 1 shows a schematic diagram of an authentication system 100 according to an embodiment of the present disclosure. Verification system 100 may include a debug tool 102, a host 104, and a storage device 106.
The debug tool 102 may be a hardware or software system for debugging a Device Under Test (DUT). The DUT may also be referred to as a logic system design. The logic System design (e.g., ASIC or System-On-Chip) can be designed from a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). In some embodiments, debug tool 102 may be a software emulator (simulator). In this case, the debug tool 102 may run on a computer (e.g., host 104) to simulate the operation of the DUT and the test environment (testbench) and to generate waveform data for the DUT. In other embodiments, the debug tool 102 may be a hardware emulator (emulator) that utilizes a programmable logic device (e.g., a field programmable gate array, FPGA) to simulate the operation of the DUT. In this case, the debug tool 102 may be independent of the host 104 and communicatively connected with the host 104. The debug tool 102 can emulate the DUT on the programmable logic device and generate waveform data for the DUT as directed by the host 104. Waveform data generated by the debug tool 102 may be transmitted to the host 104 and stored in the storage device 106. It will be appreciated that in some embodiments, the hardware emulator may store the waveform data directly in the storage device 106, without going through the host 104 (not shown).
The storage device 106 may be a hard disk for long-term storage of emulation data and the like. The hard disk referred to herein is a large capacity nonvolatile storage device (e.g., a mechanical hard disk, an SSD (solid state disk), etc.). The storage device 106 may be part of the host 104 or a separate storage device communicatively connected to the host 104. The host 104 may be used to retrieve emulation data from the storage device 106 and configure the debug tool 102 for display. In some embodiments, host 104 may be a virtual host in a cloud computing system. In some embodiments, the host 104 may also obtain the simulation data of the DUT from other data sources, for example, the simulator may store the simulation data of the DUT in the other data sources, from which the host 104 may obtain the simulation data of the DUT by wired or wireless communication or copying. The simulation data in the present application includes software simulation (simulation) data and hardware simulation (emulation) data, unless otherwise specified.
The debug tool 102 may include a front end and a back end. The back-end may be used to read simulation data (e.g., waveform data), while the front-end may be used to process simulation data (e.g., generate a waveform map from the waveform data).
In embodiments of the present application, during the debug phase, the emulation data may include waveform data. A user issues a read instruction for reading specified waveform data, the debugging tool 102 can read the specified waveform data (for example, waveform data associated with a module to be debugged) from the storage device 106 according to the read instruction, the back end of the debugging tool 102 can read the specified waveform data multiple times and store the read specified waveform data in the memory of the host 104, the front end of the debugging tool 102 processes the read waveform data to generate a corresponding waveform and displays the waveform via the image interface, and at the same time, the back end of the debugging tool 102 continues to read the remaining waveform data from the storage device 106, because the time for the debugging tool 102 to process one waveform data, generate a corresponding waveform and display the waveform is longer than the time for reading one waveform data, even if the remaining waveform data is read while displaying one waveform data, the waveform data to be displayed can be guaranteed to be stored in the memory all the time, until all the specified waveform data are read, the debugging tool 102 can continuously display the specified waveform data, and the fluency of the debugging process is ensured. In addition, the waveform data is read for multiple times without reading all the waveform data, so that the occupation of the memory of the host computer by reading the waveform data every time is reduced, the response speed of the system is improved, and the problem that the debugging efficiency is influenced by the blockage in the debugging process is avoided.
Fig. 2 shows a schematic flow diagram of a method 200 of displaying waveform data according to an embodiment of the present disclosure. In some embodiments, the method 200 of displaying waveform data may be performed by a debugging tool in a verification system, such as the debugging tool 102 in fig. 1.
In fig. 2, the method 200 may specifically include the following steps.
In step S202, the debugging tool 102 may receive a first instruction for reading specified waveform data, the specified waveform data including a plurality of sub data.
Wherein the logic system design may include one or more modules, each module may include at least one signal, each signal having waveform data over a respective time period. In some embodiments, the user may determine the specified waveform data by selecting a module, a signal of a module, or a specified time period, or may determine the specified waveform data by selecting a signal.
In some embodiments, the specified waveform data may include waveform data for a user-selected module. For example, debug tool 102 may read a description of a logic system design, the logic system design including a plurality of modules; the user selects module a and module B and issues a first instruction, and the debug tool 102 can determine that the specified waveform data includes waveform data for module a and module B. For the module a, it may include a Signal _ a, where the waveform data of the Signal _ a is data _ a; for module B, it may include signals Signal _ B1 and Signal _ B2, and the waveform data of signals Signal _ B1 and Signal _ B2 are data _ B1 and data _ B2. At this time, the designated waveform data may include a plurality of sub data _ A, data _ B1 and data _ B2.
In some embodiments, the specified waveform data may also include waveform data associated with the selected module. For example, debug tool 102 may read a description of a logic system design, the logic system design including a plurality of modules; the user selects module C and issues a first instruction, and module C is associated with module D, and the debug tool 102 can determine that the specified waveform data includes waveform data for module C and module D. For the module C, it may include a Signal _ C, where the waveform data of the Signal _ C is data _ C; for module D, it may include Signal _ D, the waveform data of Signal _ D being data _ D. At this time, the designated waveform data may include waveform data _ C and data _ D, where the data _ C and the data _ D are sub data.
In some embodiments, the specified waveform data may include waveform data of a signal selected by a user. For example, debug tool 102 may read a description of a logic system design that includes a plurality of signals, which may be from one module or a plurality of modules; the user selects the Signal _ E and the Signal _ F and issues a first instruction, and the debugging tool 102 may determine that the specified waveform data includes waveform data _ E and data _ F of the Signal _ E and the Signal _ F, where the data _ E and the data _ F are the sub-data.
In some embodiments, the specified waveform data may also include waveform data associated with the selected signal. For example, debug tool 102 may read a description of a logic system design that includes a plurality of signals, which may be from one module or a plurality of modules; the user selects the Signal _ G and issues the first instruction, and the Signal _ H and the Signal _ I are associated with the Signal _ G, the debugging tool 102 may determine that the specified waveform data includes the waveform data _ G, data _ H and the data _ I of the Signal _ G, the Signal _ H and the Signal _ I, where the data _ G, data _ H and the data _ I are the sub data.
It should be understood that the above-mentioned specific waveform data is only an example and is not intended to be limiting, and the number of sub-data in the specific waveform data may be more or less, and the number of signals corresponding to each module, the number of associated modules of each module, and the number of associated signals corresponding to each signal may also be more or less, and is not limited herein.
In step S204, the debugging tool 102 may read a first sub-data of the plurality of sub-data.
In some embodiments, the plurality of sub data may be waveform data corresponding to a plurality of signals, each signal corresponding to one sub data, and the first sub data may refer to waveform data of a part of the signals therein. In still other embodiments, the plurality of sub-data may also be a plurality of segments of waveform data corresponding to one signal, each segment of waveform data corresponds to a time segment, and the first sub-data may refer to a part of the plurality of segments of waveform data.
In step S206, the debug tool 102 may process the first sub-data. In some embodiments, the debug tool 102 may decompress the waveform data, generate a waveform from the decompressed waveform data, output a waveform map using a graphical interface, and the like.
In step S208, during the processing of the first sub data, the debugging tool 102 may read a second sub data of the plurality of sub data.
In some embodiments, processing the first sub data in step S206 further includes generating a first waveform based on the first sub data and displaying the first waveform via the image interface.
In some embodiments, the number of the first sub data is determined based on a maximum number of waveforms displayed by the image interface. Further, in some embodiments, the number of the first sub-data is the maximum number.
When the waveform data is displayed through the image interface, the image interface can only display a limited number of waveforms at the same time, the number of the waveforms required to be displayed is possibly far larger than the number of the waveforms capable of being displayed by the image interface, and the limited number of the waveforms can only be displayed at the same time even if more waveform data is loaded in the memory, so that the number of the first subdata can be determined based on the maximum number of the waveforms displayed by the image interface, and the occupation of the memory by the loaded excessive waveform data is avoided.
Fig. 3 is a schematic and schematic diagram of a display method of waveform data according to an embodiment of the present disclosure. As shown in fig. 3, if the maximum number of waveforms displayed on the image interface 301 is m, the number of the first sub data may be determined to be m, and the specified waveform data includes n sub data1、data2、……、datanN is greater than or equal to m, and m and n are positive integers. Referring to FIG. 1, the debugging tool 102 can divide the specified waveform data into a first lot data if the lot is the first lot1-datamThe second batch of datam+1-data2m… … ith batch data(i-1)m+1-dataimAnd the (i + 1) th batch dataim+1-datanThe back-end device of the debugging tool 102 can read the specified waveform data in batches, and first reads the first batch of subdata data1-datamAt time t1, the first batch of sub data1-datamAfter the reading is finished, the back-end device of the debugging tool 102 notifies the front-end device of the debugging tool 102 to perform waveform drawing on the first batch of sub-data to generate a first waveform wave.1-wave.m, and displays the first waveform wave.1-wave.m on the image interface 301, during the period that the front-end device of the debugging tool 102 draws and displays the first waveform wave.1-wave.m, for example, the back-end device of the debugging tool 102 continues to read the second batch of sub-data at the time t1m+1-data2mThen, the front-end device of the debugging tool 102 continuously performs waveform drawing and displaying on the read sub-data, and the back-end device of the debugging tool 102 also reads the sub-data to be read in parallel until the (i + 1) th batch of data is readim+1-datan. Therefore, the quantity of the waveform data read at each time is not too large, the system can respond in time, the burden can not be brought to the system, and the blocking state is avoided.
In some embodiments, the data amount of each sub data is determined based on a preset time period. Further, in some embodiments, the preset duration is greater than or equal to a minimum duration, where the minimum duration is a duration corresponding to a minimum amount of data required to generate the waveform.
In this case, for some waveform data in a specific format, for example, waveform data in a VCD (value change dump) format, values of a signal at respective time points are recorded in order of time points. In a conventional manner, after waveform data in a specific format in a time period is completely loaded into a memory, values at each time point are traversed in a time sequence, which makes the loading time long.
According to the embodiment of the disclosure, the waveform data in the specific format is segmented according to the preset duration in a segmentation mode of internal data thereof, the preset duration can be greater than or equal to the duration corresponding to the minimum data amount required by the generated waveform, the waveform data with the preset duration is loaded each time to ensure that the system can respond in time, and then iteration is performed step by step, and the waveform data with the preset duration is repeatedly loaded until the loading of the waveform data of the signal is completed.
Fig. 4 is yet another schematic and schematic diagram of a method 200 of displaying waveform data according to an embodiment of the present disclosure. As shown in fig. 4, the vcd-format waveform data of a signal may be divided into the first segment of waveform data _ vcd1, the second segment of waveform data _ vcd2, … …, and the k-th segment of waveform data _ vcdk based on the minimum duration L. With reference to fig. 1, the back end of the debug tool 102 first reads the first segment of waveform data _ vcd1, the first segment of waveform data _ vcd1 is completely read at time t2, the back end device of the debug tool 102 notifies the front end of the debug tool 102 to perform waveform drawing on the first segment of waveform data _ vcd1 to generate a waveform wave.vcd1, and displays the waveform wave.vcd1 in the image interface, during the period that the front end device of the debug tool 102 draws and displays the waveform wave.vcd1, for example, the back end device of the debug tool 102 continues to read the second segment of waveform data _ vcd2 at time t2, the front end device of the debug tool 102 performs waveform drawing and display on the read sub-data uninterruptedly, and the back end device of the debug tool 102 also reads the sub-data to be read in parallel until the k segment of waveform data _ vcdkk is completely read. Therefore, on one hand, occupation of all waveform data loaded at one time on a memory can be reduced, on the other hand, waveform drawing and displaying can be started after all waveform data are loaded without waiting for completion of waveform drawing and displaying, only waveform data with preset duration of a signal are loaded, response time for signal waveform displaying is shortened, a stuck state cannot occur, and debugging efficiency is improved.
In some embodiments, the first sub data includes first signal data and second signal data, and the method 200 may further include: reading the first signal data and the second signal data; comparing the first signal data and the second signal data; and reading third signal data and fourth signal data to be compared in the second sub data during the comparison.
Wherein the comparison period may include a process of waveform-drawing the first signal data and the second signal data, displaying, and comparing the drawn waveforms. When a user needs to perform waveform comparison, it is also generally shown that all waveform data to be compared are loaded into a memory of a host computer first, and then waveform data in the memory are traversed for comparison, and similarly, all waveforms to be compared are loaded into the memory at one time, and because a huge data volume of the waveforms brings burden to a system, the memory is easily overloaded, so that the system is jammed, and corresponding waveform comparison instructions cannot be timely performed, so that the debugging efficiency is low. However, according to the embodiment of the present disclosure, during the comparison of the loaded waveform data, the remaining waveform data to be compared is loaded at the same time, so that the response speed of the system can be improved, and the user experience can be improved.
Fig. 5 is yet another schematic and schematic diagram of a method 200 of displaying waveform data according to an embodiment of the present disclosure.
As shown in fig. 5, the first sub data _1 includes the first signal data _ com1 and the second signal data _ com2 to be compared, and the second sub data _2 includes the third signal data _ com3 and the fourth signal data _ com4 to be compared.
In some embodiments, the debugging tool (e.g., 102 in fig. 1) may read the waveform data one at a time, for example, the first signal data _ com1 may be read first, and the first signal data _ com1 may be waveform-plotted at time t3 to generate a waveform wave.com 1. Com1 may be displayed on the image interface 301. Com1 (e.g., at time t3), the debug tool 102 may continue to read the second signal data _ com 2. After the reading of the second signal data _ com2 is completed, the debug tool 102 may continue to read the third signal data _ com3 and the fourth signal data _ com4 in sequence. It should be understood that, when the third signal data _ com3, the fourth signal data _ com4 are read, the first signal data _ com1 may still be in waveform drawing or displaying, or the waveform wave.com1 generated based on the first signal data _ com1 may have been displayed on the image interface and the second signal data _ com2 may be in waveform drawing or displaying, or the waveforms wave.com1 and wave.com2 generated based on the first signal data _ com1 and the second signal data _ com2 may have been displayed on the image interface 301, in a stage of comparing the waveforms wave.com1 and wave.cm 2.
In still other embodiments, the debug tool (e.g., 102 in FIG. 1) may read two waveform data at a time. For example, the debug tool 102 may first read the first signal data _ com1 and the second signal data _ com2, and perform waveform drawing, display and comparison on the first signal data _ com1 and the second signal data _ com2 after the reading is completed at time t 4. During this time (e.g., at time t4), the debug tool 102 may continue to read the third signal data _ com3 and the fourth signal data _ com 4.
It should be understood that the number of waveform data read by the debugging tool in the above embodiments is only an example, and is not intended to be limiting, and more waveform data can be read at a time, and is not limited herein.
It should be noted that the specific waveform data in the storage medium and the memory in fig. 3 to 5 are merely examples for convenience of description of the embodiments of the present disclosure, and do not mean that the specific waveform data is only stored in a continuous form in the storage medium and the memory, and may also be stored in a non-continuous manner, which is not limited herein.
In some embodiments, the method 200 further comprises: a plurality of sub data are read based on the priority of the sub data.
In the debugging process, signals of the modules have certain relevance, for example, when a plurality of modules are jointly debugged, the signals of the modules have relevance, or different signals inside a single module may also have relevance, waveforms of the relevant waveform data often need to be displayed in a relevant manner (for example, simultaneous display or front-back adjacent display), so that after a user determines the modules or signals needing to be debugged, a debugging tool can determine the priority of each subdata in the specified waveform data, and then reads the plurality of subdata according to the priority, the subdata with high relevance can be loaded in a self-adaptive manner preferentially, response speed is improved, and debugging efficiency is improved.
In some embodiments, the method 200 further comprises: reading a description of a logic system design, the logic system design comprising a plurality of modules; and determining a target module associated with the first subdata in the plurality of modules, wherein the second subdata is subdata corresponding to at least one signal of the target module.
For example, a debug tool may read a description of a logic system design, the logic system design including a plurality of modules; the user selects module J and module K and issues a first instruction, and module J is associated with module L, and the debug tool can determine that the specified waveform data includes waveform data for module J, module K, and module L. For the module J, it may include a Signal _ J, the waveform data of the Signal _ J is data _ J; for the module K, it may include a Signal _ K, the waveform data _ K of the Signal _ K; for the module L, it may include a Signal _ L, and the waveform data of the Signal _ L is data _ L. The debugging tool can read the waveform data _ J of the Signal _ J in the module J, determine the target module L related to the waveform data _ J, and the priority of the module L is higher than that of the module K.
In some embodiments, the method 200 further comprises: reading a description of a logic system design, the logic system design comprising a plurality of signals; and receiving a second instruction for reading waveform data of the designated signal; determining at least one associated signal associated with the specified signal among the plurality of signals according to the description of the logic system design; the sub data corresponding to at least one of the associated signals is preferentially read.
For example, debug tool 102 may read a description of a logic system design, the logic system design including a plurality of signals; the user selects the signal M and the signal N and issues a second instruction, and the signal M is associated with the signal O and the signal P, and the debugging tool can determine the waveform data of the specified waveform data including the signal M, the signal N, the signal O and the signal P. For the signal M, the waveform data is data _ M; for the module N, the waveform data _ N thereof; for the module O, the waveform data is data _ O; for the module P, its waveform data _ P. The debugging tool can read the waveform data _ M of the signal M and determine the associated signal O and the associated signal P associated with the waveform data _ M, so that the priority of the signal O and the priority of the signal P are higher than that of the signal N, and during the waveform drawing and displaying of the waveform data _ M by the debugging tool, the waveform data _ O, data _ P of the module L is read, and then the waveform data _ N of the signal N is read.
It should be noted that the above describes some embodiments of the disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present disclosure further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the waveform data display method according to any of the above-mentioned embodiments when executing the program.
Fig. 6 shows a hardware structure diagram of an electronic device according to an embodiment of the present disclosure, where the device may include: a processor 610, a memory 620, an input/output interface 630, a communication interface 640, and a bus 650. Wherein the processor 610, memory 620, input/output interface 630, and communication interface 640 are communicatively coupled to each other within the device via a bus 650.
The processor 610 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solutions provided in the embodiments of the present specification.
The Memory 620 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 620 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present specification is implemented by software or firmware, the relevant program codes are stored in the memory 620 and called by the processor 610 to be executed.
The input/output interface 630 is used for connecting an input/output module to realize information input and output. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.
The communication interface 640 is used for connecting a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).
It should be noted that although the above-mentioned devices only show the processor 610, the memory 620, the input/output interface 630, the communication interface 640 and the bus 650, in a specific implementation, the devices may also include other components necessary for normal operation. In addition, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement the embodiments of the present description, and not necessarily all of the components shown in the figures.
The electronic device of the foregoing embodiment is used to implement the display method of the corresponding waveform data in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which are not described herein again.
Based on the same inventive concept, the present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the method for displaying waveform data according to any of the above embodiments, corresponding to any of the above embodiment methods.
Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.
The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method for displaying waveform data according to any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which are not described herein again.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of brevity.
In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the present disclosure, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present disclosure are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.
The disclosed embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the embodiments of the disclosure are intended to be included within the scope of the disclosure.
Claims (10)
1. A method of displaying waveform data, comprising:
receiving a first instruction for reading specified waveform data, wherein the specified waveform data comprises a plurality of subdata;
reading first subdata in the plurality of subdata;
processing the first subdata; and
reading second sub-data of the plurality of sub-data during processing of the first sub-data, wherein processing of the first sub-data includes generating a first waveform based on the first sub-data and displaying the first waveform via an image interface.
2. The method of claim 1, further comprising: determining the number of the first sub data based on the maximum number of the waveforms displayed by the image interface.
3. The method of claim 1, wherein the data amount of each of the sub data is determined based on a preset time period.
4. The method of claim 3, wherein the preset time period is greater than or equal to a minimum time period, wherein the minimum time period corresponds to a minimum amount of data required to generate the waveform.
5. The method of claim 1, wherein the first sub data comprises first signal data and second signal data, and the method further comprises:
reading the first signal data and the second signal data;
comparing the first signal data and the second signal data; and
and reading third signal data and fourth signal data to be compared in the second sub data during the comparison.
6. The method of claim 1, further comprising: reading the plurality of sub data based on the priority of the sub data.
7. The method of claim 1 or 6, further comprising:
reading a description of a logic system design, the logic system design comprising a plurality of modules; and
determining a target module associated with the first child data among the plurality of modules, wherein,
the second subdata is subdata corresponding to at least one signal of the target module.
8. The method of claim 1 or 6, further comprising:
reading a description of a logic system design, the logic system design comprising a plurality of signals; and
receiving a second instruction for reading the specified signal;
determining at least one associated signal associated with the designated signal among the plurality of signals according to the description of the logic system design;
and preferentially reading the sub data corresponding to the at least one associated signal.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 8 when executing the program.
10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 8.
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