CN109490760A - A kind of apparatus for testing chip, system and method - Google Patents
A kind of apparatus for testing chip, system and method Download PDFInfo
- Publication number
- CN109490760A CN109490760A CN201811589025.4A CN201811589025A CN109490760A CN 109490760 A CN109490760 A CN 109490760A CN 201811589025 A CN201811589025 A CN 201811589025A CN 109490760 A CN109490760 A CN 109490760A
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- chip
- programmable logic
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- test
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present embodiments relate to electronic technology field more particularly to a kind of apparatus for testing chip, system and method, adapt to Multiple Type chip to provide a general test device.Apparatus for testing chip in the embodiment of the present invention includes test bottom plate；The test bottom plate includes unit of testing and controlling, test interface unit, plant-grid connection unit and chip access unit；The unit of testing and controlling includes at least programmable logic cells, and the programmable logic cells are used to provide the logic circuit suitable for chip to be measured；The chip access unit is used to provide the chip interface being adapted with the chip to be measured, so that the chip to be measured is electrical connected with the programmable logic cells；The test interface unit is electrically connected with the unit of testing and controlling, for receiving the test instruction of operation equipment transmission and providing to the programmable logic cells；The plant-grid connection unit is powered for connecting power supply for the test bottom plate.
Description
Technical field
The present invention relates to electronic technology field more particularly to a kind of apparatus for testing chip, system and method.
Background technique
Chip checking and test are very important link for the volume production of chip, will be into before shipment to every chips
Row functional test, to guarantee the yield of shipment chip, and this test process also directly affects the cost of chip.
For the IT enterprises of solid type, since equipment yield is larger, the core number for needing to introduce can be very much, type
Also very much.And for these are from the chip that other factory introduces, incorporated business needs to carry out these chips one and preliminary comes
Material detection, whether the internal firmware version to determine chip correct, and whether basic function normal etc..Due to the chip of different vendor
It encapsulates multifarious, and is not that each chip factory commercial city can provide the fixture slave pedestal to test platform of complete set.Therefore,
Need a kind of detection platform for being adapted to various chips.
Summary of the invention
The application provides a kind of apparatus for testing chip, system and method, adapts to provide a general test device
Multiple Type chip.
A kind of apparatus for testing chip provided in an embodiment of the present invention includes at least test bottom plate；The test bottom plate includes
Unit of testing and controlling, test interface unit, plant-grid connection unit and chip access unit；
The unit of testing and controlling includes at least programmable logic cells, and the programmable logic cells are applicable for providing
In the logic circuit of chip to be measured；
The chip access unit is used to provide the chip interface being adapted with the chip to be measured, so that the core to be measured
Piece is electrical connected with the programmable logic cells；
The test interface unit is electrically connected with the unit of testing and controlling, the test sent for receiving operation equipment
It instructs and is provided to the programmable logic cells；
The plant-grid connection unit is powered for connecting power supply for the test bottom plate.
In a kind of optional embodiment, the unit of testing and controlling further includes control input unit；The control input is single
It is first to be electrical connected with the programmable logic cells, for configuring signal to programmable logic cells transmission chip, so that
The programmable logic cells configure the logic circuit that signal offer is suitable for the chip to be measured according to the chip.
In a kind of optional embodiment, the unit of testing and controlling further includes programming interface, for logic circuit is corresponding
The programming of function firmware to the programmable logic cells.
In a kind of optional embodiment, the unit of testing and controlling further includes status indicator lamp, is used to indicate the test
Test mode locating for bottom plate.
In a kind of optional embodiment, the unit of testing and controlling further includes reset button, for programmable patrolling described
It collects unit and reverts to original state.
In a kind of optional embodiment, the chip access unit includes multiple chip interfaces, the programmable logic list
Member selects chip interface corresponding with the pin of the chip to be measured to be attached from the multiple chip interface.
It further include access board and chip mounting base in a kind of optional embodiment；
The access board includes mounted array and installation slot, and the mounted array is used to connect the chip mounting base,
The installation slot with the chip access unit for connecting；
The chip mounting base is connect for encapsulating chip to be measured, and with the mounted array.
In a kind of optional embodiment, the programmable logic cells are CPLD (Complex Programmable Logic Devices).
The embodiment of the present invention also provides a kind of chip test system, including apparatus for testing chip as described above, core to be measured
Piece and the operation equipment instructed for providing test.
The embodiment of the present invention also provides a kind of chip detecting method, comprising:
Programmable logic cells chip receives chip and configures signal；
The programmable logic cells configure signal according to the chip and provide logic circuit, and from chip access unit
Corresponding chip interface is selected to be attached；
The programmable logic cells receive the test instruction that operation equipment is sent, and the test instructed be sent to
Survey chip.
Apparatus for testing chip in the embodiment of the present invention includes at least test bottom plate, which includes testing and control list
Member, test interface unit, plant-grid connection unit and chip access unit.Unit of testing and controlling includes at least programmable logic list
Member, programmable logic cells are used to provide the logic circuit suitable for chip to be measured.Chip access unit for provide with it is to be measured
The adaptable chip interface of chip, so that chip to be measured is electrical connected with programmable logic cells.Test interface unit, with test
Control unit electrical connection, for receiving the test instruction of operation equipment transmission and being provided to programmable logic cells；Plant-grid connection
Unit is for connecting power supply, for test bottom plate power supply.Due to the programmable logic cells in apparatus for testing chip can provide it is suitable
For the logic circuit of multiple types chip, chip access unit provides the chip interface being adapted with chip to be measured again, because
This, the embodiment of the invention provides general apparatus for testing chip, a plurality of types of chips are adapted to, without for each
An apparatus for testing chip is arranged in kind chip, saves resource.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without any creative labor, it can also be obtained according to these attached drawings
His attached drawing.
Fig. 1 is a kind of schematic diagram of apparatus for testing chip provided in an embodiment of the present invention；
Fig. 2 is a kind of schematic diagram for apparatus for testing chip that the specific embodiment of the invention provides；
Fig. 3 is a kind of schematic diagram of access board provided in an embodiment of the present invention；
Fig. 4 is a kind of mounting means schematic diagram of apparatus for testing chip provided in an embodiment of the present invention；
Fig. 5 is a kind of schematic diagram for system architecture that the embodiment of the present invention is applicable in；
Fig. 6 is a kind of flow diagram of chip detecting method provided in an embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into
It is described in detail to one step, it is clear that the described embodiments are only some of the embodiments of the present invention, rather than whole implementation
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
All other embodiment, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of apparatus for testing chip, Fig. 1 shows its structural schematic diagram.As shown in Figure 1, extremely
Few includes test bottom plate 1；Testing bottom plate includes unit of testing and controlling 11, test interface unit 12, plant-grid connection unit 13 and core
Piece access unit 14.Unit of testing and controlling 11 includes at least programmable logic cells 111, and programmable logic cells 111 are for mentioning
For being suitable for the logic circuit of chip to be measured.Chip access unit 14 is used to provide the chip interface being adapted with chip to be measured,
So that chip to be measured is electrical connected with programmable logic cells 111.Test interface unit 12 is electrically connected with unit of testing and controlling 11
It connects, the test for providing chip to be measured to programmable logic cells 111 instructs.Plant-grid connection unit 13 is used to connect power supply,
It powers for test bottom plate 1.
Since the programmable logic cells in apparatus for testing chip can provide the logic electricity suitable for multiple types chip
Road, chip access unit provide the chip interface being adapted with chip to be measured again, and therefore, the embodiment of the invention provides general
Apparatus for testing chip, be adapted to a plurality of types of chips, filled it is not necessary that chip testing is arranged for each chip
It sets, saves resource.
Plant-grid connection unit 13 in the embodiment of the present invention, may include voltage regulator circuit, and 15V, 9V, 5V, 3.3V power supply are defeated
Incoming interface, multistage LDO (Low Dropout Regulator, low pressure difference linear voltage regulator) pressure stabilizing export anti-reverse graft circuit.
Programmable logic cells 111 can (Complex Programmable Logic Device, complexity can for CPLD
Programmed logic device), it is a kind of user according to respective the need and voluntarily digital integrated electronic circuit of constitutive logic function, it can be by user
Specific circuit structure is generated as needed, completes certain function.
Test interface unit 12 is set of interfaces needed for test, including common all kinds of interfaces, as SPI interface, I2C connect
Mouth, Uart0 interface, Uart2 interface, GPIO interface, I/O interface, SIM card interface and network interface etc..
In a kind of preferable specific embodiment, above-mentioned unit of testing and controlling 11 further includes that control input unit 112, programming connect
Mouth 113, status indicator lamp 114 and reset button 115.As shown in Fig. 2, control input unit 112 and programmable logic cells 111
It is electrical connected, signal is configured for transmitting chip to programmable logic cells 111, so that programmable logic cells 111 are according to core
Piece configuration signal provides the logic circuit for being applicable in chip to be measured.Control input unit 112 in the embodiment of the present invention can be square
Battle array keyboard.Program inside programmable logic cells 111, the information that can be transmitted by matrix keyboard, is screened and is matched,
Meanwhile by the pin line of the corresponding required connection chip to be measured of matrix keyboard selection and needing interface to be tested.
Programming interface 113 is specifically as follows JTAG (Joint Test Action Group；Joint test working group) it connects
Mouthful, it is used for the corresponding function firmware programming of logic circuit to programmable logic cells.It specifically, can be by external dedicated
Complex programmable logic fever writes are connected on programming interface 113, can be by function firmware by electronic equipments such as laptop computers
In programming to complex programmable logic.Alternatively, it is also possible to carry out firmware upgrade by way of remote upgrade.Firstly, passing through net
The firmware that the mode of network upgrades needs, downloads in the electronic equipment of connection, later, is connected to complex programmable by control
Logical device configuration pin simulates downloading timing, completes firmware remote upgrade.
Status indicator lamp 114 is used to indicate test mode locating for test bottom plate.For example, during the test, state refers to
Show that lamp 114 can be yellow；Test is completed, and status indicator lamp 114 is green；Test does not pass through, and status indicator lamp 114 is shown as
It is red.In addition, the upgrading performance of programmable logic cells can also be indicated by status indicator lamp 114.Specifically, shape
State indicator light 114 can be LED light cluster.
Reset button 115, for programmable logic cells 111 to be reverted to original state, convenient for different types of core
When built-in testing, different logic circuits is provided.
Preferably, the chip access unit 14 in the embodiment of the present invention includes multiple chip interfaces, programmable logic cells
111 select chip interface corresponding with the pin of chip to be measured to be attached from multiple chip interfaces.For example, chip access is single
Member 14 can arrange seat for two 32 needles, as shown in 141 in Fig. 2, include 32 chip interfaces in each 32 needle row seat, can compile
Journey logic unit 111 arranges seat by the two 32 needles and is connected with the pin of chip to be measured.
For example, when what is if desired tested is a Modem (modem) chip, before testing, obtaining should
The pin information and chip data of modem chip, determine the logic circuit of complex programmable logic unit, and according to the Modem
Pin distribution carry out electric wiring, the interface position by required test is drawn with pin later, and access operation equipment is surveyed
Try correlation function.The function of test can be believed such as power supply, clock, Uart line, electrifying timing sequence correlation function and necessary pull-up
Number etc..
Fixed installation when testing chip to be measured for convenience, the embodiment of the invention also includes access boards and core
Piece mounting base.
Fig. 3 shows a kind of schematic diagram of optional access board, as shown in figure 3, access board 2 includes mounted array and installation
Slot, mounted array are used to connect with the chip access unit 14 of test bottom plate for connecting chip mounting base, installation slot, because
This, the form for installing slot is corresponding with the form of chip access unit 14, for example, chip access unit 14 is two 32 needles rows
Seat, then installing slot also is two 32 needles row's seats.
Chip mounting base is connect for encapsulating chip to be measured, and with the mounted array of access board.Chip mounting base can be set
It is set to knob chip pad.Customization mainly is provided by third party manufacturer, because of the specificity of the chip package of different model, no
The chip of different encapsulation may be placed with a pedestal, therefore need to customize.It is worth noting that, being needed in the requirement of customization
The pin of chip is drawn, and according to the lead pin pitch and layout of the setting extraction of the mounted array of access board, so that different
Chip mounting base can adapt to the access board in the embodiment of the present invention, and further realizing different chip mounting bases can be even
After connecing access board 2, it is connected in the same test bottom plate.
Fig. 4 shows a kind of mounting means of apparatus for testing chip provided in an embodiment of the present invention.As shown in figure 4, to be measured
Chip 4 is fitted into chip mounting base 3, and chip mounting base 3 is installed on access board 2, the peace of chip mounting base 3 and access board 2
Dress array is connected.Access board 2 is installed on test bottom plate 1, the chip that access board 2 passes through installation slot and test bottom plate 1
Access unit is connected.
The applicable a kind of system architecture of the embodiment of the present invention, as shown in figure 5, including said chip test device, core to be measured
Piece and the operation equipment instructed for providing test.
Based on system architecture shown in fig. 5, the embodiment of the invention provides a kind of chip detecting methods, as shown in fig. 6, this
Inventive embodiments provide chip detecting method the following steps are included:
Step 601, programmable logic cells chip receive chip and configure signal.
Step 602, the programmable logic cells configure signal according to the chip and provide logic circuit, and connect from chip
Enter and corresponding chip interface is selected to be attached in unit.
Step 603, the programmable logic cells receive the test instruction that operation equipment is sent, and the test is instructed
It is sent to chip to be measured.
For convenience's sake, specific terminology has been used in the explanation of the embodiment of the present invention, and this is not limit
Property processed.Word "left", "right", "up" and "down" indicate the direction in the attached drawing of reference.Word " inside " and " outside " point
Do not refer to the geometric center of the object and its specified portions toward and away from description.Term includes specifically mentioned above arranges
Word, its derivative and the similar word introduced.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the invention is also intended to include including these modification and variations.
Claims (10)
1. a kind of apparatus for testing chip, which is characterized in that include at least test bottom plate；The test bottom plate includes testing and control list
Member, test interface unit, plant-grid connection unit and chip access unit；
The unit of testing and controlling include at least programmable logic cells, the programmable logic cells for provide be suitable for
Survey the logic circuit of chip；
The chip access unit be used for provides with the chip to be measured be adapted chip interface so that the chip to be measured and
The programmable logic cells are electrical connected；
The test interface unit is electrically connected with the unit of testing and controlling, the test instruction sent for receiving operation equipment
And it is provided to the programmable logic cells；
The plant-grid connection unit is powered for connecting power supply for the test bottom plate.
2. device as described in claim 1, which is characterized in that the unit of testing and controlling further includes control input unit；Institute
It states control input unit to be electrical connected with the programmable logic cells, for matching to programmable logic cells transmission chip
Confidence number, so that the programmable logic cells configure the logic that signal offer is suitable for the chip to be measured according to the chip
Circuit.
3. device as described in claim 1, which is characterized in that the unit of testing and controlling further includes programming interface, and being used for will
The corresponding function firmware programming of logic circuit is to the programmable logic cells.
4. device as described in claim 1, which is characterized in that the unit of testing and controlling further includes status indicator lamp, is used for
Indicate test mode locating for the test bottom plate.
5. device as described in claim 1, which is characterized in that the unit of testing and controlling further includes reset button, and being used for will
The programmable logic cells revert to original state.
6. device as described in claim 1, which is characterized in that the chip access unit includes multiple chip interfaces, described
Programmable logic cells select chip interface corresponding with the pin of the chip to be measured to carry out from the multiple chip interface
Connection.
7. such as device as claimed in any one of claims 1 to 6, which is characterized in that further include access board and chip mounting base；
The access board includes mounted array and installation slot, and the mounted array is described for connecting the chip mounting base
Installation slot with the chip access unit for connecting；
The chip mounting base is connect for encapsulating chip to be measured, and with the mounted array.
8. such as device as claimed in any one of claims 1 to 6, which is characterized in that the programmable logic cells are CPLD (complicated
Programmable logic device).
9. a kind of chip test system, which is characterized in that including the described in any item apparatus for testing chip of claim 1 to 9, to
Survey chip and for providing the operation equipment of test instruction.
10. a kind of chip detecting method characterized by comprising
Programmable logic cells chip receives chip and configures signal；
The programmable logic cells configure signal according to the chip and provide logic circuit, and select from chip access unit
Corresponding chip interface is attached；
The programmable logic cells receive the test instruction that operation equipment is sent, and test instruction is sent to core to be measured
Piece.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811589025.4A CN109490760A (en) | 2018-12-25 | 2018-12-25 | A kind of apparatus for testing chip, system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811589025.4A CN109490760A (en) | 2018-12-25 | 2018-12-25 | A kind of apparatus for testing chip, system and method |
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| CN109490760A true CN109490760A (en) | 2019-03-19 |
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| CN201811589025.4A Pending CN109490760A (en) | 2018-12-25 | 2018-12-25 | A kind of apparatus for testing chip, system and method |
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| CN110072023A (en) * | 2019-03-30 | 2019-07-30 | 岳西县天鹅电子科技有限公司 | A kind of modem of installation easy to disassemble |
| CN110275805A (en) * | 2019-06-13 | 2019-09-24 | 上海琪埔维半导体有限公司 | A kind of full-automatic test system for MCU chip |
| CN111913471A (en) * | 2020-07-21 | 2020-11-10 | 北京京瀚禹电子工程技术有限公司 | Testing device |
| CN113238980A (en) * | 2021-04-07 | 2021-08-10 | 南昌华勤电子科技有限公司 | Chip connecting device and system |
| US20230027611A1 (en) * | 2021-07-26 | 2023-01-26 | Realtek Semiconductor Corporation | Power supply device, power supply system and non-transitory computer-readable recording medium |
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Effective date of registration: 20200108 Address after: 510663 Shenzhou Road 10, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangzhou, Guangdong Applicant after: Jingxin Communication System (China) Co., Ltd. Address before: 510663 Shenzhou Road, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangdong, 10 Applicant before: Jingxin Communication System (China) Co., Ltd. Applicant before: Jingxin Communication System (Guangzhou) Co., Ltd. Applicant before: Jingxin Communication Technology (Guangzhou) Co., Ltd. Applicant before: TIANJIN COMBA TELECOM SYSTEMS CO., LTD. |
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Address after: 510663 Shenzhou Road 10, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangzhou, Guangdong Applicant after: Jingxin Network System Co.,Ltd. Address before: 510663 Shenzhou Road 10, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangzhou, Guangdong Applicant before: Comba Telecom System (China) Ltd. |
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Application publication date: 20190319 |