CN109478081A - 管理跨不同时钟域的时钟信号的频率变化 - Google Patents

管理跨不同时钟域的时钟信号的频率变化 Download PDF

Info

Publication number
CN109478081A
CN109478081A CN201680087626.8A CN201680087626A CN109478081A CN 109478081 A CN109478081 A CN 109478081A CN 201680087626 A CN201680087626 A CN 201680087626A CN 109478081 A CN109478081 A CN 109478081A
Authority
CN
China
Prior art keywords
clock
clock signal
edge
processor
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201680087626.8A
Other languages
English (en)
Chinese (zh)
Inventor
史蒂文·科姆鲁施
艾米塔布赫·梅拉
理查德·马丁·博恩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN109478081A publication Critical patent/CN109478081A/zh
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
CN201680087626.8A 2016-07-13 2016-09-15 管理跨不同时钟域的时钟信号的频率变化 Pending CN109478081A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,521 US10168731B2 (en) 2016-07-13 2016-07-13 Managing frequency changes of clock signals across different clock domains
US15/209,521 2016-07-13
PCT/US2016/051813 WO2018013155A1 (en) 2016-07-13 2016-09-15 Managing frequency changes of clock signals across different clock domains

Publications (1)

Publication Number Publication Date
CN109478081A true CN109478081A (zh) 2019-03-15

Family

ID=60941023

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680087626.8A Pending CN109478081A (zh) 2016-07-13 2016-09-15 管理跨不同时钟域的时钟信号的频率变化

Country Status (6)

Country Link
US (1) US10168731B2 (enExample)
EP (1) EP3485341B1 (enExample)
JP (1) JP6707706B2 (enExample)
KR (1) KR102427773B1 (enExample)
CN (1) CN109478081A (enExample)
WO (1) WO2018013155A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI755830B (zh) * 2020-08-28 2022-02-21 力晶積成電子製造股份有限公司 記憶體的讀取方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7034156B2 (ja) 2016-10-31 2022-03-11 グローバル・ライフ・サイエンシズ・ソリューションズ・ユーエスエー・エルエルシー 生物反応器組立体
CN113227935B (zh) * 2018-10-24 2024-09-13 奇跃公司 异步asic
WO2020242991A1 (en) 2019-05-24 2020-12-03 Intel Corporation Device, method and system for transparently changing a frequency of an interconnect fabric
US11967960B2 (en) * 2021-07-30 2024-04-23 Advanced Micro Devices, Inc. Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
CN114461012B (zh) * 2022-01-19 2024-05-10 许昌许继软件技术有限公司 一种嵌入式系统不同时钟域运行时戳获取方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090319745A1 (en) * 2004-06-04 2009-12-24 Laberge Paul A System and method for an asynchronous data buffer having buffer write and read pointers
CN102647374A (zh) * 2011-02-18 2012-08-22 瑞昱半导体股份有限公司 跨时钟域的干扰消除装置及方法
CN103003807A (zh) * 2010-07-28 2013-03-27 格诺多有限公司 第一时钟域和第二时钟域之间的同步数据传输
CN103650406A (zh) * 2011-05-23 2014-03-19 英特尔移动通信有限公司 用于同步第一时钟域与第二时钟域之间的数据切换的设备
CN103812590A (zh) * 2012-11-12 2014-05-21 辉达公司 用于确定用于安全采样时钟域的信号的时间的系统和方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200095A (ja) * 1993-12-28 1995-08-04 Victor Co Of Japan Ltd データ転送回路
JP3417476B2 (ja) * 2000-09-06 2003-06-16 日本電気株式会社 多入力データ同期回路
US7194500B2 (en) * 2003-07-11 2007-03-20 Sony Corporation Scalable gray code counter
US7315600B2 (en) * 2004-03-30 2008-01-01 Arm Limited Asynchronous FIFO apparatus and method for passing data between a first clock domain and a second clock domain and a second clock domain of a data processing apparatus
US7574635B1 (en) * 2004-12-23 2009-08-11 Xilinx, Inc. Circuit for and method of testing a memory device
US7234017B2 (en) * 2005-02-24 2007-06-19 International Business Machines Corporation Computer system architecture for a processor connected to a high speed bus transceiver
US8260982B2 (en) 2005-06-07 2012-09-04 Lsi Corporation Method for reducing latency
TW200717519A (en) * 2005-10-28 2007-05-01 Univ Nat Chiao Tung Asynchronous first-in-first-out cell
WO2008129364A1 (en) 2007-04-23 2008-10-30 Nokia Corporation Transferring data between asynchronous clock domains
US7934113B2 (en) * 2007-05-21 2011-04-26 Texas Instruments Incorporated Self-clearing asynchronous interrupt edge detect latching register
TWI385924B (zh) * 2009-09-24 2013-02-11 Richwave Technology Corp 非同步先進先出介面、介面操作方法和整合式接收器
US8433875B2 (en) 2010-02-24 2013-04-30 Esilicon Corporation Asynchronous scheme for clock domain crossing
WO2013100976A1 (en) 2011-12-28 2013-07-04 Intel Corporation Data transfer between asynchronous clock domains
WO2013147839A1 (en) * 2012-03-30 2013-10-03 Intel Corporation On-die all-digital delay measurement circuit
US9367286B2 (en) * 2013-08-28 2016-06-14 Imagination Technologies Limited Crossing pipelined data between circuitry in different clock domains
US9449127B1 (en) * 2015-04-01 2016-09-20 Freescale Semiconductor, Inc. System for verifying timing constraints of IC design

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090319745A1 (en) * 2004-06-04 2009-12-24 Laberge Paul A System and method for an asynchronous data buffer having buffer write and read pointers
CN103003807A (zh) * 2010-07-28 2013-03-27 格诺多有限公司 第一时钟域和第二时钟域之间的同步数据传输
CN102647374A (zh) * 2011-02-18 2012-08-22 瑞昱半导体股份有限公司 跨时钟域的干扰消除装置及方法
CN103650406A (zh) * 2011-05-23 2014-03-19 英特尔移动通信有限公司 用于同步第一时钟域与第二时钟域之间的数据切换的设备
CN103812590A (zh) * 2012-11-12 2014-05-21 辉达公司 用于确定用于安全采样时钟域的信号的时间的系统和方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI755830B (zh) * 2020-08-28 2022-02-21 力晶積成電子製造股份有限公司 記憶體的讀取方法

Also Published As

Publication number Publication date
KR102427773B1 (ko) 2022-08-01
WO2018013155A1 (en) 2018-01-18
US20180017988A1 (en) 2018-01-18
JP2019522858A (ja) 2019-08-15
EP3485341B1 (en) 2022-09-07
US10168731B2 (en) 2019-01-01
KR20190018742A (ko) 2019-02-25
JP6707706B2 (ja) 2020-06-10
EP3485341A4 (en) 2020-03-18
EP3485341A1 (en) 2019-05-22

Similar Documents

Publication Publication Date Title
CN109478081A (zh) 管理跨不同时钟域的时钟信号的频率变化
CN111316234B (zh) 极低功率微控制器系统
CN102257569B (zh) 时钟转发的低功率信号传输系统
US5506809A (en) Predictive status flag generation in a first-in first-out (FIFO) memory device method and apparatus
ES2365438T3 (es) Dispositivo de circuito y procedimiento para medir la fluctuación de reloj.
US9628089B1 (en) Supply voltage tracking clock generator in adaptive clock distribution systems
CN102571319B (zh) 用于在频率改变期间的高效延迟锁定环训练协议的机制
US8195849B2 (en) Device and method for transferring data between devices
TW200539182A (en) Synchronization devices having input/output delay model tuning elements
TW201250452A (en) Apparatus, method, and system for improved power delivery performance with a dynamic voltage pulse scheme
US11683149B2 (en) Precise time management using local time base
US10083736B1 (en) Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage
US9672882B1 (en) Conditional reference voltage calibration of a memory system in data transmisson
US9666264B1 (en) Apparatus and method for memory calibration averaging
WO2012064537A2 (en) Using a stuttered clock signal to reduce self-induced voltage noise
US8023343B2 (en) Systems and methods for issuing address and data signals to a memory array
JP2021506027A (ja) ポインタオフセットを用いた非同期バッファ
US20150277481A1 (en) Semiconductor device
US20180061465A1 (en) System and Method for Calibrating Memory Using Credit-Based Segmentation Control
US9104364B2 (en) Generation and distribution of steered time interval pulse to a plurality of hardware components of the computing system
US7047433B2 (en) Method and circuit for synchronizing a higher frequency clock and a lower frequency clock
CN113922905B (zh) 一种交叉连接设备及其时钟保持方法、系统
US12445120B2 (en) Dynamic setup and hold times adjustment for memories
KR100834399B1 (ko) 반도체 메모리 장치 및 그의 구동방법
WO2023064729A1 (en) Dynamic setup and hold times adjustment for memories

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190315

RJ01 Rejection of invention patent application after publication