CN109473468A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN109473468A CN109473468A CN201811261431.8A CN201811261431A CN109473468A CN 109473468 A CN109473468 A CN 109473468A CN 201811261431 A CN201811261431 A CN 201811261431A CN 109473468 A CN109473468 A CN 109473468A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims description 26
- 239000012535 impurity Substances 0.000 claims abstract description 186
- 238000002360 preparation method Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 41
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 25
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910021480 group 4 element Inorganic materials 0.000 claims abstract description 24
- 238000000137 annealing Methods 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 16
- 239000007787 solid Substances 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 7
- RRNIZKPFKNDSRS-UHFFFAOYSA-N Bensulide Chemical group CC(C)OP(=S)(OC(C)C)SCCNS(=O)(=O)C1=CC=CC=C1 RRNIZKPFKNDSRS-UHFFFAOYSA-N 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 230000004913 activation Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021478 group 5 element Inorganic materials 0.000 description 4
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 238000005280 amorphization Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052729 chemical element Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- BLMUAVFFONATJG-UHFFFAOYSA-L dipotassium;4-[4-(4-sulfonatophenyl)hexan-3-yl]benzenesulfonate Chemical compound [K+].[K+].C=1C=C(S([O-])(=O)=O)C=CC=1C(CC)C(CC)C1=CC=C(S([O-])(=O)=O)C=C1 BLMUAVFFONATJG-UHFFFAOYSA-L 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a germanium-based semiconductor preparation body with a source region and/or a drain region, wherein the doping impurities of the source region and/or the drain region are first N-type impurities; a pre-epitaxial layer is arranged on the exposed surface of the source region and/or the drain region, the pre-epitaxial layer comprises a base material and a second N-type impurity doped in the base material, the base material comprises a non-Ge group IV element, and the doping concentration of the second N-type impurity is 1.0 multiplied by 1020cm‑3～9.0×1021cm‑3To (c) to (d); injecting third impurities into the pre-epitaxial layer to make the part of the pre-epitaxial layer far away from the semiconductor preparation body amorphous to form an epitaxial layer;providing an electrode layer on a surface of the epitaxial layer remote from the source and/or drain regions; and carrying out heat treatment on the semiconductor preparation body provided with the electrode layer to form a source contact and/or a drain contact. The source contact and/or the drain contact formed by the manufacturing method has low contact resistance.
Description
Technical field
This application involves semiconductor fields, in particular to a kind of semiconductor devices and its production method.
Background technique
Germanium material becomes the extremely promising hair of high-performance MOS devices using its high and symmetrical carrier mobility as advantage
Open up one of direction.But there are still many urgent problems to be solved for germanium base NMOS device, such as since low N-type impurity activation is dense
Degree leads to excessive source-drain contact resistance, limit device performance boost.
Disclosed information above is used only to reinforce the background technique to technology described herein in the background section
Understanding may include therefore certain information in background technique, these information are to those skilled in the art and not formed
The home known prior art.
Summary of the invention
The main purpose of the application is to provide a kind of semiconductor devices and its production method, to solve germanium in the prior art
The larger problem of the source-drain contact resistance of base device.
To achieve the goals above, according to the one aspect of the application, a kind of production method of semiconductor devices is provided,
The production method includes: to provide the semiconductor Tooth preparation with source region and/or drain region, and above-mentioned semiconductor Tooth preparation is that germanium base is partly led
Body Tooth preparation, and the impurity in above-mentioned source region and/or above-mentioned drain region is the first N-type impurity；In above-mentioned source region and/or above-mentioned leakage
Pre- epitaxial layer is set on the exposed surface in area, and above-mentioned pre- epitaxial layer includes basis material and is entrained in above-mentioned basis material
Second N-type impurity, above-mentioned basis material include the Group IV element of non-Ge, the doping concentration of above-mentioned second N-type impurity 1.0 ×
1020cm-3~9.0 × 1021cm-3Between；Third impurity is injected into above-mentioned pre- epitaxial layer, so that above-mentioned pre- epitaxial layer is separate
The partial amorphization of above-mentioned semiconductor Tooth preparation, so that above-mentioned pre- epitaxial layer forms epitaxial layer；In the remote of above-mentioned epitaxial layer
From electrode layer is arranged on the surface in above-mentioned source region and/or above-mentioned drain region；To be provided with the above-mentioned semiconductor Tooth preparation of electrode layer into
Row heat treatment forms source contact and/or drain contact.
Further, above-mentioned third impurity includes third N-type impurity, and above-mentioned third impurity is injected into above-mentioned pre- epitaxial layer
Process include: that above-mentioned third N-type impurity is injected into above-mentioned pre- epitaxial layer so that above-mentioned pre- epitaxial layer is partly led far from above-mentioned
The first part of body Tooth preparation is decrystallized, and the doping concentration of the N-type impurity in above-mentioned pre- epitaxial layer is made to be 0.8~1.0C,
Wherein, C is the solid solubility of the N-type impurity in above-mentioned pre- epitaxial layer；To inject the above-mentioned pre- epitaxial layer of above-mentioned third N-type impurity into
Row annealing.
Further, above-mentioned third impurity includes the non-N-type impurity of third, and it is miscellaneous to inject above-mentioned third into above-mentioned pre- epitaxial layer
The process of matter further include: the non-N-type impurity of third is injected into above-mentioned pre- epitaxial layer, at least so that above-mentioned pre- epitaxial layer is separate upper
The second part for stating semiconductor Tooth preparation is decrystallized, and the non-N-type impurity of above-mentioned third includes Group IV element.
Further, above-mentioned third impurity includes third N-type impurity and the non-N-type impurity of third, into above-mentioned pre- epitaxial layer
Inject the process of above-mentioned third impurity further include: above-mentioned third N-type impurity is injected into above-mentioned pre- epitaxial layer, so that above-mentioned pre- outer
The first part far from above-mentioned semiconductor Tooth preparation for prolonging layer is decrystallized, and makes mixing for N-type impurity in above-mentioned pre- epitaxial layer
Miscellaneous concentration is 0.8~1.0C, wherein C is the solid solubility of the N-type impurity in above-mentioned pre- epitaxial layer；To injecting, above-mentioned third N-type is miscellaneous
The above-mentioned pre- epitaxial layer of matter is annealed；The non-N-type impurity of third is injected into the above-mentioned pre- epitaxial layer after annealing, at least so that on
The second part including first part far from above-mentioned semiconductor Tooth preparation for stating pre- epitaxial layer is decrystallized, and the non-N of above-mentioned third
Type impurity includes Group IV element.
When further, between -100 DEG C~25 DEG C of temperature, it is miscellaneous that the non-N-type of above-mentioned third is injected into above-mentioned pre- epitaxial layer
Matter, preferably above-mentioned basis material includes silicon, and the above-mentioned non-N-type impurity of third includes silicon and/or germanium.
When further, between -100 DEG C~25 DEG C of temperature, it is miscellaneous that above-mentioned third N-type is injected into above-mentioned pre- epitaxial layer
Matter.
Further, above-mentioned annealing is implemented using dynamic surface annealing processing, the temperature of preferably above-mentioned annealing 500~
Between 1200 DEG C.
According to the another aspect of the application, a kind of semiconductor devices is provided, the semiconductor devices is by any above-mentioned
Production method is made.
According to the application's in another aspect, providing a kind of semiconductor devices, which includes: semiconductor preparation
Body, has source region and/or drain region, and above-mentioned semiconductor Tooth preparation is Ge-based semiconductor Tooth preparation, and above-mentioned source region and/or above-mentioned leakage
The impurity in area is the first N-type impurity；Epitaxial layer, on the surface in above-mentioned source region and/or above-mentioned drain region, above-mentioned epitaxial layer
The side far from above-mentioned semiconductor Tooth preparation there is decrystallized part, above-mentioned epitaxial layer includes basis material and being entrained in
The second N-type impurity in basis material is stated, above-mentioned basis material includes the Group IV element of non-Ge, above-mentioned second N-type impurity
Doping concentration is 1.0 × 1020cm-3~9.0 × 1021cm-3Between；Electrode layer, positioned at above-mentioned epitaxial layer far from above-mentioned source region
And/or on the surface in above-mentioned drain region, an above-mentioned electrode layer and an above-mentioned epitaxial layer form source contact or drain contact.
Further, above-mentioned decrystallized part includes third N-type impurity, and the N-type impurity in above-mentioned epitaxial layer is dense
Degree is 0.8~1.0C, wherein C is the solid solubility of the N-type impurity in above-mentioned epitaxial layer.
Further, above-mentioned decrystallized part includes the non-N-type impurity of third, and the above-mentioned non-N-type impurity of third includes Section IV
Race's element.
Using the technical solution of the application, in above-mentioned production method, doping is set on the surface in source region and/or drain region
There is the epitaxial layer of N-type impurity, and the concentration of the N-type impurity in the epitaxial layer is higher, 1.0 × 1020cm-3~9.0 × 1021cm-3
Or it is higher, in this way, being higher than the activation concentration of the N-type impurity in epitaxial layer in source region and/or drain region, and then can drop
The contact resistance of low source contact and/or drain contact；In addition, forming decrystallized part in the epitaxial layer in the production method, making
The concentration for obtaining n-type doping impurity in the part of electrode layer and decrystallized contact is higher, so that contact resistance is smaller；Furthermore
Since the basis material of epitaxial layer includes the Group IV element of non-Ge, the basis material and germanium have good conduction band EcAlignment
Property, and conduction band effective mass mcThe contact resistance very little at the interface between epitaxial layer and Ge for being not much different, therefore introducing.Therefore,
The contact resistance of source contact and/or drain contact that the production method is formed is smaller.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 to Fig. 5 shows a kind of structural schematic diagram of the manufacturing process of semiconductor devices of the application；And
Fig. 6 shows the structural schematic diagram of another semiconductor devices.
Wherein, the above drawings include the following reference numerals:
10, semiconductor Tooth preparation；11, source region；12, drain region；20, pre- epitaxial layer；21, epitaxial layer；211, first part；
212, second part；30, electrode layer；31, source contacts；32, drain contact；40, grid.
Specific embodiment
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also it is intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
It should be understood that when element (such as layer, film, region or substrate) is described as at another element "upper", this yuan
Part can be directly on another element, or intermediary element also may be present.Moreover, in specification and claims, when
When description has element " connected " to another element, which " can be directly connected to " to another element, or pass through third element
" connected " to another element.
As background technique is introduced, in germanium base NMOS device in the prior art, source-drain area has lower N-type miscellaneous
Matter activates concentration, and then leads to excessive source-drain contact resistance, limit device performance boost, in order to which the technology for solving as above is asked
Topic, present applicant proposes a kind of semiconductor devices and its production method.
In a kind of typical embodiment of the application, a kind of production method of semiconductor devices, the production side are provided
Method includes: to provide the semiconductor Tooth preparation with source region 11 and/or drain region, and above-mentioned semiconductor Tooth preparation is Ge-based semiconductor preparation
Body, and the impurity in above-mentioned source region 11 and/or above-mentioned drain region is the first N-type impurity, illustrates only source region 11 in Fig. 1；Upper
It states and pre- epitaxial layer 20 is set on the exposed surface in source region 11 and/or above-mentioned drain region, and above-mentioned pre- epitaxial layer 20 includes basis material
With the second N-type impurity being entrained in above-mentioned basis material, above-mentioned basis material includes the Group IV element of non-Ge, and above-mentioned second
The doping concentration of N-type impurity is 1.0 × 1020cm-3~9.0 × 1021cm-3Between, it is illustrated only in Fig. 2 on the surface of source region 11
Structure after upper setting epitaxial layer 21；Third impurity is injected into above-mentioned pre- epitaxial layer 20, so that above-mentioned pre- epitaxial layer 20 is remote
Partial amorphization from above-mentioned semiconductor Tooth preparation, as shown in Fig. 2, epitaxial layers 21 inject P ion；To the upper of partial amorphization
It states pre- epitaxial layer 20 to anneal, so that above-mentioned pre- epitaxial layer 20 forms epitaxial layer 21；Above-mentioned epitaxial layer 21 after annealing
Electrode layer 30 is set on the surface far from above-mentioned source region 11 and/or above-mentioned drain region；To the above-mentioned semiconductor for being provided with electrode layer 30
Tooth preparation is heat-treated, and source contact 31 and/or drain contact are formed.
In above-mentioned production method, the epitaxial layer doped with N-type impurity is set on the surface in source region and/or drain region, and
The concentration of N-type impurity in the epitaxial layer is higher, 1.0 × 1020cm-3~9.0 × 1021cm-3Or it is higher, in this way, making outer
The activation concentration for prolonging the N-type impurity in layer is higher than in source region and/or drain region, and then can reduce source contact and/or drain contact
Contact resistance；In addition, form decrystallized part in the epitaxial layer in the production method, so that electrode layer and decrystallized connecing
The concentration of n-type doping impurity is higher in the part of touching, so that contact resistance is smaller；Furthermore due to the matrix material of epitaxial layer
Material includes the Group IV element of non-Ge, and the basis material and germanium have good conduction band EcAlignment, and conduction band effective mass mcPhase
It is poor little, therefore the contact resistance very little at the interface between the epitaxial layer and Ge introduced.Therefore, the source contact which forms
And/or the contact resistance of drain contact is smaller.
In a kind of specific embodiment of the application, above-mentioned third impurity includes third N-type impurity, to above-mentioned pre- epitaxial layer
The process that above-mentioned third impurity is injected in 20 includes: to inject above-mentioned third N-type impurity into above-mentioned pre- epitaxial layer 20, so that above-mentioned
The first part 211 far from above-mentioned semiconductor Tooth preparation of pre- epitaxial layer 20 is decrystallized, as shown in Fig. 2, and making above-mentioned pre- outer
The doping concentration for prolonging the N-type impurity in layer 20 is 0.8~1.0C, wherein C is consolidating for the N-type impurity in above-mentioned pre- epitaxial layer 20
Solubility；It anneals to the above-mentioned pre- epitaxial layer 20 for injecting above-mentioned third N-type impurity.By injecting the 3rd N to pre- epitaxial layer 20
Type impurity and subsequent annealing, so that the N-type impurity concentration of pre- epitaxial layer 20 further increases, so as to further decrease
The contact resistance of source contact 31 and/or drain contact.
In order to further enhance the crystallization degree in epitaxial layer 21, so that contact resistance is further decreased, the one of the application
In kind embodiment, above-mentioned third impurity includes the non-N-type impurity of third, injects above-mentioned third impurity into above-mentioned pre- epitaxial layer 20
Process further include: the non-N-type impurity of third is injected into above-mentioned pre- epitaxial layer 20, at least so that above-mentioned pre- epitaxial layer 20 is separate upper
The second part 212 for stating semiconductor Tooth preparation is decrystallized, and the non-N-type impurity of above-mentioned third includes Group IV element, shown in Fig. 3
In the process, Ge ion is injected into pre- epitaxial layer 20.
In another embodiment of the application, above-mentioned third impurity includes third N-type impurity and the non-N-type impurity of third, to
The process of above-mentioned third impurity is injected in above-mentioned pre- epitaxial layer 20 further include: inject above-mentioned 3rd N into above-mentioned pre- epitaxial layer 20
Type impurity so that the first part 211 far from above-mentioned semiconductor Tooth preparation of above-mentioned pre- epitaxial layer 20 is decrystallized, and makes above-mentioned
The doping concentration of N-type impurity in pre- epitaxial layer 20 is 0.8~1.0C, wherein C is the N-type impurity in above-mentioned pre- epitaxial layer 20
Solid solubility, to further promote the doping concentration of the N-type impurity in pre- epitaxial layer 20；To the above-mentioned third N-type impurity of injection
Above-mentioned pre- epitaxial layer 20 anneal, the concentration of the N-type impurity in pre- epitaxial layer 20 is further increased；To after annealing
The non-N-type impurity of third is injected in above-mentioned pre- epitaxial layer 20, at least so that the separate above-mentioned semiconductor preparation of above-mentioned pre- epitaxial layer 20
The second part 212 including first part 211 of body is decrystallized, and the non-N-type impurity of above-mentioned third include Group IV element i.e. pair
The first part 211 of crystallization carries out again decrystallized, so that the volume of the amorphized portion in pre- epitaxial layer 20 is more
Big and decrystallized effect is more preferable, further reduces the contact resistance of source contact 31 and/or drain contact.
In order to further enhance the decrystallized efficiency of first part, and less impurity is introduced, so that decrystallized effect
Preferably, in a kind of embodiment of the application, the injection of the non-N-type impurity of third is carried out at low temperature, specifically, at -100 DEG C of temperature
When between~25 DEG C, the non-N-type impurity of above-mentioned third is injected into above-mentioned pre- epitaxial layer.
In another specific embodiment of the application, above-mentioned basis material includes silicon, and the above-mentioned non-N-type impurity of third includes
Silicon and/or germanium.In more specifically a kind of embodiment, above-mentioned basis material is silicon, and the above-mentioned non-N-type impurity of third is germanium.
Certainly, above-mentioned basis material and the non-N-type impurity of above-mentioned third can be identical material, or different
Material, if it is further decrystallized to enable to pre- epitaxial layer to occur by the injection of the non-N-type impurity of third, such as when
When basis material is silicon, the non-N-type impurity of above-mentioned third may be silicon.
Certainly, the basis material in the application is not limited to only include silicon, may also include SiGe and/or SiGe tin etc.,
The non-N-type impurity of third is also not limited to silicon and germanium, can also include others IV race element.
It should be noted that " the Group IV element " of the application refers to the Group IV element in the periodic table of chemical element, packet
Include silicon, germanium and tin etc..
In order to further enhance the decrystallized efficiency of first part, and less impurity is introduced, so that decrystallized effect
Preferably, in a kind of embodiment of the application, when between -100 DEG C~25 DEG C of temperature, above-mentioned is injected into above-mentioned pre- epitaxial layer
Three N-type impurities.
It should be noted that the first above-mentioned N-type impurity, the second N-type impurity and third N-type impurity can be identical, it can also
With difference, those skilled in the art can select identical group V element or different group V elements according to the actual situation.
Specifically, P and/or As etc. can be selected independently in the first N-type impurity, the second N-type impurity and third N-type impurity.
For process simplification, in a kind of embodiment of the application, the first N-type impurity, the second N-type impurity and the 3rd N
Type impurity is P element.
The annealing of the above-mentioned pre- epitaxial layer to injection third N-type impurity in the application can be in the prior art any
Annealing process, those skilled in the art can select according to the actual situation suitable annealing process to anneal.
It is above-mentioned that above-mentioned annealing is implemented using dynamic surface annealing processing in the another embodiment of the application.The dynamic table
Face annealing process can preferably activate N-type impurity.
In order to further decrease the contact resistance of the semiconductor devices, in a kind of embodiment of the application, pre- epitaxial layer
Thickness is between 1~20nm.
In a kind of preferred embodiment of the application, pre- epitaxial layer is respectively set on the exposed surface in source region 11 and drain region
20, and the two pre- epitaxial layers 20 can be formed during same；Then is injected into two pre- epitaxial layers 20 again
Three impurity form epitaxial layer 21；Source electrode finally is set on the surface of the epitaxial layer 21 on the surface of drain region, on 11 surface of source region
On epitaxial layer 21 on drain electrode is set, finally, be heat-treated, heat treatment generally here is to anneal.Specifically formed
Device is as shown in Figure 6.
It should be noted that the setting of the above-mentioned pre- epitaxial layer of the application and the setting technique of electrode layer can be existing
Any one available technique in technology, such as pre- epitaxial layer can use pecvd process, and electrode layer can be steamed using vacuum
Plating method is formed.
In the typical embodiment of the another kind of the application, a kind of semiconductor devices is provided, the semiconductor devices is by upper
Any production method stated is made.
Above-mentioned semiconductor devices, due to being formed using above-mentioned production method, so that its source contact resistance and/or leakage
Contact resistance is smaller, and then the contact resistance of the semiconductor devices is smaller, and electric property is preferable.
In the typical embodiment of another of the application, a kind of semiconductor devices is provided, it as shown in Figure 5 and Figure 6, should
Semiconductor devices includes semiconductor Tooth preparation, epitaxial layer 21 and electrode layer 30, wherein semiconductor Tooth preparation have source region 11 and/
Or drain region, above-mentioned semiconductor Tooth preparation are Ge-based semiconductor Tooth preparation, and the impurity in above-mentioned source region 11 and/or above-mentioned drain region
For the first N-type impurity；Epitaxial layer 21 is located on the surface in above-mentioned source region 11 and/or above-mentioned drain region, above-mentioned epitaxial layer 21 it is separate
The side of above-mentioned semiconductor Tooth preparation has decrystallized part, and above-mentioned epitaxial layer 21 includes basis material and is entrained in above-mentioned base
The second N-type impurity in body material, above-mentioned basis material include the Group IV element of non-Ge, the doping of above-mentioned second N-type impurity
Concentration is 1.0 × 1020cm-3~9.0 × 1021cm-3Between；Electrode layer 30 is located at the separate above-mentioned source region 11 of above-mentioned epitaxial layer 21
Source contact 31 or leakage are formed and/or on the surface in above-mentioned drain region, between an above-mentioned electrode layer 30 and an above-mentioned epitaxial layer 21
Contact.
In above-mentioned semiconductor devices, there is epitaxial layer, and in the epitaxial layer between source region and/or drain region and electrode layer
The concentration of second N-type impurity is higher, so that the concentration of the N-type impurity in the epitaxial layer is 1.0 × 1020cm-3~9.0 ×
1021cm-3Or it is higher, in this way, the activation concentration of the N-type impurity in epitaxial layer is higher than in source region and/or drain region, into
And the contact resistance of source contact and/or drain contact can be reduced；And at least surface part of epitaxial layer is amorphized portion, in this way
So that the N-type impurity concentration of the interface of source region and epitaxial layer is higher, so that contact resistance is smaller；In addition, due to extension
The basis material of layer includes the Group IV element of non-Ge, and the basis material and germanium have good conduction band EcAlignment, and conduction band
Effective mass mcThe contact resistance very little at the interface between epitaxial layer and Ge for being not much different, therefore introducing.Therefore, the semiconductor device
The source of part contacts and/or the contact resistance of drain contact is smaller.
It should be noted that above-mentioned epitaxial layer number can be one, or two, still, art technology
Personnel can select one epitaxial layer of setting or two epitaxial layers according to the actual situation, and when an epitaxial layer is arranged, this is outer
Prolonging layer can be located on the surface in source region or drain region, be the epitaxial layer on the surface of source region shown in Fig. 5.When epitaxial layer has
At two, two epitaxial layers are located on the surface in source region and drain region, are partly led as shown in fig. 6, can further decrease in this way
The contact resistance of body device, and then further promote the electric property of semiconductor devices.
In order to further enhance the concentration of the N-type impurity in epitaxial layer, so that contact resistance is further decreased, the application's
In a kind of embodiment, above-mentioned decrystallized part includes third N-type impurity, and the concentration of the N-type impurity in above-mentioned epitaxial layer is
0.8~1.0C, wherein C is the solid solubility of the N-type impurity in above-mentioned epitaxial layer.
In another embodiment of the application, above-mentioned decrystallized part includes the non-N-type impurity of third, the above-mentioned non-N of third
Type impurity includes Group IV element, and the non-N-type impurity of third can make the non-crystallization degree in epitaxial layer more preferable, can further drop
Low contact resistance, so that the semiconductor devices has lesser dead resistance.
In another specific embodiment of the application, above-mentioned basis material includes silicon, and the above-mentioned non-N-type impurity of third includes
Silicon and/or germanium.In more specifically a kind of embodiment, above-mentioned basis material is silicon, and the above-mentioned non-N-type impurity of third is germanium.
Certainly, the basis material in the application is not limited to only include silicon, may also include SiGe and/or SiGe tin etc.,
The non-N-type impurity of third is also not limited to silicon and germanium, can also include others IV race element.
It should be noted that " the Group IV element " of the application refers to the Group IV element in the periodic table of chemical element, packet
Include silicon, germanium and tin etc..
It should be noted that the first above-mentioned N-type impurity, the second N-type impurity and third N-type impurity can be identical, it can also
With difference, those skilled in the art can select identical group V element or different group V elements according to the actual situation.
Specifically, P and/or As etc. can be selected independently in the first N-type impurity, the second N-type impurity and third N-type impurity.
For process simplification, in a kind of embodiment of the application, above-mentioned first N-type impurity, the second N-type impurity and
Three N-type impurities are P element.
In order to further decrease the contact resistance of the semiconductor devices, in a kind of embodiment of the application, epitaxial layer 21
Thickness is between 1~20nm, and the thickness of amorphized portion is between 1~20nm.
In order to enable those skilled in the art can clearly understand the technical solution of the application, below with reference to tool
The embodiment of body illustrates.
Embodiment
The manufacturing process of semiconductor devices includes:
Ge-based semiconductor Tooth preparation 10 is provided, which includes germanium substrate and the source being arranged in germanium substrate
Area 11 and drain region 12 merely illustrate source region 11 in Fig. 1, and drain region 12 is identical as source region 11, doped with N-type impurity P；
Pre- epitaxial layer 20, and each above-mentioned pre- extension are respectively set on the exposed surface in above-mentioned source region 11 and above-mentioned drain region 12
Layer 20 includes basis material and the second N-type impurity being entrained in above-mentioned basis material, and above-mentioned basis material is silicon, the second N-type
Impurity is P, and the doping concentration of above-mentioned second N-type impurity is 1.0 × 1020cm-3~9.0 × 1021cm-3Between, Fig. 2 only goes out
Pre- epitaxial layer 20 is set on the surface of source region 11；
At -50 DEG C, inject above-mentioned third N-type impurity P into each above-mentioned pre- epitaxial layer 20, the dosage of injection be (0.1~
1)1×1016cm-2, so that the first part 211 far from above-mentioned semiconductor Tooth preparation 10 of each above-mentioned pre- epitaxial layer 20 is decrystallized,
And the doping concentration of the N-type impurity in each above-mentioned pre- epitaxial layer 20 is made to be 0.8~1.0C, wherein C is above-mentioned pre- epitaxial layer 20
In N-type impurity solid solubility, as shown in Figure 2；
It is annealed using dynamic surface annealing processing to each above-mentioned pre- epitaxial layer 20 for injecting above-mentioned third N-type impurity,
The temperature of annealing is 500~1200 DEG C；
The non-N-type impurity Ge of third is injected into each above-mentioned pre- epitaxial layer 20 after annealing, so that each above-mentioned pre- epitaxial layer 20
Far from above-mentioned semiconductor Tooth preparation 10 the second part 212 including first part 211 it is decrystallized, formation epitaxial layer 21, Fig. 3
Show is to inject Ge in pre- epitaxial layer 20 above source region 11.
Electrode layer 30, tool are set on the surface far from above-mentioned source region 11 and/or above-mentioned drain region 12 of above-mentioned epitaxial layer 21
Body is Ti layers, is one electrode layer 30 of formation, specially source electrode above source region 11 shown in Fig. 4；
The above-mentioned semiconductor Tooth preparation 10 for being provided with electrode layer 30 is heat-treated, the temperature of heat treatment is 400-600
DEG C, source contact 31 and drain contact 32 are formed, TiSi is specifically formedx/ Si/Ge is contacted, and is formed source above the source region 11 shown in Fig. 4 and is connect
Touching 31, ultimately forms structure as shown in FIG. 6, on the one hand amorphous silicon layer is repaired on the one hand be consumed during heat treatment.It should
Semiconductor devices further includes grid 40, specifically as shown in Figure 6.Since silicon and germanium have good conduction band EcAlignment, conduction band are effective
Quality mcThe Si/Ge interface resistance very little for being not much different, therefore introducing；And N-type impurity activation concentration is much higher than germanium in silicon, so this
The TiSi formed in embodimentxTiSi is compared in/Si/Ge contactx/ Ge contact resistivity is effectively reduced.
It can be seen from the above description that the application the above embodiments realize following technical effect:
1), in the production method of the application, the extension doped with N-type impurity is set on the surface in source region and/or drain region
Layer, and the concentration of the N-type impurity in the epitaxial layer is higher, 1.0 × 1020cm-3~9.0 × 1021cm-3Or it is higher, in this way,
So that the activation concentration of the N-type impurity in epitaxial layer is higher than in source region and/or drain region, so can reduce source contact and/or
The contact resistance of drain contact；In addition, form decrystallized part in the epitaxial layer in the production method, so that electrode layer and non-
The concentration of n-type doping impurity is higher in the part of crystallization contact, so that contact resistance is smaller；Furthermore due to epitaxial layer
Basis material includes the Group IV element of non-Ge, and the basis material and germanium have good conduction band EcAlignment, and conduction band is effective
Quality mcThe contact resistance very little at the interface between epitaxial layer and Ge for being not much different, therefore introducing.Therefore, which forms
Source contact and/or drain contact contact resistance it is smaller.
2), the semiconductor devices of the application, due to being formed using above-mentioned production method, so that its source contact resistance
And/or drain contact resistance is smaller, and then the contact resistance of the semiconductor devices is smaller, electric property is preferable.
3), the semiconductor devices of the application has epitaxial layer, and the epitaxial layer between source region and/or drain region and electrode layer
In the second N-type impurity concentration it is higher, so that the concentration of the N-type impurity in the epitaxial layer is 1.0 × 1020cm-3~
9.0×1021cm-3Or it is higher, in this way, being higher than the activation concentration of the N-type impurity in epitaxial layer in source region and/or drain region
, and then the contact resistance of source contact and/or drain contact can be reduced；And at least surface part of epitaxial layer is decrystallized portion
Point, so that the N-type impurity concentration of the interface of source region and epitaxial layer is higher, so that contact resistance is smaller；In addition, by
In the Group IV element that the basis material of epitaxial layer includes non-Ge, the basis material and germanium have good conduction band EcAlignment,
And conduction band effective mass mcThe contact resistance very little at the interface between epitaxial layer and Ge for being not much different, therefore introducing.It therefore, should be partly
The source of conductor device contacts and/or the contact resistance of drain contact is smaller.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (11)
1. a kind of production method of semiconductor devices, which is characterized in that the production method includes:
The semiconductor Tooth preparation for having source region and/or drain region is provided, the semiconductor Tooth preparation is Ge-based semiconductor Tooth preparation, and
The impurity in the source region and/or the drain region is the first N-type impurity；
Pre- epitaxial layer is set on the exposed surface in the source region and/or the drain region, and the pre- epitaxial layer includes matrix material
The second N-type impurity expected and be entrained in described matrix material, described matrix material include the Group IV element of non-Ge, and described
The doping concentration of two N-type impurities is 1.0 × 1020cm-3~9.0 × 1021cm-3Between；
Third impurity is injected into the pre- epitaxial layer, so that the part far from the semiconductor Tooth preparation of the pre- epitaxial layer
It is decrystallized, so that the pre- epitaxial layer forms epitaxial layer；
Electrode layer is set on the surface far from the source region and/or the drain region of the epitaxial layer；
The semiconductor Tooth preparation for being provided with electrode layer is heat-treated, source contact and/or drain contact are formed.
2. manufacturing method according to claim 1, which is characterized in that the third impurity includes third N-type impurity, to institute
It states and injects the process of the third impurity in pre- epitaxial layer and include:
The third N-type impurity is injected into the pre- epitaxial layer, so that the separate semiconductor preparation of the pre- epitaxial layer
The first part of body is decrystallized, and the doping concentration of the N-type impurity in the pre- epitaxial layer is made to be 0.8~1.0C, wherein C
For the solid solubility of the N-type impurity in the pre- epitaxial layer；
It anneals to the pre- epitaxial layer for injecting the third N-type impurity.
3. manufacturing method according to claim 1, which is characterized in that the third impurity includes the non-N-type impurity of third, to
The process of the third impurity is injected in the pre- epitaxial layer further include:
The non-N-type impurity of third is injected into the pre- epitaxial layer, at least so that the pre- epitaxial layer is pre- far from the semiconductor
The second part of standby body is decrystallized, and the non-N-type impurity of the third includes Group IV element.
4. manufacturing method according to claim 1, which is characterized in that the third impurity includes third N-type impurity and
Three non-N-type impurities inject the process of the third impurity into the pre- epitaxial layer further include:
The third N-type impurity is injected into the pre- epitaxial layer, so that the separate semiconductor preparation of the pre- epitaxial layer
The first part of body is decrystallized, and the doping concentration of the N-type impurity in the pre- epitaxial layer is made to be 0.8~1.0C, wherein C
For the solid solubility of the N-type impurity in the pre- epitaxial layer；
It anneals to the pre- epitaxial layer for injecting the third N-type impurity；
The non-N-type impurity of third is injected into the pre- epitaxial layer after annealing, at least so that the pre- epitaxial layer is separate described
The second part including first part of semiconductor Tooth preparation is decrystallized, and the non-N-type impurity of the third includes Group IV element.
5. production method according to claim 3 or 4, which is characterized in that when between -100 DEG C~25 DEG C of temperature, to institute
It states and injects the non-N-type impurity of the third in pre- epitaxial layer, preferably described matrix material includes silicon, the non-N-type impurity packet of third
Include silicon and/or germanium.
6. the production method according to any one of claim 2 or 4, which is characterized in that -100 DEG C~25 DEG C of temperature it
Between when, the third N-type impurity is injected into the pre- epitaxial layer.
7. the production method according to any one of claim 2 or 4, which is characterized in that use dynamic surface annealing processing
Implement the annealing, the temperature of the preferably described annealing is between 500~1200 DEG C.
8. a kind of semiconductor devices, which is characterized in that semiconductor devices system as described in any one of claims 1 to 7
It is made as method.
9. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Semiconductor Tooth preparation has source region and/or drain region, and the semiconductor Tooth preparation is Ge-based semiconductor Tooth preparation, and described
The impurity in source region and/or the drain region is the first N-type impurity；
Epitaxial layer, on the surface in the source region and/or the drain region, the separate semiconductor Tooth preparation of the epitaxial layer
Side there is decrystallized part, the epitaxial layer includes basis material and the second N-type for being entrained in described matrix material
Impurity, described matrix material include the Group IV element of non-Ge, and the doping concentration of second N-type impurity is 1.0 × 1020cm-3
~9.0 × 1021cm-3Between；
Electrode layer, on surface of the epitaxial layer far from the source region and/or the drain region, the electrode layer and
One epitaxial layer forms source contact or drain contact.
10. semiconductor devices according to claim 9, which is characterized in that the decrystallized part includes that third N-type is miscellaneous
Matter, and the concentration of the N-type impurity in the epitaxial layer is 0.8~1.0C, wherein C is consolidating for the N-type impurity in the epitaxial layer
Solubility.
11. semiconductor devices according to claim 9 or 10, which is characterized in that the decrystallized part includes third
Non- N-type impurity, the non-N-type impurity of third includes Group IV element.
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| US20120138928A1 (en) * | 2010-12-06 | 2012-06-07 | Katholieke Universiteit Leuven, K.U. Leuven R&D | Method of Manufacturing Low Resistivity Contacts on n-Type Germanium |
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